diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -703,6 +703,14 @@
                           list<dag> pattern=[]> {
   def _noexch : MVE_VMLAMLSDAV<iname, suffix, iops, cstr, sz,
                             bit_28, A, 0b0, bit_8, bit_0, pattern>;
+
+  // Architectural restriction: the add instructions in this family
+  // (with bit_0 == 0) can't both use the exchange variant (with an
+  // 'x' in the name) *and* take an unsigned type.
+  //
+  // I use a 'foreach' to condition this out because Tablegen has no
+  // 'if' statement.
+  foreach dummy = !if(!and(bit_28,!eq(bit_0,0)), []<int>, [1]) in
   def _exch   : MVE_VMLAMLSDAV<iname # "x", suffix, iops, cstr, sz,
                             bit_28, A, 0b1, bit_8, bit_0, pattern>;
 }
@@ -778,6 +786,10 @@
                               bit bit_8, bit bit_0, list<dag> pattern=[]> {
   def _noexch : MVE_VMLALDAVBase<iname, suffix, iops, cstr, sz,
                                bit_28, A, 0b0, bit_8, bit_0, pattern>;
+
+  // Similarly to MVE_VMLAMLSDAV_X, condition out the combination of
+  // addition, 'x' variant, and an unsigned type.
+  foreach dummy = !if(!and(bit_28,!eq(bit_0,0)), []<int>, [1]) in
   def _exch   : MVE_VMLALDAVBase<iname # "x", suffix, iops, cstr, sz,
                                bit_28, A, 0b1, bit_8, bit_0, pattern>;
 }
diff --git a/llvm/test/MC/ARM/mve-reductions.s b/llvm/test/MC/ARM/mve-reductions.s
--- a/llvm/test/MC/ARM/mve-reductions.s
+++ b/llvm/test/MC/ARM/mve-reductions.s
@@ -130,6 +130,42 @@
 # CHECK: vmladavax.s16 lr, q0, q7  @ encoding: [0xf0,0xee,0x2e,0xfe]
 vmladavax.s16 lr, q0, q7
 
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmladavax.u16 r0, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmladavx.u16 r0, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmladavax.u32 r0, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmladavx.u32 r0, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmladavax.u8 r0, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmladavx.u8 r0, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmlaldavax.u16 r2, r3, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmlaldavx.u16 r2, r3, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmlaldavax.u32 r2, r3, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vmlaldavx.u32 r2, r3, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vrmlaldavhax.u32 r2, r3, q4, q5
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vrmlaldavhx.u32 r2, r3, q4, q5
+
 # CHECK: vmlav.s8 lr, q3, q0  @ encoding: [0xf6,0xee,0x00,0xef]
 vmladav.s8 lr, q3, q0
 
diff --git a/llvm/test/MC/Disassembler/ARM/mve-reductions.txt b/llvm/test/MC/Disassembler/ARM/mve-reductions.txt
--- a/llvm/test/MC/Disassembler/ARM/mve-reductions.txt
+++ b/llvm/test/MC/Disassembler/ARM/mve-reductions.txt
@@ -1,4 +1,5 @@
-# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s 2> %t | FileCheck %s
+# RUN: FileCheck --check-prefix=ERROR < %t %s
 # RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
 # RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
 
@@ -182,6 +183,42 @@
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0xf0,0xee,0x2e,0xfe]
 
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf8,0xfe,0x2a,0x1e]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf8,0xfe,0x0a,0x1e]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf9,0xfe,0x2a,0x1e]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf9,0xfe,0x0a,0x1e]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf8,0xfe,0x2a,0x1f]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf8,0xfe,0x0a,0x1f]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xfe,0x2a,0x3e]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xfe,0x0a,0x3e]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x99,0xfe,0x2a,0x3e]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x99,0xfe,0x0a,0x3e]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xfe,0x2a,0x3f]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x98,0xfe,0x0a,0x3f]
+
 # CHECK: vmlav.s8 lr, q3, q0  @ encoding: [0xf6,0xee,0x00,0xef]
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0xf6,0xee,0x00,0xef]