Index: llvm/trunk/lib/Target/PowerPC/P9InstrResources.td
===================================================================
--- llvm/trunk/lib/Target/PowerPC/P9InstrResources.td
+++ llvm/trunk/lib/Target/PowerPC/P9InstrResources.td
@@ -125,8 +125,8 @@
     (instregex "SRAD(I)?$"),
     (instregex "EXTSWSLI_32_64$"),
     (instregex "MFV(S)?RD$"),
-    (instregex "MTVSRD$"),
-    (instregex "MTVSRW(A|Z)$"),
+    (instregex "MTV(S)?RD$"),
+    (instregex "MTV(S)?RW(A|Z)$"),
     (instregex "CMP(WI|LWI|W|LW)(8)?$"),
     (instregex "CMP(L)?D(I)?$"),
     (instregex "SUBF(I)?C(8)?$"),
@@ -159,6 +159,7 @@
     XSNEGDP,
     XSCPSGNDP,
     MFVSRWZ,
+    MFVRWZ,
     EXTSWSLI,
     SRADI_32,
     RLDIC,
Index: llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
===================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
@@ -1593,16 +1593,33 @@
   def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT),
                                "mfvsrwz $rA, $XT", IIC_VecGeneral,
                                [(set i32:$rA, (PPCmfvsr f64:$XT))]>;
+  let isCodeGenOnly = 1 in
+  def MFVRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsrc:$XT),
+                               "mfvsrwz $rA, $XT", IIC_VecGeneral,
+                               []>;
   def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$rA),
                               "mtvsrd $XT, $rA", IIC_VecGeneral,
                               [(set f64:$XT, (PPCmtvsra i64:$rA))]>,
       Requires<[In64BitMode]>;
+  let isCodeGenOnly = 1 in
+  def MTVRD : XX1_RS6_RD5_XO<31, 179, (outs vsrc:$XT), (ins g8rc:$rA),
+                              "mtvsrd $XT, $rA", IIC_VecGeneral,
+                              []>,
+      Requires<[In64BitMode]>;
   def MTVSRWA : XX1_RS6_RD5_XO<31, 211, (outs vsfrc:$XT), (ins gprc:$rA),
                                "mtvsrwa $XT, $rA", IIC_VecGeneral,
                                [(set f64:$XT, (PPCmtvsra i32:$rA))]>;
+  let isCodeGenOnly = 1 in
+  def MTVRWA : XX1_RS6_RD5_XO<31, 211, (outs vsrc:$XT), (ins gprc:$rA),
+                               "mtvsrwa $XT, $rA", IIC_VecGeneral,
+                               []>;
   def MTVSRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsfrc:$XT), (ins gprc:$rA),
                                "mtvsrwz $XT, $rA", IIC_VecGeneral,
                                [(set f64:$XT, (PPCmtvsrz i32:$rA))]>;
+  let isCodeGenOnly = 1 in
+  def MTVRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsrc:$XT), (ins gprc:$rA),
+                               "mtvsrwz $XT, $rA", IIC_VecGeneral,
+                               []>;
 } // HasDirectMove
 
 let Predicates = [IsISA3_0, HasDirectMove] in {
@@ -1626,6 +1643,22 @@
                 (MFVRD g8rc:$rA, vrrc:$XT), 0>;
 def : InstAlias<"mffprd $rA, $src",
                 (MFVSRD g8rc:$rA, f8rc:$src)>;
+def : InstAlias<"mtvrd $XT, $rA",
+                (MTVRD vrrc:$XT, g8rc:$rA), 0>;
+def : InstAlias<"mtfprd $dst, $rA",
+                (MTVSRD f8rc:$dst, g8rc:$rA)>;
+def : InstAlias<"mfvrwz $rA, $XT",
+                (MFVRWZ gprc:$rA, vrrc:$XT), 0>;
+def : InstAlias<"mffprwz $rA, $src",
+                (MFVSRWZ gprc:$rA, f8rc:$src)>;
+def : InstAlias<"mtvrwa $XT, $rA",
+                (MTVRWA vrrc:$XT, gprc:$rA), 0>;
+def : InstAlias<"mtfprwa $dst, $rA",
+                (MTVSRWA f8rc:$dst, gprc:$rA)>;
+def : InstAlias<"mtvrwz $XT, $rA",
+                (MTVRWZ vrrc:$XT, gprc:$rA), 0>;
+def : InstAlias<"mtfprwz $dst, $rA",
+                (MTVSRWZ f8rc:$dst, gprc:$rA)>;
 
 /*  Direct moves of various widths from GPR's into VSR's. Each move lines
     the value up into element 0 (both BE and LE). Namely, entities smaller than
Index: llvm/trunk/test/CodeGen/PowerPC/bitcasts-direct-move.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/bitcasts-direct-move.ll
+++ llvm/trunk/test/CodeGen/PowerPC/bitcasts-direct-move.ll
@@ -40,7 +40,7 @@
   ret double %0
 ; CHECK-P7: std 3,
 ; CHECK-P7: lfd 1,
-; CHECK: mtvsrd 1, 3
+; CHECK: mtfprd 1, 3
 }
 
 define zeroext i32 @f32toi32u(float %a) {
@@ -80,5 +80,5 @@
   ret double %0
 ; CHECK-P7: std 3,
 ; CHECK-P7: lfd 1,
-; CHECK: mtvsrd 1, 3
+; CHECK: mtfprd 1, 3
 }
Index: llvm/trunk/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
+++ llvm/trunk/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
@@ -112,7 +112,7 @@
   %2 = call fp128 @llvm.ppc.scalar.insert.exp.qp(fp128 %0, i64 %1)
   ret fp128 %2
 ; CHECK-LABEL: insert_exp_qp
-; CHECK-DAG: mtvsrd [[FPREG:f[0-9]+]], r3
+; CHECK-DAG: mtfprd [[FPREG:f[0-9]+]], r3
 ; CHECK-DAG: lxvx [[VECREG:v[0-9]+]]
 ; CHECK: xsiexpqp v2, [[VECREG]], [[FPREG]]
 ; CHECK: blr
Index: llvm/trunk/test/CodeGen/PowerPC/direct-move-profit.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/direct-move-profit.ll
+++ llvm/trunk/test/CodeGen/PowerPC/direct-move-profit.ll
@@ -69,7 +69,7 @@
   store i32 %add, i32* %arrayidx6, align 4, !tbaa !1
   ret void
 
-; CHECK: mtvsrwa
+; CHECK: mtfprwa
 ; CHECK: blr
 
 }
Index: llvm/trunk/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll
+++ llvm/trunk/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll
@@ -25,7 +25,7 @@
 define float @_Z6testfcc(i8 zeroext %arg) {
 ; CHECK-LABEL: _Z6testfcc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrwz f0, r3
+; CHECK-NEXT:    mtfprwz f0, r3
 ; CHECK-NEXT:    stb r3, -1(r1)
 ; CHECK-NEXT:    xscvuxdsp f1, f0
 ; CHECK-NEXT:    blr
@@ -58,7 +58,7 @@
 define double @_Z6testdcc(i8 zeroext %arg) {
 ; CHECK-LABEL: _Z6testdcc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrwz f0, r3
+; CHECK-NEXT:    mtfprwz f0, r3
 ; CHECK-NEXT:    stb r3, -1(r1)
 ; CHECK-NEXT:    xscvuxddp f1, f0
 ; CHECK-NEXT:    blr
@@ -91,7 +91,7 @@
 define float @_Z7testfuch(i8 zeroext %arg) {
 ; CHECK-LABEL: _Z7testfuch:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrwz f0, r3
+; CHECK-NEXT:    mtfprwz f0, r3
 ; CHECK-NEXT:    stb r3, -1(r1)
 ; CHECK-NEXT:    xscvuxdsp f1, f0
 ; CHECK-NEXT:    blr
@@ -124,7 +124,7 @@
 define double @_Z7testduch(i8 zeroext %arg) {
 ; CHECK-LABEL: _Z7testduch:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrwz f0, r3
+; CHECK-NEXT:    mtfprwz f0, r3
 ; CHECK-NEXT:    stb r3, -1(r1)
 ; CHECK-NEXT:    xscvuxddp f1, f0
 ; CHECK-NEXT:    blr
@@ -142,7 +142,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfs f1, -4(r1)
-; CHECK-NEXT:    mfvsrwz r3, f0
+; CHECK-NEXT:    mffprwz r3, f0
 ; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 entry:
@@ -157,7 +157,7 @@
 define float @_Z6testfss(i16 signext %arg) {
 ; CHECK-LABEL: _Z6testfss:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrwa f0, r3
+; CHECK-NEXT:    mtfprwa f0, r3
 ; CHECK-NEXT:    sth r3, -2(r1)
 ; CHECK-NEXT:    xscvsxdsp f1, f0
 ; CHECK-NEXT:    blr
@@ -175,7 +175,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfd f1, -8(r1)
-; CHECK-NEXT:    mfvsrwz r3, f0
+; CHECK-NEXT:    mffprwz r3, f0
 ; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 entry:
@@ -190,7 +190,7 @@
 define double @_Z6testdss(i16 signext %arg) {
 ; CHECK-LABEL: _Z6testdss:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrwa f0, r3
+; CHECK-NEXT:    mtfprwa f0, r3
 ; CHECK-NEXT:    sth r3, -2(r1)
 ; CHECK-NEXT:    xscvsxddp f1, f0
 ; CHECK-NEXT:    blr
@@ -223,7 +223,7 @@
 define float @_Z7testfust(i16 zeroext %arg) {
 ; CHECK-LABEL: _Z7testfust:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrwz f0, r3
+; CHECK-NEXT:    mtfprwz f0, r3
 ; CHECK-NEXT:    sth r3, -2(r1)
 ; CHECK-NEXT:    xscvuxdsp f1, f0
 ; CHECK-NEXT:    blr
@@ -256,7 +256,7 @@
 define double @_Z7testdust(i16 zeroext %arg) {
 ; CHECK-LABEL: _Z7testdust:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrwz f0, r3
+; CHECK-NEXT:    mtfprwz f0, r3
 ; CHECK-NEXT:    sth r3, -2(r1)
 ; CHECK-NEXT:    xscvuxddp f1, f0
 ; CHECK-NEXT:    blr
@@ -274,7 +274,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfs f1, -4(r1)
-; CHECK-NEXT:    mfvsrwz r3, f0
+; CHECK-NEXT:    mffprwz r3, f0
 ; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 entry:
@@ -289,7 +289,7 @@
 define float @_Z6testfii(i32 signext %arg) {
 ; CHECK-LABEL: _Z6testfii:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrwa f0, r3
+; CHECK-NEXT:    mtfprwa f0, r3
 ; CHECK-NEXT:    stw r3, -4(r1)
 ; CHECK-NEXT:    xscvsxdsp f1, f0
 ; CHECK-NEXT:    blr
@@ -307,7 +307,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpsxws f0, f1
 ; CHECK-NEXT:    stfd f1, -8(r1)
-; CHECK-NEXT:    mfvsrwz r3, f0
+; CHECK-NEXT:    mffprwz r3, f0
 ; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
 entry:
@@ -322,7 +322,7 @@
 define double @_Z6testdii(i32 signext %arg) {
 ; CHECK-LABEL: _Z6testdii:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrwa f0, r3
+; CHECK-NEXT:    mtfprwa f0, r3
 ; CHECK-NEXT:    stw r3, -4(r1)
 ; CHECK-NEXT:    xscvsxddp f1, f0
 ; CHECK-NEXT:    blr
@@ -355,7 +355,7 @@
 define float @_Z7testfuij(i32 zeroext %arg) {
 ; CHECK-LABEL: _Z7testfuij:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrwz f0, r3
+; CHECK-NEXT:    mtfprwz f0, r3
 ; CHECK-NEXT:    stw r3, -4(r1)
 ; CHECK-NEXT:    xscvuxdsp f1, f0
 ; CHECK-NEXT:    blr
@@ -388,7 +388,7 @@
 define double @_Z7testduij(i32 zeroext %arg) {
 ; CHECK-LABEL: _Z7testduij:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrwz f0, r3
+; CHECK-NEXT:    mtfprwz f0, r3
 ; CHECK-NEXT:    stw r3, -4(r1)
 ; CHECK-NEXT:    xscvuxddp f1, f0
 ; CHECK-NEXT:    blr
@@ -420,7 +420,7 @@
 define float @_Z7testfllx(i64 %arg) {
 ; CHECK-LABEL: _Z7testfllx:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrd f0, r3
+; CHECK-NEXT:    mtfprd f0, r3
 ; CHECK-NEXT:    std r3, -8(r1)
 ; CHECK-NEXT:    xscvsxdsp f1, f0
 ; CHECK-NEXT:    blr
@@ -452,7 +452,7 @@
 define double @_Z7testdllx(i64 %arg) {
 ; CHECK-LABEL: _Z7testdllx:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrd f0, r3
+; CHECK-NEXT:    mtfprd f0, r3
 ; CHECK-NEXT:    std r3, -8(r1)
 ; CHECK-NEXT:    xscvsxddp f1, f0
 ; CHECK-NEXT:    blr
@@ -484,7 +484,7 @@
 define float @_Z8testfully(i64 %arg) {
 ; CHECK-LABEL: _Z8testfully:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrd f0, r3
+; CHECK-NEXT:    mtfprd f0, r3
 ; CHECK-NEXT:    std r3, -8(r1)
 ; CHECK-NEXT:    xscvuxdsp f1, f0
 ; CHECK-NEXT:    blr
@@ -516,7 +516,7 @@
 define double @_Z8testdully(i64 %arg) {
 ; CHECK-LABEL: _Z8testdully:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mtvsrd f0, r3
+; CHECK-NEXT:    mtfprd f0, r3
 ; CHECK-NEXT:    std r3, -8(r1)
 ; CHECK-NEXT:    xscvuxddp f1, f0
 ; CHECK-NEXT:    blr
Index: llvm/trunk/test/CodeGen/PowerPC/fp64-to-int16.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/fp64-to-int16.ll
+++ llvm/trunk/test/CodeGen/PowerPC/fp64-to-int16.ll
@@ -6,7 +6,7 @@
 ; CHECK-LABEL: Test:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xscvdpsxws 0, 1
-; CHECK-NEXT:    mfvsrwz 3, 0
+; CHECK-NEXT:    mffprwz 3, 0
 ; CHECK-NEXT:    xori 3, 3, 65534
 ; CHECK-NEXT:    cntlzw 3, 3
 ; CHECK-NEXT:    srwi 3, 3, 5
Index: llvm/trunk/test/CodeGen/PowerPC/gpr-vsr-spill.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/gpr-vsr-spill.ll
+++ llvm/trunk/test/CodeGen/PowerPC/gpr-vsr-spill.ll
@@ -17,7 +17,7 @@
 ; CHECK: @foo
 ; CHECK: mr [[NEWREG:[0-9]+]], 3
 ; CHECK: mr [[REG1:[0-9]+]], 4
-; CHECK: mtvsrd [[NEWREG2:[0-9]+]], 4
+; CHECK: mtfprd [[NEWREG2:[0-9]+]], 4
 ; CHECK: add {{[0-9]+}}, [[NEWREG]], [[REG1]]
 ; CHECK: mffprd [[REG2:[0-9]+]], [[NEWREG2]]
 ; CHECK: add {{[0-9]+}}, [[REG2]], [[NEWREG]]
Index: llvm/trunk/test/CodeGen/PowerPC/inlineasm-extendedmne.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/inlineasm-extendedmne.ll
+++ llvm/trunk/test/CodeGen/PowerPC/inlineasm-extendedmne.ll
@@ -0,0 +1,72 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names  \
+; RUN:     -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
+
+define dso_local void @foo()  {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mfvsrd r0, vs33
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mffprd r0, f3
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mfvsrd r0, vs34
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mfvsrwz r0, vs33
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mffprwz r0, f3
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mfvsrwz r0, vs34
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mtvsrd vs33, r0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mtfprd f3, r0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mtvsrd vs34, r0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mtvsrwa vs33, r0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mtfprwa f3, r0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mtvsrwa vs34, r0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mtvsrwz vs33, r0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mtfprwz f3, r0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    mtvsrwz vs34, r0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    blr
+entry:
+  call void asm sideeffect "mfvsrd 0,33", ""()
+  call void asm sideeffect "mffprd 0,3", ""()
+  call void asm sideeffect "mfvrd  0,2", ""()
+  call void asm sideeffect "mfvsrwz 0,33", ""()
+  call void asm sideeffect "mffprwz 0,3", ""()
+  call void asm sideeffect "mfvrwz  0,2", ""()
+  call void asm sideeffect "mtvsrd 33,0", ""()
+  call void asm sideeffect "mtfprd 3,0", ""()
+  call void asm sideeffect "mtvrd  2,0", ""()
+  call void asm sideeffect "mtvsrwa 33,0", ""()
+  call void asm sideeffect "mtfprwa 3,0", ""()
+  call void asm sideeffect "mtvrwa  2,0", ""()
+  call void asm sideeffect "mtvsrwz 33,0", ""()
+  call void asm sideeffect "mtfprwz 3,0", ""()
+  call void asm sideeffect "mtvrwz  2,0", ""()
+  ret void
+}
+
Index: llvm/trunk/test/CodeGen/PowerPC/ppc64-align-long-double.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/ppc64-align-long-double.ll
+++ llvm/trunk/test/CodeGen/PowerPC/ppc64-align-long-double.ll
@@ -45,8 +45,8 @@
 ;
 ; CHECK-P9-LABEL: test:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrd 1, 5
-; CHECK-P9-NEXT:    mtvsrd 2, 6
+; CHECK-P9-NEXT:    mtfprd 1, 5
+; CHECK-P9-NEXT:    mtfprd 2, 6
 ; CHECK-P9-NEXT:    std 6, 72(1)
 ; CHECK-P9-NEXT:    std 5, 64(1)
 ; CHECK-P9-NEXT:    std 3, 48(1)
Index: llvm/trunk/test/CodeGen/PowerPC/pr26180.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/pr26180.ll
+++ llvm/trunk/test/CodeGen/PowerPC/pr26180.ll
@@ -11,7 +11,7 @@
 ; CHECK: stfd [[REG0]], [[OFF:.*]](1)
 ; CHECK: lwz {{[0-9]*}}, [[OFF]](1)
 ; GENERIC: xscvdpuxws [[REG0:[0-9]+]], 1
-; GENERIC: mfvsrwz  {{[0-9]*}}, [[REG0]]
+; GENERIC: mffprwz  {{[0-9]*}}, [[REG0]]
 }
 
 define i32 @bad1(float %x) {
@@ -23,5 +23,5 @@
 ; CHECK: stfd [[REG0]], [[OFF:.*]](1)
 ; CHECK: lwa {{[0-9]*}}, [[OFF]](1)
 ; GENERIC: xscvdpsxws [[REG0:[0-9]+]], 1
-; GENERIC: mfvsrwz  {{[0-9]*}}, [[REG0]]
+; GENERIC: mffprwz  {{[0-9]*}}, [[REG0]]
 }
Index: llvm/trunk/test/CodeGen/PowerPC/pr31144.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/pr31144.ll
+++ llvm/trunk/test/CodeGen/PowerPC/pr31144.ll
@@ -10,7 +10,7 @@
   ret void
 
 ; CHECK-LABEL: @foo1
-; CHECK:     mtvsrwz
+; CHECK:     mtfprwz
 }
 
 define void @foo2(i16* %p) {
@@ -21,6 +21,6 @@
   ret void
 
 ; CHECK-LABEL: @foo2
-; CHECK:       mtvsrwz
+; CHECK:       mtfprwz
 }
 
Index: llvm/trunk/test/CodeGen/PowerPC/select-addrRegRegOnly.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/select-addrRegRegOnly.ll
+++ llvm/trunk/test/CodeGen/PowerPC/select-addrRegRegOnly.ll
@@ -23,7 +23,7 @@
 ; CHECK-NEXT:    lwz 4, 8(3)
 ; CHECK-NEXT:    lwz 3, 12(3)
 ; CHECK-NEXT:    add 3, 3, 4
-; CHECK-NEXT:    mtvsrwa 0, 3
+; CHECK-NEXT:    mtfprwa 0, 3
 ; CHECK-NEXT:    xscvsxdsp 1, 0
 ; CHECK-NEXT:    blr
 entry:
Index: llvm/trunk/test/CodeGen/PowerPC/setrnd.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/setrnd.ll
+++ llvm/trunk/test/CodeGen/PowerPC/setrnd.ll
@@ -26,7 +26,7 @@
 ; CHECK-DAG:   mffs 1 
 ; CHECK-DAG:   mffprd [[REG1:[0-9]+]], 1 
 ; CHECK-DAG:   rldimi [[REG1]], 3, 0, 62
-; CHECK-DAG:   mtvsrd [[REG2:[0-9]+]], [[REG1]]
+; CHECK-DAG:   mtfprd [[REG2:[0-9]+]], [[REG1]]
 ; CHECK-DAG:   mtfsf 255, [[REG2]] 
 ; CHECK:       blr
 
Index: llvm/trunk/test/CodeGen/PowerPC/store_fptoi.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/store_fptoi.ll
+++ llvm/trunk/test/CodeGen/PowerPC/store_fptoi.ll
@@ -66,7 +66,7 @@
 ; CHECK-PWR8-LABEL: dpConv2shw
 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
 ; CHECK-PWR8-NEXT: blr
 }
@@ -88,7 +88,7 @@
 ; CHECK-PWR8-LABEL: dpConv2sb
 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
 ; CHECK-PWR8-NEXT: blr
 }
@@ -152,7 +152,7 @@
 ; CHECK-PWR8-LABEL: spConv2shw
 ; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
 ; CHECK-PWR8-NEXT: blr
 }
@@ -174,7 +174,7 @@
 ; CHECK-PWR8-LABEL: spConv2sb
 ; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
 ; CHECK-PWR8-NEXT: blr
 }
@@ -253,7 +253,7 @@
 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: sthx [[REG]], 4, 5
 ; CHECK-PWR8-NEXT: blr
 }
@@ -278,7 +278,7 @@
 ; CHECK-PWR8-LABEL: dpConv2sb_x
 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5
 ; CHECK-PWR8-NEXT: blr
 }
@@ -357,7 +357,7 @@
 ; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG2:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG2:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: sthx [[REG2]], 4, [[REG]]
 ; CHECK-PWR8-NEXT: blr
 }
@@ -382,7 +382,7 @@
 ; CHECK-PWR8-LABEL: spConv2sb_x
 ; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5
 ; CHECK-PWR8-NEXT: blr
 }
@@ -450,7 +450,7 @@
 ; CHECK-PWR8-LABEL: dpConv2uhw
 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
 ; CHECK-PWR8-NEXT: blr
 }
@@ -472,7 +472,7 @@
 ; CHECK-PWR8-LABEL: dpConv2ub
 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
 ; CHECK-PWR8-NEXT: blr
 }
@@ -536,7 +536,7 @@
 ; CHECK-PWR8-LABEL: spConv2uhw
 ; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
 ; CHECK-PWR8-NEXT: blr
 }
@@ -558,7 +558,7 @@
 ; CHECK-PWR8-LABEL: spConv2ub
 ; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
 ; CHECK-PWR8-NEXT: blr
 }
@@ -637,7 +637,7 @@
 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: sthx [[REG]], 4, 5
 ; CHECK-PWR8-NEXT: blr
 }
@@ -662,7 +662,7 @@
 ; CHECK-PWR8-LABEL: dpConv2ub_x
 ; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5
 ; CHECK-PWR8-NEXT: blr
 }
@@ -741,7 +741,7 @@
 ; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG2:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG2:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: sthx [[REG2]], 4, [[REG]]
 ; CHECK-PWR8-NEXT: blr
 }
@@ -766,7 +766,7 @@
 ; CHECK-PWR8-LABEL: spConv2ub_x
 ; CHECK-PWR8: lfsx [[LD:[0-9]+]], 0, 3
 ; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
-; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
+; CHECK-PWR8-NEXT: mffprwz [[REG:[0-9]+]], [[CONV]]
 ; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5
 ; CHECK-PWR8-NEXT: blr
 }
Index: llvm/trunk/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll
+++ llvm/trunk/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll
@@ -17,11 +17,11 @@
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31
-; P9BE-NEXT:    mtvsrwz f0, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31
-; P9BE-NEXT:    mtvsrwz f1, r3
+; P9BE-NEXT:    mtfprwz f1, r3
 ; P9BE-NEXT:    xscvuxddp f0, f0
 ; P9BE-NEXT:    xscvuxddp f1, f1
 ; P9BE-NEXT:    xxmrghd v2, vs0, vs1
@@ -32,11 +32,11 @@
 ; P9LE-NEXT:    li r3, 0
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    rlwinm r3, r3, 0, 16, 31
-; P9LE-NEXT:    mtvsrwz f0, r3
+; P9LE-NEXT:    mtfprwz f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    rlwinm r3, r3, 0, 16, 31
-; P9LE-NEXT:    mtvsrwz f1, r3
+; P9LE-NEXT:    mtfprwz f1, r3
 ; P9LE-NEXT:    xscvuxddp f0, f0
 ; P9LE-NEXT:    xscvuxddp f1, f1
 ; P9LE-NEXT:    xxmrghd v2, vs1, vs0
@@ -49,8 +49,8 @@
 ; P8BE-NEXT:    rldicl r3, r3, 32, 48
 ; P8BE-NEXT:    rlwinm r4, r4, 0, 16, 31
 ; P8BE-NEXT:    rlwinm r3, r3, 0, 16, 31
-; P8BE-NEXT:    mtvsrwz f0, r4
-; P8BE-NEXT:    mtvsrwz f1, r3
+; P8BE-NEXT:    mtfprwz f0, r4
+; P8BE-NEXT:    mtfprwz f1, r3
 ; P8BE-NEXT:    xscvuxddp f0, f0
 ; P8BE-NEXT:    xscvuxddp f1, f1
 ; P8BE-NEXT:    xxmrghd v2, vs0, vs1
@@ -64,8 +64,8 @@
 ; P8LE-NEXT:    rldicl r3, r3, 48, 48
 ; P8LE-NEXT:    rlwinm r4, r4, 0, 16, 31
 ; P8LE-NEXT:    rlwinm r3, r3, 0, 16, 31
-; P8LE-NEXT:    mtvsrwz f0, r4
-; P8LE-NEXT:    mtvsrwz f1, r3
+; P8LE-NEXT:    mtfprwz f0, r4
+; P8LE-NEXT:    mtfprwz f1, r3
 ; P8LE-NEXT:    xscvuxddp f0, f0
 ; P8LE-NEXT:    xscvuxddp f1, f1
 ; P8LE-NEXT:    xxmrghd v2, vs1, vs0
@@ -103,10 +103,10 @@
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    xxsldwi vs0, v2, v2, 3
 ; P8BE-NEXT:    mfvsrwz r4, v3
-; P8BE-NEXT:    mtvsrwz f1, r4
+; P8BE-NEXT:    mtfprwz f1, r4
 ; P8BE-NEXT:    mfvsrwz r3, f0
 ; P8BE-NEXT:    xscvuxddp f1, f1
-; P8BE-NEXT:    mtvsrwz f0, r3
+; P8BE-NEXT:    mtfprwz f0, r3
 ; P8BE-NEXT:    xscvuxddp f0, f0
 ; P8BE-NEXT:    xxmrghd v2, vs0, vs1
 ; P8BE-NEXT:    blr
@@ -117,8 +117,8 @@
 ; P8LE-NEXT:    xxsldwi vs1, v3, v3, 1
 ; P8LE-NEXT:    mfvsrwz r3, f0
 ; P8LE-NEXT:    mfvsrwz r4, f1
-; P8LE-NEXT:    mtvsrwz f0, r3
-; P8LE-NEXT:    mtvsrwz f1, r4
+; P8LE-NEXT:    mtfprwz f0, r3
+; P8LE-NEXT:    mtfprwz f1, r4
 ; P8LE-NEXT:    xscvuxddp f0, f0
 ; P8LE-NEXT:    xscvuxddp f1, f1
 ; P8LE-NEXT:    xxmrghd v2, vs1, vs0
Index: llvm/trunk/test/CodeGen/PowerPC/uint-to-ppcfp128-crash.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/uint-to-ppcfp128-crash.ll
+++ llvm/trunk/test/CodeGen/PowerPC/uint-to-ppcfp128-crash.ll
@@ -9,7 +9,7 @@
   %conv = uitofp i16 %0 to ppc_fp128
   ret ppc_fp128 %conv
 ; CHECK: lhz [[LD:[0-9]+]], 0(3)
-; CHECK: mtvsrwa [[MV:[0-9]+]], [[LD]]
+; CHECK: mtfprwa [[MV:[0-9]+]], [[LD]]
 ; CHECK: xscvsxddp [[CONV:[0-9]+]], [[MV]]
 ; CHECK: bl __gcc_qadd
 }
Index: llvm/trunk/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
+++ llvm/trunk/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
@@ -29,11 +29,11 @@
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    xscvdpuxws f0, v2
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
+; CHECK-P9-NEXT:    mffprwz r3, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, v2
 ; CHECK-P9-NEXT:    mtvsrws v3, r3
 ; CHECK-P9-NEXT:    xscvdpuxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
+; CHECK-P9-NEXT:    mffprwz r3, f0
 ; CHECK-P9-NEXT:    mtvsrws v2, r3
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
@@ -42,11 +42,11 @@
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xscvdpuxws f0, v2
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, v2
 ; CHECK-BE-NEXT:    mtvsrws v3, r3
 ; CHECK-BE-NEXT:    xscvdpuxws f0, f0
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    mtvsrws v2, r3
 ; CHECK-BE-NEXT:    vmrghw v2, v3, v2
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
@@ -323,11 +323,11 @@
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    xscvdpsxws f0, v2
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
+; CHECK-P9-NEXT:    mffprwz r3, f0
 ; CHECK-P9-NEXT:    xxswapd vs0, v2
 ; CHECK-P9-NEXT:    mtvsrws v3, r3
 ; CHECK-P9-NEXT:    xscvdpsxws f0, f0
-; CHECK-P9-NEXT:    mfvsrwz r3, f0
+; CHECK-P9-NEXT:    mffprwz r3, f0
 ; CHECK-P9-NEXT:    mtvsrws v2, r3
 ; CHECK-P9-NEXT:    vmrglw v2, v3, v2
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
@@ -336,11 +336,11 @@
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xscvdpsxws f0, v2
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, v2
 ; CHECK-BE-NEXT:    mtvsrws v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mfvsrwz r3, f0
+; CHECK-BE-NEXT:    mffprwz r3, f0
 ; CHECK-BE-NEXT:    mtvsrws v2, r3
 ; CHECK-BE-NEXT:    vmrghw v2, v3, v2
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
Index: llvm/trunk/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
+++ llvm/trunk/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
@@ -18,8 +18,8 @@
 ; CHECK-P8-NEXT:    rldicl r3, r3, 48, 48
 ; CHECK-P8-NEXT:    rlwinm r4, r4, 0, 16, 31
 ; CHECK-P8-NEXT:    rlwinm r3, r3, 0, 16, 31
-; CHECK-P8-NEXT:    mtvsrwz f0, r4
-; CHECK-P8-NEXT:    mtvsrwz f1, r3
+; CHECK-P8-NEXT:    mtfprwz f0, r4
+; CHECK-P8-NEXT:    mtfprwz f1, r3
 ; CHECK-P8-NEXT:    xscvuxdsp f0, f0
 ; CHECK-P8-NEXT:    xscvuxdsp f1, f1
 ; CHECK-P8-NEXT:    xscvdpspn vs0, f0
@@ -37,14 +37,14 @@
 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    vextuhrx r3, r3, v2
 ; CHECK-P9-NEXT:    rlwinm r3, r3, 0, 16, 31
-; CHECK-P9-NEXT:    mtvsrwz f0, r3
+; CHECK-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-P9-NEXT:    li r3, 2
 ; CHECK-P9-NEXT:    xscvuxdsp f0, f0
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    vextuhrx r3, r3, v2
 ; CHECK-P9-NEXT:    rlwinm r3, r3, 0, 16, 31
 ; CHECK-P9-NEXT:    xxsldwi v3, vs0, vs0, 1
-; CHECK-P9-NEXT:    mtvsrwz f0, r3
+; CHECK-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-P9-NEXT:    xscvuxdsp f0, f0
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    xxsldwi v2, vs0, vs0, 1
@@ -58,13 +58,13 @@
 ; CHECK-BE-NEXT:    li r3, 2
 ; CHECK-BE-NEXT:    vextuhlx r3, r3, v2
 ; CHECK-BE-NEXT:    rlwinm r3, r3, 0, 16, 31
-; CHECK-BE-NEXT:    mtvsrwz f0, r3
+; CHECK-BE-NEXT:    mtfprwz f0, r3
 ; CHECK-BE-NEXT:    li r3, 0
 ; CHECK-BE-NEXT:    xscvuxdsp f0, f0
 ; CHECK-BE-NEXT:    vextuhlx r3, r3, v2
 ; CHECK-BE-NEXT:    rlwinm r3, r3, 0, 16, 31
 ; CHECK-BE-NEXT:    xscvdpspn v3, f0
-; CHECK-BE-NEXT:    mtvsrwz f0, r3
+; CHECK-BE-NEXT:    mtfprwz f0, r3
 ; CHECK-BE-NEXT:    xscvuxdsp f0, f0
 ; CHECK-BE-NEXT:    xscvdpspn v2, f0
 ; CHECK-BE-NEXT:    vmrghw v2, v2, v3
@@ -270,8 +270,8 @@
 ; CHECK-P8-NEXT:    rldicl r3, r3, 48, 48
 ; CHECK-P8-NEXT:    extsh r4, r4
 ; CHECK-P8-NEXT:    extsh r3, r3
-; CHECK-P8-NEXT:    mtvsrwa f0, r4
-; CHECK-P8-NEXT:    mtvsrwa f1, r3
+; CHECK-P8-NEXT:    mtfprwa f0, r4
+; CHECK-P8-NEXT:    mtfprwa f1, r3
 ; CHECK-P8-NEXT:    xscvsxdsp f0, f0
 ; CHECK-P8-NEXT:    xscvsxdsp f1, f1
 ; CHECK-P8-NEXT:    xscvdpspn vs0, f0
@@ -289,14 +289,14 @@
 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    vextuhrx r3, r3, v2
 ; CHECK-P9-NEXT:    extsh r3, r3
-; CHECK-P9-NEXT:    mtvsrwa f0, r3
+; CHECK-P9-NEXT:    mtfprwa f0, r3
 ; CHECK-P9-NEXT:    li r3, 2
 ; CHECK-P9-NEXT:    xscvsxdsp f0, f0
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    vextuhrx r3, r3, v2
 ; CHECK-P9-NEXT:    extsh r3, r3
 ; CHECK-P9-NEXT:    xxsldwi v3, vs0, vs0, 1
-; CHECK-P9-NEXT:    mtvsrwa f0, r3
+; CHECK-P9-NEXT:    mtfprwa f0, r3
 ; CHECK-P9-NEXT:    xscvsxdsp f0, f0
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    xxsldwi v2, vs0, vs0, 1
@@ -310,13 +310,13 @@
 ; CHECK-BE-NEXT:    li r3, 2
 ; CHECK-BE-NEXT:    vextuhlx r3, r3, v2
 ; CHECK-BE-NEXT:    extsh r3, r3
-; CHECK-BE-NEXT:    mtvsrwa f0, r3
+; CHECK-BE-NEXT:    mtfprwa f0, r3
 ; CHECK-BE-NEXT:    li r3, 0
 ; CHECK-BE-NEXT:    xscvsxdsp f0, f0
 ; CHECK-BE-NEXT:    vextuhlx r3, r3, v2
 ; CHECK-BE-NEXT:    extsh r3, r3
 ; CHECK-BE-NEXT:    xscvdpspn v3, f0
-; CHECK-BE-NEXT:    mtvsrwa f0, r3
+; CHECK-BE-NEXT:    mtfprwa f0, r3
 ; CHECK-BE-NEXT:    xscvsxdsp f0, f0
 ; CHECK-BE-NEXT:    xscvdpspn v2, f0
 ; CHECK-BE-NEXT:    vmrghw v2, v2, v3
Index: llvm/trunk/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
+++ llvm/trunk/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
@@ -18,8 +18,8 @@
 ; CHECK-P8-NEXT:    rldicl r3, r3, 56, 56
 ; CHECK-P8-NEXT:    rlwinm r4, r4, 0, 24, 31
 ; CHECK-P8-NEXT:    rlwinm r3, r3, 0, 24, 31
-; CHECK-P8-NEXT:    mtvsrwz f0, r4
-; CHECK-P8-NEXT:    mtvsrwz f1, r3
+; CHECK-P8-NEXT:    mtfprwz f0, r4
+; CHECK-P8-NEXT:    mtfprwz f1, r3
 ; CHECK-P8-NEXT:    xscvuxdsp f0, f0
 ; CHECK-P8-NEXT:    xscvuxdsp f1, f1
 ; CHECK-P8-NEXT:    xscvdpspn vs0, f0
@@ -37,14 +37,14 @@
 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    vextubrx r3, r3, v2
 ; CHECK-P9-NEXT:    rlwinm r3, r3, 0, 24, 31
-; CHECK-P9-NEXT:    mtvsrwz f0, r3
+; CHECK-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-P9-NEXT:    li r3, 1
 ; CHECK-P9-NEXT:    xscvuxdsp f0, f0
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    vextubrx r3, r3, v2
 ; CHECK-P9-NEXT:    rlwinm r3, r3, 0, 24, 31
 ; CHECK-P9-NEXT:    xxsldwi v3, vs0, vs0, 1
-; CHECK-P9-NEXT:    mtvsrwz f0, r3
+; CHECK-P9-NEXT:    mtfprwz f0, r3
 ; CHECK-P9-NEXT:    xscvuxdsp f0, f0
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    xxsldwi v2, vs0, vs0, 1
@@ -58,13 +58,13 @@
 ; CHECK-BE-NEXT:    li r3, 1
 ; CHECK-BE-NEXT:    vextublx r3, r3, v2
 ; CHECK-BE-NEXT:    rlwinm r3, r3, 0, 24, 31
-; CHECK-BE-NEXT:    mtvsrwz f0, r3
+; CHECK-BE-NEXT:    mtfprwz f0, r3
 ; CHECK-BE-NEXT:    li r3, 0
 ; CHECK-BE-NEXT:    xscvuxdsp f0, f0
 ; CHECK-BE-NEXT:    vextublx r3, r3, v2
 ; CHECK-BE-NEXT:    rlwinm r3, r3, 0, 24, 31
 ; CHECK-BE-NEXT:    xscvdpspn v3, f0
-; CHECK-BE-NEXT:    mtvsrwz f0, r3
+; CHECK-BE-NEXT:    mtfprwz f0, r3
 ; CHECK-BE-NEXT:    xscvuxdsp f0, f0
 ; CHECK-BE-NEXT:    xscvdpspn v2, f0
 ; CHECK-BE-NEXT:    vmrghw v2, v2, v3
@@ -286,8 +286,8 @@
 ; CHECK-P8-NEXT:    rldicl r3, r3, 56, 56
 ; CHECK-P8-NEXT:    extsb r4, r4
 ; CHECK-P8-NEXT:    extsb r3, r3
-; CHECK-P8-NEXT:    mtvsrwa f0, r4
-; CHECK-P8-NEXT:    mtvsrwa f1, r3
+; CHECK-P8-NEXT:    mtfprwa f0, r4
+; CHECK-P8-NEXT:    mtfprwa f1, r3
 ; CHECK-P8-NEXT:    xscvsxdsp f0, f0
 ; CHECK-P8-NEXT:    xscvsxdsp f1, f1
 ; CHECK-P8-NEXT:    xscvdpspn vs0, f0
@@ -305,14 +305,14 @@
 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    vextubrx r3, r3, v2
 ; CHECK-P9-NEXT:    extsb r3, r3
-; CHECK-P9-NEXT:    mtvsrwa f0, r3
+; CHECK-P9-NEXT:    mtfprwa f0, r3
 ; CHECK-P9-NEXT:    li r3, 1
 ; CHECK-P9-NEXT:    xscvsxdsp f0, f0
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    vextubrx r3, r3, v2
 ; CHECK-P9-NEXT:    extsb r3, r3
 ; CHECK-P9-NEXT:    xxsldwi v3, vs0, vs0, 1
-; CHECK-P9-NEXT:    mtvsrwa f0, r3
+; CHECK-P9-NEXT:    mtfprwa f0, r3
 ; CHECK-P9-NEXT:    xscvsxdsp f0, f0
 ; CHECK-P9-NEXT:    xscvdpspn vs0, f0
 ; CHECK-P9-NEXT:    xxsldwi v2, vs0, vs0, 1
@@ -326,13 +326,13 @@
 ; CHECK-BE-NEXT:    li r3, 1
 ; CHECK-BE-NEXT:    vextublx r3, r3, v2
 ; CHECK-BE-NEXT:    extsb r3, r3
-; CHECK-BE-NEXT:    mtvsrwa f0, r3
+; CHECK-BE-NEXT:    mtfprwa f0, r3
 ; CHECK-BE-NEXT:    li r3, 0
 ; CHECK-BE-NEXT:    xscvsxdsp f0, f0
 ; CHECK-BE-NEXT:    vextublx r3, r3, v2
 ; CHECK-BE-NEXT:    extsb r3, r3
 ; CHECK-BE-NEXT:    xscvdpspn v3, f0
-; CHECK-BE-NEXT:    mtvsrwa f0, r3
+; CHECK-BE-NEXT:    mtfprwa f0, r3
 ; CHECK-BE-NEXT:    xscvsxdsp f0, f0
 ; CHECK-BE-NEXT:    xscvdpspn v2, f0
 ; CHECK-BE-NEXT:    vmrghw v2, v2, v3
Index: llvm/trunk/test/MC/Disassembler/PowerPC/vsx.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/PowerPC/vsx.txt
+++ llvm/trunk/test/MC/Disassembler/PowerPC/vsx.txt
@@ -528,16 +528,31 @@
 # CHECK: mfvsrd 3, 40
 0x7d 0x03 0x00 0x67
 
-# CHECK: mfvsrwz 5, 0
+# CHECK: mffprd 3, 0
+0x7c 0x03 0x00 0x66
+
+# CHECK: mfvsrwz 5, 40
+0x7d 0x05 0x00 0xe7
+
+# CHECK: mffprwz 5, 0
 0x7c 0x05 0x00 0xe6
 
-# CHECK: mtvsrd 0, 3
+# CHECK: mtvsrd 40, 3
+0x7d 0x03 0x01 0x67
+
+# CHECK: mtfprd 0, 3
 0x7c 0x03 0x01 0x66
 
-# CHECK: mtvsrwa 0, 3
+# CHECK: mtvsrwa 40, 3
+0x7d 0x03 0x01 0xa7
+
+# CHECK: mtfprwa 0, 3
 0x7c 0x03 0x01 0xa6
 
-# CHECK: mtvsrwz 0, 3
+# CHECK: mtvsrwz 40, 3
+0x7d 0x03 0x01 0xe7
+
+# CHECK: mtfprwz 0, 3
 0x7c 0x03 0x01 0xe6
 
 # Power9 Instructions:
Index: llvm/trunk/test/MC/PowerPC/vsx.s
===================================================================
--- llvm/trunk/test/MC/PowerPC/vsx.s
+++ llvm/trunk/test/MC/PowerPC/vsx.s
@@ -538,18 +538,64 @@
 # CHECK-BE: mfvsrd 3, 40                       # encoding: [0x7d,0x03,0x00,0x67]
 # CHECK-LE: mfvsrd 3, 40                       # encoding: [0x67,0x00,0x03,0x7d]
             mfvrd 3, 8
-# CHECK-BE: mfvsrwz 5, 0                       # encoding: [0x7c,0x05,0x00,0xe6]
-# CHECK-LE: mfvsrwz 5, 0                       # encoding: [0xe6,0x00,0x05,0x7c]
+# CHECK-BE: mffprd 0, 3                        # encoding: [0x7c,0x60,0x00,0x66]
+# CHECK-LE: mffprd 0, 3                        # encoding: [0x66,0x00,0x60,0x7c]
+            mfvsrd 0, 3 
+# CHECK-BE: mffprd 0, 3                        # encoding: [0x7c,0x60,0x00,0x66]
+# CHECK-LE: mffprd 0, 3                        # encoding: [0x66,0x00,0x60,0x7c]
+            mffprd 0, 3 
+
+# CHECK-BE: mfvsrwz 5, 40                      # encoding: [0x7d,0x05,0x00,0xe7]
+# CHECK-LE: mfvsrwz 5, 40                      # encoding: [0xe7,0x00,0x05,0x7d]
+            mfvsrwz 5, 40
+# CHECK-BE: mfvsrwz 5, 40                      # encoding: [0x7d,0x05,0x00,0xe7]
+# CHECK-LE: mfvsrwz 5, 40                      # encoding: [0xe7,0x00,0x05,0x7d]
+            mfvrwz 5, 8 
+# CHECK-BE: mffprwz 5, 0                       # encoding: [0x7c,0x05,0x00,0xe6]
+# CHECK-LE: mffprwz 5, 0                       # encoding: [0xe6,0x00,0x05,0x7c]
             mfvsrwz 5, 0
-# CHECK-BE: mtvsrd 0, 3                        # encoding: [0x7c,0x03,0x01,0x66]
-# CHECK-LE: mtvsrd 0, 3                        # encoding: [0x66,0x01,0x03,0x7c]
+# CHECK-BE: mffprwz 5, 0                       # encoding: [0x7c,0x05,0x00,0xe6]
+# CHECK-LE: mffprwz 5, 0                       # encoding: [0xe6,0x00,0x05,0x7c]
+            mffprwz 5, 0
+
+# CHECK-BE: mtvsrd 40, 3                       # encoding: [0x7d,0x03,0x01,0x67]
+# CHECK-LE: mtvsrd 40, 3                       # encoding: [0x67,0x01,0x03,0x7d]
+            mtvsrd 40, 3 
+# CHECK-BE: mtvsrd 40, 3                       # encoding: [0x7d,0x03,0x01,0x67]
+# CHECK-LE: mtvsrd 40, 3                       # encoding: [0x67,0x01,0x03,0x7d]
+            mtvrd 8, 3 
+# CHECK-BE: mtfprd 0, 3                        # encoding: [0x7c,0x03,0x01,0x66]
+# CHECK-LE: mtfprd 0, 3                        # encoding: [0x66,0x01,0x03,0x7c]
             mtvsrd 0, 3
-# CHECK-BE: mtvsrwa 0, 3                       # encoding: [0x7c,0x03,0x01,0xa6]
-# CHECK-LE: mtvsrwa 0, 3                       # encoding: [0xa6,0x01,0x03,0x7c]
+# CHECK-BE: mtfprd 0, 3                        # encoding: [0x7c,0x03,0x01,0x66]
+# CHECK-LE: mtfprd 0, 3                        # encoding: [0x66,0x01,0x03,0x7c]
+            mtfprd 0, 3
+
+# CHECK-BE: mtvsrwa 40, 3                      # encoding: [0x7d,0x03,0x01,0xa7]
+# CHECK-LE: mtvsrwa 40, 3                      # encoding: [0xa7,0x01,0x03,0x7d]
+            mtvsrwa 40, 3
+# CHECK-BE: mtvsrwa 40, 3                      # encoding: [0x7d,0x03,0x01,0xa7]
+# CHECK-LE: mtvsrwa 40, 3                      # encoding: [0xa7,0x01,0x03,0x7d]
+            mtvrwa 8, 3
+# CHECK-BE: mtfprwa 0, 3                       # encoding: [0x7c,0x03,0x01,0xa6]
+# CHECK-LE: mtfprwa 0, 3                       # encoding: [0xa6,0x01,0x03,0x7c]
             mtvsrwa 0, 3
-# CHECK-BE: mtvsrwz 0, 3                       # encoding: [0x7c,0x03,0x01,0xe6]
-# CHECK-LE: mtvsrwz 0, 3                       # encoding: [0xe6,0x01,0x03,0x7c]
+# CHECK-BE: mtfprwa 0, 3                       # encoding: [0x7c,0x03,0x01,0xa6]
+# CHECK-LE: mtfprwa 0, 3                       # encoding: [0xa6,0x01,0x03,0x7c]
+            mtfprwa 0, 3
+
+# CHECK-BE: mtvsrwz 40, 3                      # encoding: [0x7d,0x03,0x01,0xe7]
+# CHECK-LE: mtvsrwz 40, 3                      # encoding: [0xe7,0x01,0x03,0x7d]
+            mtvsrwz 40, 3
+# CHECK-BE: mtvsrwz 40, 3                      # encoding: [0x7d,0x03,0x01,0xe7]
+# CHECK-LE: mtvsrwz 40, 3                      # encoding: [0xe7,0x01,0x03,0x7d]
+            mtvrwz 8, 3
+# CHECK-BE: mtfprwz 0, 3                       # encoding: [0x7c,0x03,0x01,0xe6]
+# CHECK-LE: mtfprwz 0, 3                       # encoding: [0xe6,0x01,0x03,0x7c]
             mtvsrwz 0, 3
+# CHECK-BE: mtfprwz 0, 3                       # encoding: [0x7c,0x03,0x01,0xe6]
+# CHECK-LE: mtfprwz 0, 3                       # encoding: [0xe6,0x01,0x03,0x7c]
+            mtfprwz 0, 3
 
 # Power9 Instructions: