diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -70,6 +70,10 @@ The following options are deprecated and ignored. They will be removed in future versions of Clang. +- -mmpx used to enable the __MPX__ preprocessor define for the Intel MPX + instructions. There were no MPX intrinsics. +- -mno-mpx used to disable -mmpx and is the default behavior. + - ... Modified Compiler Flags diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -211,6 +211,10 @@ def : Flag<["-"], "fslp-vectorize-aggressive">, Group; def : Flag<["-"], "fno-slp-vectorize-aggressive">, Group; +// Retired with clang-10.0. Previously controlled X86 MPX ISA. +def mmpx : Flag<["-"], "mmpx">, Group; +def mno_mpx : Flag<["-"], "mno-mpx">, Group; + // Group that ignores all gcc optimizations that won't be implemented def clang_ignored_gcc_optimization_f_Group : OptionGroup< "">, Group, Flags<[Ignored]>; @@ -2998,8 +3002,6 @@ def mno_movdiri : Flag<["-"], "mno-movdiri">, Group; def mmovdir64b : Flag<["-"], "mmovdir64b">, Group; def mno_movdir64b : Flag<["-"], "mno-movdir64b">, Group; -def mmpx : Flag<["-"], "mmpx">, Group; -def mno_mpx : Flag<["-"], "mno-mpx">, Group; def mmwaitx : Flag<["-"], "mmwaitx">, Group; def mno_mwaitx : Flag<["-"], "mno-mwaitx">, Group; def mpku : Flag<["-"], "mpku">, Group; diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h --- a/clang/lib/Basic/Targets/X86.h +++ b/clang/lib/Basic/Targets/X86.h @@ -80,7 +80,6 @@ bool HasAVX512IFMA = false; bool HasAVX512VP2INTERSECT = false; bool HasSHA = false; - bool HasMPX = false; bool HasSHSTK = false; bool HasSGX = false; bool HasCX8 = false; diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp --- a/clang/lib/Basic/Targets/X86.cpp +++ b/clang/lib/Basic/Targets/X86.cpp @@ -198,7 +198,6 @@ SkylakeCommon: setFeatureEnabledImpl(Features, "xsavec", true); setFeatureEnabledImpl(Features, "xsaves", true); - setFeatureEnabledImpl(Features, "mpx", true); setFeatureEnabledImpl(Features, "clflushopt", true); setFeatureEnabledImpl(Features, "aes", true); LLVM_FALLTHROUGH; @@ -277,7 +276,6 @@ setFeatureEnabledImpl(Features, "xsavec", true); setFeatureEnabledImpl(Features, "xsaves", true); setFeatureEnabledImpl(Features, "clflushopt", true); - setFeatureEnabledImpl(Features, "mpx", true); setFeatureEnabledImpl(Features, "fsgsbase", true); setFeatureEnabledImpl(Features, "aes", true); LLVM_FALLTHROUGH; @@ -798,8 +796,6 @@ HasAVX512VP2INTERSECT = true; } else if (Feature == "+sha") { HasSHA = true; - } else if (Feature == "+mpx") { - HasMPX = true; } else if (Feature == "+shstk") { HasSHSTK = true; } else if (Feature == "+movbe") { @@ -1220,8 +1216,6 @@ Builder.defineMacro("__CLWB__"); if (HasWBNOINVD) Builder.defineMacro("__WBNOINVD__"); - if (HasMPX) - Builder.defineMacro("__MPX__"); if (HasSHSTK) Builder.defineMacro("__SHSTK__"); if (HasSGX) @@ -1378,7 +1372,6 @@ .Case("movbe", true) .Case("movdiri", true) .Case("movdir64b", true) - .Case("mpx", true) .Case("mwaitx", true) .Case("pclmul", true) .Case("pconfig", true) @@ -1462,7 +1455,6 @@ .Case("movbe", HasMOVBE) .Case("movdiri", HasMOVDIRI) .Case("movdir64b", HasMOVDIR64B) - .Case("mpx", HasMPX) .Case("mwaitx", HasMWAITX) .Case("pclmul", HasPCLMUL) .Case("pconfig", HasPCONFIG) diff --git a/clang/test/Driver/x86-target-features.c b/clang/test/Driver/x86-target-features.c --- a/clang/test/Driver/x86-target-features.c +++ b/clang/test/Driver/x86-target-features.c @@ -72,8 +72,8 @@ // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mmpx %s -### -o %t.o 2>&1 | FileCheck -check-prefix=MPX %s // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-mpx %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-MPX %s -// MPX: "-target-feature" "+mpx" -// NO-MPX: "-target-feature" "-mpx" +// MPX: the flag '-mmpx' has been deprecated and will be ignored +// NO-MPX: the flag '-mno-mpx' has been deprecated and will be ignored // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mshstk %s -### -o %t.o 2>&1 | FileCheck -check-prefix=CETSS %s // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-shstk %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-CETSS %s diff --git a/clang/test/Preprocessor/predefined-arch-macros.c b/clang/test/Preprocessor/predefined-arch-macros.c --- a/clang/test/Preprocessor/predefined-arch-macros.c +++ b/clang/test/Preprocessor/predefined-arch-macros.c @@ -682,7 +682,6 @@ // CHECK_SKL_M32: #define __LZCNT__ 1 // CHECK_SKL_M32: #define __MMX__ 1 // CHECK_SKL_M32: #define __MOVBE__ 1 -// CHECK_SKL_M32: #define __MPX__ 1 // CHECK_SKL_M32: #define __PCLMUL__ 1 // CHECK_SKL_M32: #define __POPCNT__ 1 // CHECK_SKL_M32: #define __PRFCHW__ 1 @@ -717,7 +716,6 @@ // CHECK_SKL_M64: #define __LZCNT__ 1 // CHECK_SKL_M64: #define __MMX__ 1 // CHECK_SKL_M64: #define __MOVBE__ 1 -// CHECK_SKL_M64: #define __MPX__ 1 // CHECK_SKL_M64: #define __PCLMUL__ 1 // CHECK_SKL_M64: #define __POPCNT__ 1 // CHECK_SKL_M64: #define __PRFCHW__ 1 @@ -912,7 +910,6 @@ // CHECK_SKX_M32: #define __LZCNT__ 1 // CHECK_SKX_M32: #define __MMX__ 1 // CHECK_SKX_M32: #define __MOVBE__ 1 -// CHECK_SKX_M32: #define __MPX__ 1 // CHECK_SKX_M32: #define __PCLMUL__ 1 // CHECK_SKX_M32: #define __PKU__ 1 // CHECK_SKX_M32: #define __POPCNT__ 1 @@ -958,7 +955,6 @@ // CHECK_SKX_M64: #define __LZCNT__ 1 // CHECK_SKX_M64: #define __MMX__ 1 // CHECK_SKX_M64: #define __MOVBE__ 1 -// CHECK_SKX_M64: #define __MPX__ 1 // CHECK_SKX_M64: #define __PCLMUL__ 1 // CHECK_SKX_M64: #define __PKU__ 1 // CHECK_SKX_M64: #define __POPCNT__ 1 @@ -1008,7 +1004,6 @@ // CHECK_CLX_M32: #define __LZCNT__ 1 // CHECK_CLX_M32: #define __MMX__ 1 // CHECK_CLX_M32: #define __MOVBE__ 1 -// CHECK_CLX_M32: #define __MPX__ 1 // CHECK_CLX_M32: #define __PCLMUL__ 1 // CHECK_CLX_M32: #define __PKU__ 1 // CHECK_CLX_M32: #define __POPCNT__ 1 @@ -1055,7 +1050,6 @@ // CHECK_CLX_M64: #define __LZCNT__ 1 // CHECK_CLX_M64: #define __MMX__ 1 // CHECK_CLX_M64: #define __MOVBE__ 1 -// CHECK_CLX_M64: #define __MPX__ 1 // CHECK_CLX_M64: #define __PCLMUL__ 1 // CHECK_CLX_M64: #define __PKU__ 1 // CHECK_CLX_M64: #define __POPCNT__ 1 @@ -1106,7 +1100,6 @@ // CHECK_CPX_M32: #define __LZCNT__ 1 // CHECK_CPX_M32: #define __MMX__ 1 // CHECK_CPX_M32: #define __MOVBE__ 1 -// CHECK_CPX_M32: #define __MPX__ 1 // CHECK_CPX_M32: #define __PCLMUL__ 1 // CHECK_CPX_M32: #define __PKU__ 1 // CHECK_CPX_M32: #define __POPCNT__ 1 @@ -1154,7 +1147,6 @@ // CHECK_CPX_M64: #define __LZCNT__ 1 // CHECK_CPX_M64: #define __MMX__ 1 // CHECK_CPX_M64: #define __MOVBE__ 1 -// CHECK_CPX_M64: #define __MPX__ 1 // CHECK_CPX_M64: #define __PCLMUL__ 1 // CHECK_CPX_M64: #define __PKU__ 1 // CHECK_CPX_M64: #define __POPCNT__ 1 @@ -1205,7 +1197,6 @@ // CHECK_CNL_M32: #define __LZCNT__ 1 // CHECK_CNL_M32: #define __MMX__ 1 // CHECK_CNL_M32: #define __MOVBE__ 1 -// CHECK_CNL_M32: #define __MPX__ 1 // CHECK_CNL_M32: #define __PCLMUL__ 1 // CHECK_CNL_M32: #define __PKU__ 1 // CHECK_CNL_M32: #define __POPCNT__ 1 @@ -1254,7 +1245,6 @@ // CHECK_CNL_M64: #define __LZCNT__ 1 // CHECK_CNL_M64: #define __MMX__ 1 // CHECK_CNL_M64: #define __MOVBE__ 1 -// CHECK_CNL_M64: #define __MPX__ 1 // CHECK_CNL_M64: #define __PCLMUL__ 1 // CHECK_CNL_M64: #define __PKU__ 1 // CHECK_CNL_M64: #define __POPCNT__ 1 @@ -1309,7 +1299,6 @@ // CHECK_ICL_M32: #define __LZCNT__ 1 // CHECK_ICL_M32: #define __MMX__ 1 // CHECK_ICL_M32: #define __MOVBE__ 1 -// CHECK_ICL_M32: #define __MPX__ 1 // CHECK_ICL_M32: #define __PCLMUL__ 1 // CHECK_ICL_M32: #define __PKU__ 1 // CHECK_ICL_M32: #define __POPCNT__ 1 @@ -1367,7 +1356,6 @@ // CHECK_ICL_M64: #define __LZCNT__ 1 // CHECK_ICL_M64: #define __MMX__ 1 // CHECK_ICL_M64: #define __MOVBE__ 1 -// CHECK_ICL_M64: #define __MPX__ 1 // CHECK_ICL_M64: #define __PCLMUL__ 1 // CHECK_ICL_M64: #define __PKU__ 1 // CHECK_ICL_M64: #define __POPCNT__ 1 @@ -1426,7 +1414,6 @@ // CHECK_ICX_M32: #define __LZCNT__ 1 // CHECK_ICX_M32: #define __MMX__ 1 // CHECK_ICX_M32: #define __MOVBE__ 1 -// CHECK_ICX_M32: #define __MPX__ 1 // CHECK_ICX_M32: #define __PCLMUL__ 1 // CHECK_ICX_M32: #define __PCONFIG__ 1 // CHECK_ICX_M32: #define __PKU__ 1 @@ -1485,7 +1472,6 @@ // CHECK_ICX_M64: #define __LZCNT__ 1 // CHECK_ICX_M64: #define __MMX__ 1 // CHECK_ICX_M64: #define __MOVBE__ 1 -// CHECK_ICX_M64: #define __MPX__ 1 // CHECK_ICX_M64: #define __PCLMUL__ 1 // CHECK_ICX_M64: #define __PCONFIG__ 1 // CHECK_ICX_M64: #define __PKU__ 1 @@ -1548,7 +1534,6 @@ // CHECK_TGL_M32: #define __MOVBE__ 1 // CHECK_TGL_M32: #define __MOVDIR64B__ 1 // CHECK_TGL_M32: #define __MOVDIRI__ 1 -// CHECK_TGL_M32: #define __MPX__ 1 // CHECK_TGL_M32: #define __PCLMUL__ 1 // CHECK_TGL_M32-NOT: #define __PCONFIG__ 1 // CHECK_TGL_M32: #define __PKU__ 1 @@ -1611,7 +1596,6 @@ // CHECK_TGL_M64: #define __MOVBE__ 1 // CHECK_TGL_M64: #define __MOVDIR64B__ 1 // CHECK_TGL_M64: #define __MOVDIRI__ 1 -// CHECK_TGL_M64: #define __MPX__ 1 // CHECK_TGL_M64: #define __PCLMUL__ 1 // CHECK_TGL_M64-NOT: #define __PCONFIG__ 1 // CHECK_TGL_M64: #define __PKU__ 1 @@ -1688,7 +1672,6 @@ // CHECK_GLM_M32: #define __FXSR__ 1 // CHECK_GLM_M32: #define __MMX__ 1 // CHECK_GLM_M32: #define __MOVBE__ 1 -// CHECK_GLM_M32: #define __MPX__ 1 // CHECK_GLM_M32: #define __PCLMUL__ 1 // CHECK_GLM_M32: #define __POPCNT__ 1 // CHECK_GLM_M32: #define __PRFCHW__ 1 @@ -1722,7 +1705,6 @@ // CHECK_GLM_M64: #define __FXSR__ 1 // CHECK_GLM_M64: #define __MMX__ 1 // CHECK_GLM_M64: #define __MOVBE__ 1 -// CHECK_GLM_M64: #define __MPX__ 1 // CHECK_GLM_M64: #define __PCLMUL__ 1 // CHECK_GLM_M64: #define __POPCNT__ 1 // CHECK_GLM_M64: #define __PRFCHW__ 1 @@ -1754,7 +1736,6 @@ // CHECK_GLMP_M32: #define __FXSR__ 1 // CHECK_GLMP_M32: #define __MMX__ 1 // CHECK_GLMP_M32: #define __MOVBE__ 1 -// CHECK_GLMP_M32: #define __MPX__ 1 // CHECK_GLMP_M32: #define __PCLMUL__ 1 // CHECK_GLMP_M32: #define __POPCNT__ 1 // CHECK_GLMP_M32: #define __PRFCHW__ 1 @@ -1791,7 +1772,6 @@ // CHECK_GLMP_M64: #define __FXSR__ 1 // CHECK_GLMP_M64: #define __MMX__ 1 // CHECK_GLMP_M64: #define __MOVBE__ 1 -// CHECK_GLMP_M64: #define __MPX__ 1 // CHECK_GLMP_M64: #define __PCLMUL__ 1 // CHECK_GLMP_M64: #define __POPCNT__ 1 // CHECK_GLMP_M64: #define __PRFCHW__ 1 @@ -1830,7 +1810,6 @@ // CHECK_TRM_M32: #define __MOVBE__ 1 // CHECK_TRM_M32: #define __MOVDIR64B__ 1 // CHECK_TRM_M32: #define __MOVDIRI__ 1 -// CHECK_TRM_M32: #define __MPX__ 1 // CHECK_TRM_M32: #define __PCLMUL__ 1 // CHECK_TRM_M32: #define __POPCNT__ 1 // CHECK_TRM_M32: #define __PRFCHW__ 1 @@ -1872,7 +1851,6 @@ // CHECK_TRM_M64: #define __MOVBE__ 1 // CHECK_TRM_M64: #define __MOVDIR64B__ 1 // CHECK_TRM_M64: #define __MOVDIRI__ 1 -// CHECK_TRM_M64: #define __MPX__ 1 // CHECK_TRM_M64: #define __PCLMUL__ 1 // CHECK_TRM_M64: #define __POPCNT__ 1 // CHECK_TRM_M64: #define __PRFCHW__ 1 diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -93,6 +93,10 @@ During this release ... +* Deprecated the mpx feature flag for the Intel MPX instructions. There were no + intrinsics for this feature. This change only this effects the results + returned by getHostCPUFeatures on CPUs that implement the MPX instructions. + Changes to the WebAssembly Target --------------------------------- diff --git a/llvm/lib/Support/Host.cpp b/llvm/lib/Support/Host.cpp --- a/llvm/lib/Support/Host.cpp +++ b/llvm/lib/Support/Host.cpp @@ -1378,7 +1378,6 @@ Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); Features["invpcid"] = HasLeaf7 && ((EBX >> 10) & 1); Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); - Features["mpx"] = HasLeaf7 && ((EBX >> 14) & 1); // AVX512 is only supported if the OS supports the context save for it. Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -241,8 +241,11 @@ "Enable Cache Demote">; def FeaturePTWRITE : SubtargetFeature<"ptwrite", "HasPTWRITE", "true", "Support ptwrite instruction">; -def FeatureMPX : SubtargetFeature<"mpx", "HasMPX", "true", - "Support MPX instructions">; +// FIXME: This feature is deprecated in 10.0 and should not be used for +// anything, but removing it would break IR files that may contain it in a +// target-feature attribute. +def FeatureDeprecatedMPX : SubtargetFeature<"mpx", "DeprecatedHasMPX", "false", + "Deprecated. Support MPX instructions">; def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true", "Use LEA for adjusting the stack pointer">; def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb", @@ -580,7 +583,6 @@ // Skylake list SKLAdditionalFeatures = [FeatureAES, - FeatureMPX, FeatureXSAVEC, FeatureXSAVES, FeatureCLFLUSHOPT, @@ -719,7 +721,6 @@ // Goldmont list GLMAdditionalFeatures = [FeatureAES, - FeatureMPX, FeatureSHA, FeatureRDSEED, FeatureXSAVE, diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -940,7 +940,6 @@ def HasPTWRITE : Predicate<"Subtarget->hasPTWRITE()">; def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; -def HasMPX : Predicate<"Subtarget->hasMPX()">; def HasSHSTK : Predicate<"Subtarget->hasSHSTK()">; def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">; def HasCLWB : Predicate<"Subtarget->hasCLWB()">; diff --git a/llvm/lib/Target/X86/X86InstrMPX.td b/llvm/lib/Target/X86/X86InstrMPX.td --- a/llvm/lib/Target/X86/X86InstrMPX.td +++ b/llvm/lib/Target/X86/X86InstrMPX.td @@ -18,10 +18,10 @@ multiclass mpx_bound_make opc, string OpcodeStr> { def 32rm: I, - Requires<[HasMPX, Not64BitMode]>; + Requires<[Not64BitMode]>; def 64rm: I, - Requires<[HasMPX, In64BitMode]>; + Requires<[In64BitMode]>; } defm BNDMK : mpx_bound_make<0x1B, "bndmk">, XS; @@ -29,17 +29,17 @@ multiclass mpx_bound_check opc, string OpcodeStr> { def 32rm: I, - Requires<[HasMPX, Not64BitMode]>; + Requires<[Not64BitMode]>; def 64rm: I, - Requires<[HasMPX, In64BitMode]>; + Requires<[In64BitMode]>; def 32rr: I, - Requires<[HasMPX, Not64BitMode]>; + Requires<[Not64BitMode]>; def 64rr: I, - Requires<[HasMPX, In64BitMode]>; + Requires<[In64BitMode]>; } defm BNDCL : mpx_bound_check<0x1A, "bndcl">, XS, NotMemoryFoldable; defm BNDCU : mpx_bound_check<0x1A, "bndcu">, XD, NotMemoryFoldable; @@ -47,33 +47,31 @@ def BNDMOVrr : I<0x1A, MRMSrcReg, (outs BNDR:$dst), (ins BNDR:$src), "bndmov\t{$src, $dst|$dst, $src}", []>, PD, - Requires<[HasMPX]>, NotMemoryFoldable; + NotMemoryFoldable; let mayLoad = 1 in { def BNDMOV32rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src), "bndmov\t{$src, $dst|$dst, $src}", []>, PD, - Requires<[HasMPX, Not64BitMode]>, NotMemoryFoldable; + Requires<[Not64BitMode]>, NotMemoryFoldable; def BNDMOV64rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i128mem:$src), "bndmov\t{$src, $dst|$dst, $src}", []>, PD, - Requires<[HasMPX, In64BitMode]>, NotMemoryFoldable; + Requires<[In64BitMode]>, NotMemoryFoldable; } let isCodeGenOnly = 1, ForceDisassemble = 1 in def BNDMOVrr_REV : I<0x1B, MRMDestReg, (outs BNDR:$dst), (ins BNDR:$src), "bndmov\t{$src, $dst|$dst, $src}", []>, PD, - Requires<[HasMPX]>, NotMemoryFoldable; + NotMemoryFoldable; let mayStore = 1 in { def BNDMOV32mr : I<0x1B, MRMDestMem, (outs), (ins i64mem:$dst, BNDR:$src), "bndmov\t{$src, $dst|$dst, $src}", []>, PD, - Requires<[HasMPX, Not64BitMode]>, NotMemoryFoldable; + Requires<[Not64BitMode]>, NotMemoryFoldable; def BNDMOV64mr : I<0x1B, MRMDestMem, (outs), (ins i128mem:$dst, BNDR:$src), "bndmov\t{$src, $dst|$dst, $src}", []>, PD, - Requires<[HasMPX, In64BitMode]>, NotMemoryFoldable; + Requires<[In64BitMode]>, NotMemoryFoldable; def BNDSTXmr: I<0x1B, MRMDestMem, (outs), (ins anymem:$dst, BNDR:$src), - "bndstx\t{$src, $dst|$dst, $src}", []>, PS, - Requires<[HasMPX]>; + "bndstx\t{$src, $dst|$dst, $src}", []>, PS; } let mayLoad = 1 in def BNDLDXrm: I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src), - "bndldx\t{$src, $dst|$dst, $src}", []>, PS, - Requires<[HasMPX]>; + "bndldx\t{$src, $dst|$dst, $src}", []>, PS; } // SchedRW diff --git a/llvm/lib/Target/X86/X86Subtarget.h b/llvm/lib/Target/X86/X86Subtarget.h --- a/llvm/lib/Target/X86/X86Subtarget.h +++ b/llvm/lib/Target/X86/X86Subtarget.h @@ -365,8 +365,8 @@ /// Processor has AVX-512 vp2intersect instructions bool HasVP2INTERSECT = false; - /// Processor supports MPX - Memory Protection Extensions - bool HasMPX = false; + /// Deprecated flag for MPX instructions. + bool DeprecatedHasMPX = false; /// Processor supports CET SHSTK - Control-Flow Enforcement Technology /// using Shadow Stack @@ -684,7 +684,6 @@ bool hasBF16() const { return HasBF16; } bool hasVP2INTERSECT() const { return HasVP2INTERSECT; } bool hasBITALG() const { return HasBITALG; } - bool hasMPX() const { return HasMPX; } bool hasSHSTK() const { return HasSHSTK; } bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; } bool hasCLWB() const { return HasCLWB; } diff --git a/llvm/test/CodeGen/X86/ms-inline-asm-avx512.ll b/llvm/test/CodeGen/X86/ms-inline-asm-avx512.ll --- a/llvm/test/CodeGen/X86/ms-inline-asm-avx512.ll +++ b/llvm/test/CodeGen/X86/ms-inline-asm-avx512.ll @@ -20,5 +20,5 @@ ; CHECK: movq %rax, 7(%rsp) ; CHECK: retq -attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+f16c,+fma,+fsgsbase,+fxsr,+lzcnt,+mmx,+movbe,+mpx,+pclmul,+pku,+popcnt,+rdrnd,+rdseed,+rtm,+sgx,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+f16c,+fma,+fsgsbase,+fxsr,+lzcnt,+mmx,+movbe,+pclmul,+pku,+popcnt,+rdrnd,+rdseed,+rtm,+sgx,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind } diff --git a/llvm/test/CodeGen/X86/vector-width-store-merge.ll b/llvm/test/CodeGen/X86/vector-width-store-merge.ll --- a/llvm/test/CodeGen/X86/vector-width-store-merge.ll +++ b/llvm/test/CodeGen/X86/vector-width-store-merge.ll @@ -46,8 +46,8 @@ ; Function Attrs: argmemonly nounwind declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i1 immarg) #1 -attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "prefer-vector-width"="128" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+mpx,+pclmul,+pku,+popcnt,+prfchw,+rdrnd,+rdseed,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "prefer-vector-width"="128" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+pclmul,+pku,+popcnt,+prfchw,+rdrnd,+rdseed,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { argmemonly nounwind } -attributes #2 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "prefer-vector-width"="256" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+mpx,+pclmul,+pku,+popcnt,+prfchw,+rdrnd,+rdseed,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "prefer-vector-width"="256" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+pclmul,+pku,+popcnt,+prfchw,+rdrnd,+rdseed,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "unsafe-fp-math"="false" "use-soft-float"="false" } !0 = !{i32 1, !"wchar_size", i32 4}