Index: lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.cpp
+++ lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -2623,6 +2623,21 @@
 
   unsigned NewOpc = IsFMA ? (IsF16 ? AMDGPU::V_FMA_F16 : AMDGPU::V_FMA_F32)
                           : (IsF16 ? AMDGPU::V_MAD_F16 : AMDGPU::V_MAD_F32);
+
+  // If the source of the tied reg is a sgpr->vgpr copy then replace
+  // it back with the sgpr, to potentially kill the copy, if
+  // this doesn't violate the constant bus restriction
+  if (!Src0Mods && !Src1Mods && !Clamp && !Omod &&
+      (ST.getConstantBusLimit(Opc) > 1 ||
+       !Src0->isReg() ||
+       !RI.isSGPRReg(MBB->getParent()->getRegInfo(), Src0->getReg()))) {
+    const MachineFunction *MF = Src2->getParent()->getMF();
+    const MachineRegisterInfo *MRI = &MF->getRegInfo();
+    auto *Def = MRI->getUniqueVRegDef(Src2->getReg());
+    if (Def->getOpcode() == AMDGPU::COPY)
+      Src2 = &(Def->getOperand(1));
+  }
+
   if (pseudoToMCOpcode(NewOpc) == -1)
     return nullptr;