Index: lib/Target/Mips/MipsISelLowering.cpp
===================================================================
--- lib/Target/Mips/MipsISelLowering.cpp
+++ lib/Target/Mips/MipsISelLowering.cpp
@@ -1178,7 +1178,8 @@
   //   beq     success,$0,loopMBB
 
   BB = loopMBB;
-  BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
+  unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
+  BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
   if (Nand) {
     //  and andres, oldval, incr2
     //  nor binopres, $0, andres
@@ -1201,7 +1202,8 @@
     .addReg(OldVal).addReg(Mask2);
   BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
     .addReg(MaskedOldVal0).addReg(NewVal);
-  BuildMI(BB, DL, TII->get(Mips::SC), Success)
+  unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC;
+  BuildMI(BB, DL, TII->get(SC), Success)
     .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
   BuildMI(BB, DL, TII->get(Mips::BEQ))
     .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
@@ -1412,7 +1414,8 @@
   //    and     maskedoldval0,oldval,mask
   //    bne     maskedoldval0,shiftedcmpval,sinkMBB
   BB = loop1MBB;
-  BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
+  unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
+  BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
   BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
     .addReg(OldVal).addReg(Mask);
   BuildMI(BB, DL, TII->get(Mips::BNE))
@@ -1428,7 +1431,8 @@
     .addReg(OldVal).addReg(Mask2);
   BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
     .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
-  BuildMI(BB, DL, TII->get(Mips::SC), Success)
+  unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC;
+  BuildMI(BB, DL, TII->get(SC), Success)
       .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
   BuildMI(BB, DL, TII->get(Mips::BEQ))
       .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
Index: test/CodeGen/Mips/atomic.ll
===================================================================
--- test/CodeGen/Mips/atomic.ll
+++ test/CodeGen/Mips/atomic.ll
@@ -6,6 +6,14 @@
 ; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL
 ; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL
 
+; Use llvm-objdump to check wheter the encodings of microMIPS atomic instructions are correct.
+; While emitting assembly files directly when in microMIPS mode, it is possible to emit a mips32r2
+; instruction instead of microMIPS instruction, and since many mips32r2 and microMIPS
+; instructions have identical assembly formats, invalid instruction cannot be detected.
+; RUN: llc -march=mipsel -filetype=obj --disable-machine-licm -mattr=micromips < %s -o - \
+; RUN:   | llvm-objdump -no-show-raw-insn -arch mipsel -mcpu=mips32r2 -mattr=micromips -d - \
+; RUN:   | FileCheck %s -check-prefix=MICROMIPS
+
 ; Keep one big-endian check so that we don't reduce testing, but don't add more
 ; since endianness doesn't affect the body of the atomic operations.
 ; RUN: llc -march=mips   --disable-machine-licm -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EB
@@ -27,6 +35,12 @@
 ; ALL:           addu    $[[R2:[0-9]+]], $[[R1]], $4
 ; ALL:           sc      $[[R2]], 0($[[R0]])
 ; ALL:           beqz    $[[R2]], $[[BB0]]
+
+; MICROMIPS:     lw      $[[R0:[0-9]+]], 0(${{[0-9]+}})
+; MICROMIPS:     ll      $[[R1:[0-9]+]], 0($[[R0]])
+; MICROMIPS:     addu    $[[R2:[0-9]+]], $[[R1]], $4
+; MICROMIPS:     sc      $[[R2]], 0($[[R0]])
+; MICROMIPS:     beqzc   $[[R2]],
 }
 
 define i32 @AtomicLoadNand32(i32 signext %incr) nounwind {
@@ -45,6 +59,13 @@
 ; ALL:           nor     $[[R2:[0-9]+]], $zero, $[[R3]]
 ; ALL:           sc      $[[R2]], 0($[[R0]])
 ; ALL:           beqz    $[[R2]], $[[BB0]]
+
+; MICROMIPS:     lw      $[[R0:[0-9]+]], 0(${{[0-9]+}})
+; MICROMIPS:     ll      $[[R1:[0-9]+]], 0($[[R0]])
+; MICROMIPS:     and     $[[R3:[0-9]+]], $[[R1]], $4
+; MICROMIPS:     nor     $[[R2:[0-9]+]], $zero, $[[R3]]
+; MICROMIPS:     sc      $[[R2]], 0($[[R0]])
+; MICROMIPS:     beqzc   $[[R2]],
 }
 
 define i32 @AtomicSwap32(i32 signext %newval) nounwind {
@@ -64,6 +85,11 @@
 ; ALL:           ll      ${{[0-9]+}}, 0($[[R0]])
 ; ALL:           sc      $[[R2:[0-9]+]], 0($[[R0]])
 ; ALL:           beqz    $[[R2]], $[[BB0]]
+
+; MICROMIPS:     lw      $[[R0:[0-9]+]], 0(${{[0-9]+}})
+; MICROMIPS:     ll      ${{[0-9]+}}, 0($[[R0]])
+; MICROMIPS:     sc      $[[R2:[0-9]+]], 0($[[R0]])
+; MICROMIPS:     beqzc   $[[R2]],
 }
 
 define i32 @AtomicCmpSwap32(i32 signext %oldval, i32 signext %newval) nounwind {
@@ -86,6 +112,12 @@
 ; ALL:           sc      $[[R2:[0-9]+]], 0($[[R0]])
 ; ALL:           beqz    $[[R2]], $[[BB0]]
 ; ALL:       $[[BB1]]:
+
+; MICROMIPS:     lw      $[[R0:[0-9]+]], 0(${{[0-9]+}})
+; MICROMIPS:     ll      $2, 0($[[R0]])
+; MICROMIPS:     bne     $2, $4,
+; MICROMIPS:     sc      $[[R2:[0-9]+]], 0($[[R0]])
+; MICROMIPS:     beqzc   $[[R2]],
 }
 
 
@@ -129,6 +161,27 @@
 ; NO-SEB-SEH:    sra     $2, $[[R17]], 24
 
 ; HAS-SEB-SEH:   seb     $2, $[[R16]]
+
+; MICROMIPS:     lw      $[[R0:[0-9]+]], 0(${{[0-9]+}})
+; MICROMIPS:     addiu   $[[R1:[0-9]+]], $zero, -4
+; MICROMIPS:     and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
+; MICROMIPS:     andi    $[[R3:[0-9]+]], $[[R0]], 3
+; MICROMIPS:     sll     $[[R5:[0-9]+]], $[[R3]], 3
+; MICROMIPS:     ori     $[[R6:[0-9]+]], $zero, 255
+; MICROMIPS:     sllv    $[[R7:[0-9]+]], $[[R6]], $[[R5]]
+; MICROMIPS:     nor     $[[R8:[0-9]+]], $zero, $[[R7]]
+; MICROMIPS:     sllv    $[[R9:[0-9]+]], $4, $[[R5]]
+; MICROMIPS:     ll      $[[R10:[0-9]+]], 0($[[R2]])
+; MICROMIPS:     addu    $[[R11:[0-9]+]], $[[R10]], $[[R9]]
+; MICROMIPS:     and     $[[R12:[0-9]+]], $[[R11]], $[[R7]]
+; MICROMIPS:     and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
+; MICROMIPS:     or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
+; MICROMIPS:     sc      $[[R14]], 0($[[R2]])
+; MICROMIPS:     beqzc   $[[R14]],
+; MICROMIPS:     and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
+; MICROMIPS:     srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
+; MICROMIPS:     sll     $[[R17:[0-9]+]], $[[R16]], 24
+; MICROMIPS:     sra     $2, $[[R17]], 24
 }
 
 define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind {
@@ -168,6 +221,27 @@
 ; NO-SEB-SEH: sra     $2, $[[R17]], 24
 
 ; HAS-SEB-SEH:seb     $2, $[[R16]]
+
+; MICROMIPS:  lw      $[[R0:[0-9]+]], 0(${{[0-9]+}})
+; MICROMIPS:  addiu   $[[R1:[0-9]+]], $zero, -4
+; MICROMIPS:  and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
+; MICROMIPS:  andi    $[[R3:[0-9]+]], $[[R0]], 3
+; MICROMIPS:  sll     $[[R5:[0-9]+]], $[[R3]], 3
+; MICROMIPS:  ori     $[[R6:[0-9]+]], $zero, 255
+; MICROMIPS:  sllv    $[[R7:[0-9]+]], $[[R6]], $[[R5]]
+; MICROMIPS:  nor     $[[R8:[0-9]+]], $zero, $[[R7]]
+; MICROMIPS:  sllv    $[[R9:[0-9]+]], $4, $[[R5]]
+; MICROMIPS:  ll      $[[R10:[0-9]+]], 0($[[R2]])
+; MICROMIPS:  subu    $[[R11:[0-9]+]], $[[R10]], $[[R9]]
+; MICROMIPS:  and     $[[R12:[0-9]+]], $[[R11]], $[[R7]]
+; MICROMIPS:  and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
+; MICROMIPS:  or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
+; MICROMIPS:  sc      $[[R14]], 0($[[R2]])
+; MICROMIPS:  beqzc   $[[R14]],
+; MICROMIPS:  and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
+; MICROMIPS:  srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
+; MICROMIPS:  sll     $[[R17:[0-9]+]], $[[R16]], 24
+; MICROMIPS:  sra     $2, $[[R17]], 24
 }
 
 define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind {
@@ -208,6 +282,28 @@
 ; NO-SEB-SEH:    sra     $2, $[[R17]], 24
 
 ; HAS-SEB-SEH:   seb     $2, $[[R16]]
+
+; MICROMIPS:     lw      $[[R0:[0-9]+]], 0(${{[0-9]+}})
+; MICROMIPS:     addiu   $[[R1:[0-9]+]], $zero, -4
+; MICROMIPS:     and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
+; MICROMIPS:     andi    $[[R3:[0-9]+]], $[[R0]], 3
+; MICROMIPS:     sll     $[[R5:[0-9]+]], $[[R3]], 3
+; MICROMIPS:     ori     $[[R6:[0-9]+]], $zero, 255
+; MICROMIPS:     sllv    $[[R7:[0-9]+]], $[[R6]], $[[R5]]
+; MICROMIPS:     nor     $[[R8:[0-9]+]], $zero, $[[R7]]
+; MICROMIPS:     sllv    $[[R9:[0-9]+]], $4, $[[R5]]
+; MICROMIPS:     ll      $[[R10:[0-9]+]], 0($[[R2]])
+; MICROMIPS:     and     $[[R18:[0-9]+]], $[[R10]], $[[R9]]
+; MICROMIPS:     nor     $[[R11:[0-9]+]], $zero, $[[R18]]
+; MICROMIPS:     and     $[[R12:[0-9]+]], $[[R11]], $[[R7]]
+; MICROMIPS:     and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
+; MICROMIPS:     or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
+; MICROMIPS:     sc      $[[R14]], 0($[[R2]])
+; MICROMIPS:     beqzc   $[[R14]],
+; MICROMIPS:     and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
+; MICROMIPS:     srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
+; MICROMIPS:     sll     $[[R17:[0-9]+]], $[[R16]], 24
+; MICROMIPS:     sra     $2, $[[R17]], 24
 }
 
 define signext i8 @AtomicSwap8(i8 signext %newval) nounwind {
@@ -247,6 +343,25 @@
 
 ; HAS-SEB-SEH:   seb     $2, $[[R16]]
 
+; MICROMIPS:     lw      $[[R0:[0-9]+]], 0(${{[0-9]+}})
+; MICROMIPS:     addiu   $[[R1:[0-9]+]], $zero, -4
+; MICROMIPS:     and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
+; MICROMIPS:     andi    $[[R3:[0-9]+]], $[[R0]], 3
+; MICROMIPS:     sll     $[[R5:[0-9]+]], $[[R3]], 3
+; MICROMIPS:     ori     $[[R6:[0-9]+]], $zero, 255
+; MICROMIPS:     sllv    $[[R7:[0-9]+]], $[[R6]], $[[R5]]
+; MICROMIPS:     nor     $[[R8:[0-9]+]], $zero, $[[R7]]
+; MICROMIPS:     sllv    $[[R9:[0-9]+]], $4, $[[R5]]
+; MICROMIPS:     ll      $[[R10:[0-9]+]], 0($[[R2]])
+; MICROMIPS:     and     $[[R18:[0-9]+]], $[[R9]], $[[R7]]
+; MICROMIPS:     and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
+; MICROMIPS:     or      $[[R14:[0-9]+]], $[[R13]], $[[R18]]
+; MICROMIPS:     sc      $[[R14]], 0($[[R2]])
+; MICROMIPS:     beqzc   $[[R14]],
+; MICROMIPS:     and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
+; MICROMIPS:     srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
+; MICROMIPS:     sll     $[[R17:[0-9]+]], $[[R16]], 24
+; MICROMIPS:     sra     $2, $[[R17]], 24
 }
 
 define signext i8 @AtomicCmpSwap8(i8 signext %oldval, i8 signext %newval) nounwind {
@@ -291,6 +406,29 @@
 ; NO-SEB-SEH:    sra     $2, $[[R18]], 24
 
 ; HAS-SEB-SEH:   seb     $2, $[[R17]]
+
+; MICROMIPS:     lw      $[[R0:[0-9]+]], 0(${{[0-9]+}})
+; MICROMIPS:     addiu   $[[R1:[0-9]+]], $zero, -4
+; MICROMIPS:     and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
+; MICROMIPS:     andi    $[[R3:[0-9]+]], $[[R0]], 3
+; MICROMIPS:     sll     $[[R5:[0-9]+]], $[[R3]], 3
+; MICROMIPS:     ori     $[[R6:[0-9]+]], $zero, 255
+; MICROMIPS:     sllv    $[[R7:[0-9]+]], $[[R6]], $[[R5]]
+; MICROMIPS:     nor     $[[R8:[0-9]+]], $zero, $[[R7]]
+; MICROMIPS:     andi    $[[R9:[0-9]+]], $4, 255
+; MICROMIPS:     sllv    $[[R10:[0-9]+]], $[[R9]], $[[R5]]
+; MICROMIPS:     andi    $[[R11:[0-9]+]], $5, 255
+; MICROMIPS:     sllv    $[[R12:[0-9]+]], $[[R11]], $[[R5]]
+; MICROMIPS:     ll      $[[R13:[0-9]+]], 0($[[R2]])
+; MICROMIPS:     and     $[[R14:[0-9]+]], $[[R13]], $[[R7]]
+; MICROMIPS:     bne     $[[R14]], $[[R10]],
+; MICROMIPS:     and     $[[R15:[0-9]+]], $[[R13]], $[[R8]]
+; MICROMIPS:     or      $[[R16:[0-9]+]], $[[R15]], $[[R12]]
+; MICROMIPS:     sc      $[[R16]], 0($[[R2]])
+; MICROMIPS:     beqzc   $[[R16]],
+; MICROMIPS:     srlv    $[[R17:[0-9]+]], $[[R14]], $[[R5]]
+; MICROMIPS:     sll     $[[R18:[0-9]+]], $[[R17]], 24
+; MICROMIPS:     sra     $2, $[[R18]], 24
 }
 
 define i1 @AtomicCmpSwapRes8(i8* %ptr, i8 signext %oldval, i8 signext %newval) nounwind {
@@ -334,6 +472,30 @@
 
 ; ALL:           xor     $[[R20:[0-9]+]], $[[R19]], $5
 ; ALL:           sltiu   $2, $[[R20]], 1
+
+; MICROMIPS:     addiu   $[[R1:[0-9]+]], $zero, -4
+; MICROMIPS:     and     $[[R2:[0-9]+]], $4, $[[R1]]
+; MICROMIPS:     andi    $[[R3:[0-9]+]], $4, 3
+; MICROMIPS:     sll     $[[R5:[0-9]+]], $[[R3]], 3
+; MICROMIPS:     ori     $[[R6:[0-9]+]], $zero, 255
+; MICROMIPS:     sllv    $[[R7:[0-9]+]], $[[R6]], $[[R5]]
+; MICROMIPS:     nor     $[[R8:[0-9]+]], $zero, $[[R7]]
+; MICROMIPS:     andi    $[[R9:[0-9]+]], $5, 255
+; MICROMIPS:     sllv    $[[R10:[0-9]+]], $[[R9]], $[[R5]]
+; MICROMIPS:     andi    $[[R11:[0-9]+]], $6, 255
+; MICROMIPS:     sllv    $[[R12:[0-9]+]], $[[R11]], $[[R5]]
+; MICROMIPS:     ll      $[[R13:[0-9]+]], 0($[[R2]])
+; MICROMIPS:     and     $[[R14:[0-9]+]], $[[R13]], $[[R7]]
+; MICROMIPS:     bne     $[[R14]], $[[R10]],
+; MICROMIPS:     and     $[[R15:[0-9]+]], $[[R13]], $[[R8]]
+; MICROMIPS:     or      $[[R16:[0-9]+]], $[[R15]], $[[R12]]
+; MICROMIPS:     sc      $[[R16]], 0($[[R2]])
+; MICROMIPS:     beqzc   $[[R16]],
+; MICROMIPS:     srlv    $[[R17:[0-9]+]], $[[R14]], $[[R5]]
+; MICROMIPS:     sll     $[[R18:[0-9]+]], $[[R17]], 24
+; MICROMIPS:     sra     $[[R19:[0-9]+]], $[[R18]], 24
+; MICROMIPS:     xor     $[[R20:[0-9]+]], $[[R19]], $5
+; MICROMIPS:     sltiu   $2, $[[R20]], 1
 }
 
 ; Check one i16 so that we cover the seh sign extend
@@ -376,6 +538,27 @@
 ; NO-SEB-SEH:    sra     $2, $[[R17]], 16
 
 ; MIPS32R2:      seh     $2, $[[R16]]
+
+; MICROMIPS:     lw      $[[R0:[0-9]+]], 0(${{[0-9]+}})
+; MICROMIPS:     addiu   $[[R1:[0-9]+]], $zero, -4
+; MICROMIPS:     and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
+; MICROMIPS:     andi    $[[R3:[0-9]+]], $[[R0]], 3
+; MICROMIPS:     sll     $[[R5:[0-9]+]], $[[R3]], 3
+; MICROMIPS:     ori     $[[R6:[0-9]+]], $zero, 65535
+; MICROMIPS:     sllv    $[[R7:[0-9]+]], $[[R6]], $[[R5]]
+; MICROMIPS:     nor     $[[R8:[0-9]+]], $zero, $[[R7]]
+; MICROMIPS:     sllv    $[[R9:[0-9]+]], $4, $[[R5]]
+; MICROMIPS:     ll      $[[R10:[0-9]+]], 0($[[R2]])
+; MICROMIPS:     addu    $[[R11:[0-9]+]], $[[R10]], $[[R9]]
+; MICROMIPS:     and     $[[R12:[0-9]+]], $[[R11]], $[[R7]]
+; MICROMIPS:     and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
+; MICROMIPS:     or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
+; MICROMIPS:     sc      $[[R14]], 0($[[R2]])
+; MICROMIPS:     beqzc   $[[R14]],
+; MICROMIPS:     and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
+; MICROMIPS:     srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
+; MICROMIPS:     sll     $[[R17:[0-9]+]], $[[R16]], 16
+; MICROMIPS:     sra     $2, $[[R17]], 16
 }
 
 
@@ -393,6 +576,12 @@
 ; ALL:           sc
 ; ALL:           beq
 ; ALL:           sync
+
+; MICROMIPS:     sync
+; MICROMIPS:     ll
+; MICROMIPS:     sc
+; MICROMIPS:     beq
+; MICROMIPS:     sync
 }
 
 ; make sure that this assertion in
@@ -431,4 +620,11 @@
 ; ALL:           addu    $[[R2:[0-9]+]], $[[R1]], $4
 ; ALL:           sc      $[[R2]], 0($[[PTR]])
 ; ALL:           beqz    $[[R2]], $[[BB0]]
+
+; MICROMIPS:     lw      $[[R0:[0-9]+]], 0($[[R0]])
+; MICROMIPS:     addiu   $[[PTR:[0-9]+]], $[[R0]], 1024
+; MICROMIPS:     ll      $[[R1:[0-9]+]], 0($[[PTR]])
+; MICROMIPS:     addu    $[[R2:[0-9]+]], $[[R1]], $4
+; MICROMIPS:     sc      $[[R2]], 0($[[PTR]])
+; MICROMIPS:     beqzc   $[[R2]],
 }