Index: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp =================================================================== --- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -3039,18 +3039,22 @@ break; case ARM::VSELEQD: case ARM::VSELEQS: + case ARM::VSELEQH: CC = ARMCC::EQ; break; case ARM::VSELGTD: case ARM::VSELGTS: + case ARM::VSELGTH: CC = ARMCC::GT; break; case ARM::VSELGED: case ARM::VSELGES: + case ARM::VSELGEH: CC = ARMCC::GE; break; - case ARM::VSELVSS: case ARM::VSELVSD: + case ARM::VSELVSS: + case ARM::VSELVSH: CC = ARMCC::VS; break; } Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp =================================================================== --- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -43,6 +43,8 @@ cl::desc("Disable isel of shifter-op"), cl::init(false)); +extern cl::opt ARMGenerateCSEL; + //===--------------------------------------------------------------------===// /// ARMDAGToDAGISel - ARM specific code to select ARM machine /// instructions for SelectionDAG operations. Index: llvm/lib/Target/ARM/ARMISelLowering.h =================================================================== --- llvm/lib/Target/ARM/ARMISelLowering.h +++ llvm/lib/Target/ARM/ARMISelLowering.h @@ -240,6 +240,11 @@ // instructions. MEMCPY, + // V8.1MMainline condition select + CSINV, // Conditional select invert. + CSNEG, // Conditional select negate. + CSINC, // Conditional select increment. + // Vector load N-element structure to all lanes: VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE, VLD2DUP, Index: llvm/lib/Target/ARM/ARMISelLowering.cpp =================================================================== --- llvm/lib/Target/ARM/ARMISelLowering.cpp +++ llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -142,6 +142,9 @@ cl::desc("Maximum size of ALL constants to promote into a constant pool"), cl::init(128)); +cl::opt ARMGenerateCSEL( + "arm-csel", cl::desc("Enable v8.1-m CSEL generation"), cl::init(true)); + // The APCS parameter registers. static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 @@ -1634,6 +1637,9 @@ case ARMISD::WLS: return "ARMISD::WLS"; case ARMISD::LE: return "ARMISD::LE"; case ARMISD::LOOP_DEC: return "ARMISD::LOOP_DEC"; + case ARMISD::CSINV: return "ARMISD::CSINV"; + case ARMISD::CSNEG: return "ARMISD::CSNEG"; + case ARMISD::CSINC: return "ARMISD::CSINC"; } return nullptr; } @@ -4815,6 +4821,52 @@ ISD::CondCode CC = cast(Op.getOperand(4))->get(); SDValue TrueVal = Op.getOperand(2); SDValue FalseVal = Op.getOperand(3); + ConstantSDNode *CFVal = dyn_cast(FalseVal); + ConstantSDNode *CTVal = dyn_cast(TrueVal); + + if (Subtarget->hasV8_1MMainlineOps() && ARMGenerateCSEL && + LHS.getValueType() == MVT::i32 && RHS.getValueType() == MVT::i32) { + if (CFVal && CTVal) { + unsigned TVal = CTVal->getZExtValue(); + unsigned FVal = CFVal->getZExtValue(); + unsigned Opcode = 0; + + if (TVal == ~FVal) { + Opcode = ARMISD::CSINV; + } else if (TVal == ~FVal + 1) { + Opcode = ARMISD::CSNEG; + } else if (TVal + 1 == FVal) { + Opcode = ARMISD::CSINC; + } else if (TVal == FVal + 1) { + Opcode = ARMISD::CSINC; + std::swap(TrueVal, FalseVal); + std::swap(TVal, FVal); + CC = ISD::getSetCCInverse(CC, true); + } + + if (Opcode) { + // Drops F's value because we can get it by inverting/negating TVal. + FalseVal = TrueVal; + + // Attempt to use ZR checking TVal is 0, possibly inverting the + // condition to get there. + if (FVal == 0 && Opcode != ARMISD::CSINC) { + std::swap(TrueVal, FalseVal); + std::swap(TVal, FVal); + CC = ISD::getSetCCInverse(CC, true); + } + if (TVal == 0) { + TrueVal = DAG.getRegister(ARM::ZR, MVT::i32); + FalseVal = DAG.getRegister(ARM::ZR, MVT::i32); + } + + SDValue ARMcc; + SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); + EVT VT = TrueVal.getValueType(); + return DAG.getNode(Opcode, dl, VT, TrueVal, FalseVal, ARMcc, Cmp); + } + } + } if (isUnsupportedFloatingType(LHS.getValueType())) { DAG.getTargetLoweringInfo().softenSetCCOperands( Index: llvm/lib/Target/ARM/ARMInstrFormats.td =================================================================== --- llvm/lib/Target/ARM/ARMInstrFormats.td +++ llvm/lib/Target/ARM/ARMInstrFormats.td @@ -188,6 +188,13 @@ let DecoderMethod = "DecodeCCOutOperand"; } +// Transform to generate the inverse of a condition code during ISel +def inv_cond_XFORM : SDNodeXForm(N->getZExtValue()); + return CurDAG->getTargetConstant(ARMCC::getOppositeCondition(CC), SDLoc(N), + MVT::i32); +}]>; + // VPT predicate def VPTPredNOperand : AsmOperandClass { Index: llvm/lib/Target/ARM/ARMInstrInfo.td =================================================================== --- llvm/lib/Target/ARM/ARMInstrInfo.td +++ llvm/lib/Target/ARM/ARMInstrInfo.td @@ -116,6 +116,16 @@ def ARMSmlsld : SDNode<"ARMISD::SMLSLD", SDT_LongMac>; def ARMSmlsldx : SDNode<"ARMISD::SMLSLDX", SDT_LongMac>; +def SDT_ARMCSel : SDTypeProfile<1, 3, + [SDTCisSameAs<0, 1>, + SDTCisSameAs<0, 2>, + SDTCisInt<3>, + SDTCisVT<3, i32>]>; + +def ARMcsinv : SDNode<"ARMISD::CSINV", SDT_ARMCSel, [SDNPOptInGlue]>; +def ARMcsneg : SDNode<"ARMISD::CSNEG", SDT_ARMCSel, [SDNPOptInGlue]>; +def ARMcsinc : SDNode<"ARMISD::CSINC", SDT_ARMCSel, [SDNPOptInGlue]>; + def SDT_MulHSR : SDTypeProfile<1, 3, [SDTCisVT<0,i32>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, Index: llvm/lib/Target/ARM/ARMInstrThumb2.td =================================================================== --- llvm/lib/Target/ARM/ARMInstrThumb2.td +++ llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -5257,6 +5257,27 @@ def t2CSINV : CS<"csinv", 0b1010>; def t2CSNEG : CS<"csneg", 0b1011>; +def GenerateCSEL : Predicate<"ARMGenerateCSEL">; + +let Predicates = [HasV8_1MMainline, GenerateCSEL] in { + def : T2Pat<(ARMcsinc GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm), + (t2CSINC GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm)>; + def : T2Pat<(ARMcsinv GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm), + (t2CSINV GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm)>; + def : T2Pat<(ARMcsneg GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm), + (t2CSNEG GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm)>; + + multiclass ModifiedV8_1CSEL { + def : T2Pat<(ARMcmov modvalue, GPRwithZR:$tval, cmovpred:$imm), + (Insn GPRwithZR:$tval, GPRwithZR:$fval, imm0_31:$imm)>; + def : T2Pat<(ARMcmov GPRwithZR:$tval, modvalue, cmovpred:$imm), + (Insn GPRwithZR:$tval, GPRwithZR:$fval, + (i32 (inv_cond_XFORM imm:$imm)))>; + } + defm : ModifiedV8_1CSEL; + defm : ModifiedV8_1CSEL; + defm : ModifiedV8_1CSEL; +} // CS aliases. let Predicates = [HasV8_1MMainline] in { Index: llvm/lib/Target/ARM/ARMInstructionSelector.cpp =================================================================== --- llvm/lib/Target/ARM/ARMInstructionSelector.cpp +++ llvm/lib/Target/ARM/ARMInstructionSelector.cpp @@ -163,6 +163,8 @@ const unsigned zero_reg = 0; +extern cl::opt ARMGenerateCSEL; + #define GET_GLOBALISEL_IMPL #include "ARMGenGlobalISel.inc" #undef GET_GLOBALISEL_IMPL Index: llvm/test/CodeGen/Thumb2/csel.ll =================================================================== --- llvm/test/CodeGen/Thumb2/csel.ll +++ llvm/test/CodeGen/Thumb2/csel.ll @@ -6,9 +6,7 @@ ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: movs r1, #5 ; CHECK-NEXT: cmp r0, #45 -; CHECK-NEXT: it gt -; CHECK-NEXT: movgt r1, #6 -; CHECK-NEXT: mov r0, r1 +; CHECK-NEXT: csinc r0, r1, r1, le ; CHECK-NEXT: bx lr entry: %cmp = icmp sgt i32 %a, 45 @@ -19,11 +17,9 @@ define i32 @csinc_const_56(i32 %a) { ; CHECK-LABEL: csinc_const_56: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: movs r1, #6 +; CHECK-NEXT: movs r1, #5 ; CHECK-NEXT: cmp r0, #45 -; CHECK-NEXT: it gt -; CHECK-NEXT: movgt r1, #5 -; CHECK-NEXT: mov r0, r1 +; CHECK-NEXT: csinc r0, r1, r1, gt ; CHECK-NEXT: bx lr entry: %cmp = icmp sgt i32 %a, 45 @@ -34,11 +30,8 @@ define i32 @csinc_const_zext(i32 %a) { ; CHECK-LABEL: csinc_const_zext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: movs r1, #0 ; CHECK-NEXT: cmp r0, #45 -; CHECK-NEXT: it gt -; CHECK-NEXT: movgt r1, #1 -; CHECK-NEXT: mov r0, r1 +; CHECK-NEXT: csinc r0, zr, zr, le ; CHECK-NEXT: bx lr entry: %cmp = icmp sgt i32 %a, 45 @@ -49,11 +42,9 @@ define i32 @csinv_const_56(i32 %a) { ; CHECK-LABEL: csinv_const_56: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: movs r1, #5 +; CHECK-NEXT: mvn r1, #5 ; CHECK-NEXT: cmp r0, #45 -; CHECK-NEXT: it gt -; CHECK-NEXT: mvngt r1, #5 -; CHECK-NEXT: mov r0, r1 +; CHECK-NEXT: csinv r0, r1, r1, gt ; CHECK-NEXT: bx lr entry: %cmp = icmp sgt i32 %a, 45 @@ -64,11 +55,9 @@ define i32 @csinv_const_65(i32 %a) { ; CHECK-LABEL: csinv_const_65: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: mvn r1, #5 +; CHECK-NEXT: movs r1, #5 ; CHECK-NEXT: cmp r0, #45 -; CHECK-NEXT: it gt -; CHECK-NEXT: movgt r1, #5 -; CHECK-NEXT: mov r0, r1 +; CHECK-NEXT: csinv r0, r1, r1, gt ; CHECK-NEXT: bx lr entry: %cmp = icmp sgt i32 %a, 45 @@ -79,11 +68,8 @@ define i32 @csinv_const_sext(i32 %a) { ; CHECK-LABEL: csinv_const_sext: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: movs r1, #0 ; CHECK-NEXT: cmp r0, #45 -; CHECK-NEXT: it gt -; CHECK-NEXT: movgt.w r1, #-1 -; CHECK-NEXT: mov r0, r1 +; CHECK-NEXT: csinv r0, zr, zr, le ; CHECK-NEXT: bx lr entry: %cmp = icmp sgt i32 %a, 45 @@ -94,11 +80,9 @@ define i32 @csneg_const(i32 %a) { ; CHECK-LABEL: csneg_const: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: mov.w r1, #-1 +; CHECK-NEXT: movs r1, #1 ; CHECK-NEXT: cmp r0, #45 -; CHECK-NEXT: it gt -; CHECK-NEXT: movgt r1, #1 -; CHECK-NEXT: mov r0, r1 +; CHECK-NEXT: csneg r0, r1, r1, gt ; CHECK-NEXT: bx lr entry: %cmp = icmp sgt i32 %a, 45 @@ -109,11 +93,9 @@ define i32 @csneg_const_r(i32 %a) { ; CHECK-LABEL: csneg_const_r: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: movs r1, #1 +; CHECK-NEXT: mov.w r1, #-1 ; CHECK-NEXT: cmp r0, #45 -; CHECK-NEXT: it gt -; CHECK-NEXT: movgt.w r1, #-1 -; CHECK-NEXT: mov r0, r1 +; CHECK-NEXT: csneg r0, r1, r1, gt ; CHECK-NEXT: bx lr entry: %cmp = icmp sgt i32 %a, 45 @@ -139,9 +121,7 @@ ; CHECK-LABEL: csinc_var: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: cmp r0, #45 -; CHECK-NEXT: it le -; CHECK-NEXT: addle r1, r2, #1 -; CHECK-NEXT: mov r0, r1 +; CHECK-NEXT: csinc r0, r1, r2, gt ; CHECK-NEXT: bx lr entry: %cmp = icmp sgt i32 %a, 45 @@ -154,9 +134,7 @@ ; CHECK-LABEL: csinc_swap_var: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: cmp r0, #45 -; CHECK-NEXT: it gt -; CHECK-NEXT: addgt r2, r1, #1 -; CHECK-NEXT: mov r0, r2 +; CHECK-NEXT: csinc r0, r2, r1, le ; CHECK-NEXT: bx lr entry: %cmp = icmp sgt i32 %a, 45 @@ -169,9 +147,7 @@ ; CHECK-LABEL: csinv_var: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: cmp r0, #45 -; CHECK-NEXT: it le -; CHECK-NEXT: mvnle r1, r2 -; CHECK-NEXT: mov r0, r1 +; CHECK-NEXT: csinv r0, r1, r2, gt ; CHECK-NEXT: bx lr entry: %cmp = icmp sgt i32 %a, 45 @@ -184,9 +160,7 @@ ; CHECK-LABEL: csinv_swap_var: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: cmp r0, #45 -; CHECK-NEXT: it gt -; CHECK-NEXT: mvngt r2, r1 -; CHECK-NEXT: mov r0, r2 +; CHECK-NEXT: csinv r0, r2, r1, le ; CHECK-NEXT: bx lr entry: %cmp = icmp sgt i32 %a, 45 @@ -199,9 +173,7 @@ ; CHECK-LABEL: csneg_var: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: cmp r0, #45 -; CHECK-NEXT: it le -; CHECK-NEXT: rsble r1, r2, #0 -; CHECK-NEXT: mov r0, r1 +; CHECK-NEXT: csneg r0, r1, r2, gt ; CHECK-NEXT: bx lr entry: %cmp = icmp sgt i32 %a, 45 @@ -214,9 +186,7 @@ ; CHECK-LABEL: csneg_swap_var: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: cmp r0, #45 -; CHECK-NEXT: it gt -; CHECK-NEXT: rsbgt r2, r1, #0 -; CHECK-NEXT: mov r0, r2 +; CHECK-NEXT: csneg r0, r2, r1, le ; CHECK-NEXT: bx lr entry: %cmp = icmp sgt i32 %a, 45 @@ -229,8 +199,7 @@ ; CHECK-LABEL: csinc_inplace: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: cmp r1, #45 -; CHECK-NEXT: it gt -; CHECK-NEXT: addgt r0, #1 +; CHECK-NEXT: csinc r0, r0, r0, le ; CHECK-NEXT: bx lr entry: %cmp = icmp sgt i32 %b, 45 @@ -243,8 +212,7 @@ ; CHECK-LABEL: csinv_inplace: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: cmp r1, #45 -; CHECK-NEXT: it gt -; CHECK-NEXT: mvngt r0, r0 +; CHECK-NEXT: csinv r0, r0, r0, le ; CHECK-NEXT: bx lr entry: %cmp = icmp sgt i32 %b, 45 Index: llvm/test/CodeGen/Thumb2/mve-abs.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-abs.ll +++ llvm/test/CodeGen/Thumb2/mve-abs.ll @@ -40,39 +40,36 @@ define arm_aapcs_vfpcc <2 x i64> @abs_v2i64(<2 x i64> %s1) { ; CHECK-LABEL: abs_v2i64: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: .save {r4, r5, r6, lr} -; CHECK-NEXT: push {r4, r5, r6, lr} -; CHECK-NEXT: vmov r12, s2 -; CHECK-NEXT: movs r2, #0 -; CHECK-NEXT: vmov r0, s3 -; CHECK-NEXT: movs r1, #0 -; CHECK-NEXT: vmov r4, s0 -; CHECK-NEXT: rsbs.w r3, r12, #0 -; CHECK-NEXT: sbc.w lr, r2, r0 +; CHECK-NEXT: .save {r7, lr} +; CHECK-NEXT: push {r7, lr} +; CHECK-NEXT: vmov q1, q0 +; CHECK-NEXT: mov.w r12, #0 +; CHECK-NEXT: vmov lr, s4 +; CHECK-NEXT: vmov r0, s5 +; CHECK-NEXT: rsbs.w r3, lr, #0 +; CHECK-NEXT: sbc.w r2, r12, r0 ; CHECK-NEXT: cmp r0, #0 -; CHECK-NEXT: it mi -; CHECK-NEXT: movmi r1, #1 -; CHECK-NEXT: cmp r1, #0 -; CHECK-NEXT: it eq -; CHECK-NEXT: moveq lr, r0 -; CHECK-NEXT: vmov r0, s1 -; CHECK-NEXT: rsbs r5, r4, #0 -; CHECK-NEXT: sbc.w r6, r2, r0 -; CHECK-NEXT: cmp r0, #0 -; CHECK-NEXT: it mi -; CHECK-NEXT: movmi r2, #1 -; CHECK-NEXT: cmp r2, #0 +; CHECK-NEXT: csinc r1, zr, zr, pl +; CHECK-NEXT: ands r1, r1, #1 ; CHECK-NEXT: itt eq -; CHECK-NEXT: moveq r6, r0 -; CHECK-NEXT: moveq r5, r4 -; CHECK-NEXT: vmov.32 q0[0], r5 -; CHECK-NEXT: vmov.32 q0[1], r6 -; CHECK-NEXT: cmp r1, #0 +; CHECK-NEXT: moveq r2, r0 +; CHECK-NEXT: moveq r3, lr +; CHECK-NEXT: vmov lr, s6 +; CHECK-NEXT: vmov.32 q0[0], r3 +; CHECK-NEXT: vmov r0, s7 +; CHECK-NEXT: vmov.32 q0[1], r2 +; CHECK-NEXT: rsbs.w r2, lr, #0 +; CHECK-NEXT: sbc.w r3, r12, r0 +; CHECK-NEXT: cmp r0, #0 +; CHECK-NEXT: csinc r1, zr, zr, pl +; CHECK-NEXT: ands r1, r1, #1 +; CHECK-NEXT: it eq +; CHECK-NEXT: moveq r2, lr +; CHECK-NEXT: vmov.32 q0[2], r2 ; CHECK-NEXT: it eq -; CHECK-NEXT: moveq r3, r12 -; CHECK-NEXT: vmov.32 q0[2], r3 -; CHECK-NEXT: vmov.32 q0[3], lr -; CHECK-NEXT: pop {r4, r5, r6, pc} +; CHECK-NEXT: moveq r3, r0 +; CHECK-NEXT: vmov.32 q0[3], r3 +; CHECK-NEXT: pop {r7, pc} entry: %0 = icmp slt <2 x i64> %s1, zeroinitializer %1 = sub nsw <2 x i64> zeroinitializer, %s1 Index: llvm/test/CodeGen/Thumb2/mve-fmath.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-fmath.ll +++ llvm/test/CodeGen/Thumb2/mve-fmath.ll @@ -1460,21 +1460,19 @@ ; CHECK-NEXT: vmov s4, r0 ; CHECK-NEXT: ldrb.w r0, [sp, #25] ; CHECK-NEXT: vabs.f16 s4, s4 -; CHECK-NEXT: ands r0, r0, #128 +; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: vneg.f16 s6, s4 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne r0, #1 -; CHECK-NEXT: cmp r0, #0 +; CHECK-NEXT: csinc r0, zr, zr, eq +; CHECK-NEXT: lsls r0, r0, #31 ; CHECK-NEXT: vseleq.f16 s4, s4, s6 ; CHECK-NEXT: vmov r0, s4 ; CHECK-NEXT: vmov s4, r1 ; CHECK-NEXT: ldrb.w r1, [sp, #29] ; CHECK-NEXT: vabs.f16 s4, s4 -; CHECK-NEXT: ands r1, r1, #128 +; CHECK-NEXT: tst.w r1, #128 ; CHECK-NEXT: vneg.f16 s6, s4 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne r1, #1 -; CHECK-NEXT: cmp r1, #0 +; CHECK-NEXT: csinc r1, zr, zr, eq +; CHECK-NEXT: lsls r1, r1, #31 ; CHECK-NEXT: vseleq.f16 s4, s4, s6 ; CHECK-NEXT: vmov r1, s4 ; CHECK-NEXT: vmov.16 q1[0], r1 @@ -1483,11 +1481,10 @@ ; CHECK-NEXT: vmov s8, r0 ; CHECK-NEXT: ldrb.w r0, [sp, #21] ; CHECK-NEXT: vabs.f16 s8, s8 -; CHECK-NEXT: ands r0, r0, #128 +; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: vneg.f16 s10, s8 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne r0, #1 -; CHECK-NEXT: cmp r0, #0 +; CHECK-NEXT: csinc r0, zr, zr, eq +; CHECK-NEXT: lsls r0, r0, #31 ; CHECK-NEXT: vseleq.f16 s8, s8, s10 ; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vmov.16 q1[2], r0 @@ -1495,11 +1492,10 @@ ; CHECK-NEXT: vmov s8, r0 ; CHECK-NEXT: ldrb.w r0, [sp, #17] ; CHECK-NEXT: vabs.f16 s8, s8 -; CHECK-NEXT: ands r0, r0, #128 +; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: vneg.f16 s10, s8 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne r0, #1 -; CHECK-NEXT: cmp r0, #0 +; CHECK-NEXT: csinc r0, zr, zr, eq +; CHECK-NEXT: lsls r0, r0, #31 ; CHECK-NEXT: vseleq.f16 s8, s8, s10 ; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vmov.16 q1[3], r0 @@ -1507,11 +1503,10 @@ ; CHECK-NEXT: vmov s8, r0 ; CHECK-NEXT: ldrb.w r0, [sp, #13] ; CHECK-NEXT: vabs.f16 s8, s8 -; CHECK-NEXT: ands r0, r0, #128 +; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: vneg.f16 s10, s8 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne r0, #1 -; CHECK-NEXT: cmp r0, #0 +; CHECK-NEXT: csinc r0, zr, zr, eq +; CHECK-NEXT: lsls r0, r0, #31 ; CHECK-NEXT: vseleq.f16 s8, s8, s10 ; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vmov.16 q1[4], r0 @@ -1519,11 +1514,10 @@ ; CHECK-NEXT: vmov s8, r0 ; CHECK-NEXT: ldrb.w r0, [sp, #9] ; CHECK-NEXT: vabs.f16 s8, s8 -; CHECK-NEXT: ands r0, r0, #128 +; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: vneg.f16 s10, s8 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne r0, #1 -; CHECK-NEXT: cmp r0, #0 +; CHECK-NEXT: csinc r0, zr, zr, eq +; CHECK-NEXT: lsls r0, r0, #31 ; CHECK-NEXT: vseleq.f16 s8, s8, s10 ; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vmov.16 q1[5], r0 @@ -1531,11 +1525,10 @@ ; CHECK-NEXT: vmov s8, r0 ; CHECK-NEXT: ldrb.w r0, [sp, #5] ; CHECK-NEXT: vabs.f16 s8, s8 -; CHECK-NEXT: ands r0, r0, #128 +; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: vneg.f16 s10, s8 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne r0, #1 -; CHECK-NEXT: cmp r0, #0 +; CHECK-NEXT: csinc r0, zr, zr, eq +; CHECK-NEXT: lsls r0, r0, #31 ; CHECK-NEXT: vseleq.f16 s8, s8, s10 ; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vmov.16 q1[6], r0 @@ -1543,11 +1536,10 @@ ; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: ldrb.w r0, [sp, #1] ; CHECK-NEXT: vabs.f16 s0, s0 -; CHECK-NEXT: ands r0, r0, #128 +; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: vneg.f16 s2, s0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne r0, #1 -; CHECK-NEXT: cmp r0, #0 +; CHECK-NEXT: csinc r0, zr, zr, eq +; CHECK-NEXT: lsls r0, r0, #31 ; CHECK-NEXT: vseleq.f16 s0, s0, s2 ; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov.16 q1[7], r0 Index: llvm/test/CodeGen/Thumb2/mve-minmax.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-minmax.ll +++ llvm/test/CodeGen/Thumb2/mve-minmax.ll @@ -55,15 +55,13 @@ ; CHECK-NEXT: it lt ; CHECK-NEXT: movlt r1, #1 ; CHECK-NEXT: cmp r1, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r1, #-1 +; CHECK-NEXT: csinv r1, zr, zr, eq ; CHECK-NEXT: subs r2, r3, r2 ; CHECK-NEXT: sbcs.w r2, lr, r12 ; CHECK-NEXT: it lt ; CHECK-NEXT: movlt r0, #1 ; CHECK-NEXT: cmp r0, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q2[0], r0 ; CHECK-NEXT: vmov.32 q2[1], r0 ; CHECK-NEXT: vmov.32 q2[2], r1 @@ -131,15 +129,13 @@ ; CHECK-NEXT: it lo ; CHECK-NEXT: movlo r1, #1 ; CHECK-NEXT: cmp r1, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r1, #-1 +; CHECK-NEXT: csinv r1, zr, zr, eq ; CHECK-NEXT: subs r2, r3, r2 ; CHECK-NEXT: sbcs.w r2, lr, r12 ; CHECK-NEXT: it lo ; CHECK-NEXT: movlo r0, #1 ; CHECK-NEXT: cmp r0, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q2[0], r0 ; CHECK-NEXT: vmov.32 q2[1], r0 ; CHECK-NEXT: vmov.32 q2[2], r1 @@ -208,15 +204,13 @@ ; CHECK-NEXT: it lt ; CHECK-NEXT: movlt r1, #1 ; CHECK-NEXT: cmp r1, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r1, #-1 +; CHECK-NEXT: csinv r1, zr, zr, eq ; CHECK-NEXT: subs r2, r3, r2 ; CHECK-NEXT: sbcs.w r2, lr, r12 ; CHECK-NEXT: it lt ; CHECK-NEXT: movlt r0, #1 ; CHECK-NEXT: cmp r0, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q2[0], r0 ; CHECK-NEXT: vmov.32 q2[1], r0 ; CHECK-NEXT: vmov.32 q2[2], r1 @@ -284,15 +278,13 @@ ; CHECK-NEXT: it lo ; CHECK-NEXT: movlo r1, #1 ; CHECK-NEXT: cmp r1, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r1, #-1 +; CHECK-NEXT: csinv r1, zr, zr, eq ; CHECK-NEXT: subs r2, r3, r2 ; CHECK-NEXT: sbcs.w r2, lr, r12 ; CHECK-NEXT: it lo ; CHECK-NEXT: movlo r0, #1 ; CHECK-NEXT: cmp r0, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q2[0], r0 ; CHECK-NEXT: vmov.32 q2[1], r0 ; CHECK-NEXT: vmov.32 q2[2], r1 @@ -412,22 +404,20 @@ ; CHECK-NEXT: vmov r0, r1, d9 ; CHECK-NEXT: vmov r2, r3, d11 ; CHECK-NEXT: bl __aeabi_dcmpgt -; CHECK-NEXT: mov r4, r0 -; CHECK-NEXT: vmov r0, r1, d8 +; CHECK-NEXT: vmov r12, r1, d8 +; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: vmov r2, r3, d10 -; CHECK-NEXT: cmp r4, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne r4, #1 -; CHECK-NEXT: cmp r4, #0 ; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r4, #-1 +; CHECK-NEXT: movne r0, #1 +; CHECK-NEXT: cmp r0, #0 +; CHECK-NEXT: csinv r4, zr, zr, eq +; CHECK-NEXT: mov r0, r12 ; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: it ne ; CHECK-NEXT: movne r0, #1 ; CHECK-NEXT: cmp r0, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q0[0], r0 ; CHECK-NEXT: vmov.32 q0[1], r0 ; CHECK-NEXT: vmov.32 q0[2], r4 Index: llvm/test/CodeGen/Thumb2/mve-pred-and.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-pred-and.ll +++ llvm/test/CodeGen/Thumb2/mve-pred-and.ll @@ -612,18 +612,16 @@ ; CHECK-NEXT: vmov r1, s8 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s10 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[0], r0 ; CHECK-NEXT: vmov.32 q3[1], r0 ; CHECK-NEXT: vmov r0, s11 ; CHECK-NEXT: orrs r0, r1 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vbic q1, q1, q3 @@ -650,10 +648,9 @@ ; CHECK-NEXT: vmov r2, s6 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s7 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[0], r0 ; CHECK-NEXT: vmov.32 q3[1], r0 ; CHECK-NEXT: vmov r0, s11 @@ -662,27 +659,24 @@ ; CHECK-NEXT: eors r1, r2 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s0 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s2 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q2[0], r0 ; CHECK-NEXT: vmov.32 q2[1], r0 ; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: orrs r0, r1 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q2[2], r0 ; CHECK-NEXT: vmov.32 q2[3], r0 ; CHECK-NEXT: vand q2, q2, q3 @@ -706,10 +700,9 @@ ; CHECK-NEXT: eors r2, r1 ; CHECK-NEXT: eors r3, r0 ; CHECK-NEXT: orrs r2, r3 -; CHECK-NEXT: clz r2, r2 -; CHECK-NEXT: lsrs r2, r2, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r2, #-1 +; CHECK-NEXT: csinc r2, zr, zr, ne +; CHECK-NEXT: tst.w r2, #1 +; CHECK-NEXT: csinv r2, zr, zr, eq ; CHECK-NEXT: vmov.32 q2[0], r2 ; CHECK-NEXT: vmov.32 q2[1], r2 ; CHECK-NEXT: vmov r2, s7 @@ -718,27 +711,24 @@ ; CHECK-NEXT: eors r0, r2 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s0 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q2[2], r0 ; CHECK-NEXT: vmov.32 q2[3], r0 ; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s2 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[0], r0 ; CHECK-NEXT: vmov.32 q3[1], r0 ; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: orrs r0, r1 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vand q2, q3, q2 Index: llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll +++ llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll @@ -6,13 +6,12 @@ ; CHECK-LABEL: build_var0_v4i1: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: cmp r0, r1 -; CHECK-NEXT: mov.w r0, #0 -; CHECK-NEXT: it lo -; CHECK-NEXT: movlo r0, #1 -; CHECK-NEXT: movs r2, #0 +; CHECK-NEXT: mov.w r1, #0 +; CHECK-NEXT: csinc r0, zr, zr, hs +; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: rsbs r0, r0, #0 -; CHECK-NEXT: bfi r2, r0, #0, #4 -; CHECK-NEXT: vmsr p0, r2 +; CHECK-NEXT: bfi r1, r0, #0, #4 +; CHECK-NEXT: vmsr p0, r1 ; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: bx lr entry: @@ -26,13 +25,12 @@ ; CHECK-LABEL: build_var3_v4i1: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: cmp r0, r1 -; CHECK-NEXT: mov.w r0, #0 -; CHECK-NEXT: it lo -; CHECK-NEXT: movlo r0, #1 -; CHECK-NEXT: movs r2, #0 +; CHECK-NEXT: mov.w r1, #0 +; CHECK-NEXT: csinc r0, zr, zr, hs +; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: rsbs r0, r0, #0 -; CHECK-NEXT: bfi r2, r0, #12, #4 -; CHECK-NEXT: vmsr p0, r2 +; CHECK-NEXT: bfi r1, r0, #12, #4 +; CHECK-NEXT: vmsr p0, r1 ; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: bx lr entry: @@ -46,16 +44,15 @@ ; CHECK-LABEL: build_varN_v4i1: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: cmp r0, r1 -; CHECK-NEXT: mov.w r0, #0 -; CHECK-NEXT: it lo -; CHECK-NEXT: movlo r0, #1 -; CHECK-NEXT: movs r2, #0 +; CHECK-NEXT: mov.w r1, #0 +; CHECK-NEXT: csinc r0, zr, zr, hs +; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: rsbs r0, r0, #0 -; CHECK-NEXT: bfi r2, r0, #0, #4 -; CHECK-NEXT: bfi r2, r0, #4, #4 -; CHECK-NEXT: bfi r2, r0, #8, #4 -; CHECK-NEXT: bfi r2, r0, #12, #4 -; CHECK-NEXT: vmsr p0, r2 +; CHECK-NEXT: bfi r1, r0, #0, #4 +; CHECK-NEXT: bfi r1, r0, #4, #4 +; CHECK-NEXT: bfi r1, r0, #8, #4 +; CHECK-NEXT: bfi r1, r0, #12, #4 +; CHECK-NEXT: vmsr p0, r1 ; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: bx lr entry: @@ -71,13 +68,12 @@ ; CHECK-LABEL: build_var0_v8i1: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: cmp r0, r1 -; CHECK-NEXT: mov.w r0, #0 -; CHECK-NEXT: it lo -; CHECK-NEXT: movlo r0, #1 -; CHECK-NEXT: movs r2, #0 +; CHECK-NEXT: mov.w r1, #0 +; CHECK-NEXT: csinc r0, zr, zr, hs +; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: rsbs r0, r0, #0 -; CHECK-NEXT: bfi r2, r0, #0, #2 -; CHECK-NEXT: vmsr p0, r2 +; CHECK-NEXT: bfi r1, r0, #0, #2 +; CHECK-NEXT: vmsr p0, r1 ; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: bx lr entry: @@ -91,13 +87,12 @@ ; CHECK-LABEL: build_var3_v8i1: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: cmp r0, r1 -; CHECK-NEXT: mov.w r0, #0 -; CHECK-NEXT: it lo -; CHECK-NEXT: movlo r0, #1 -; CHECK-NEXT: movs r2, #0 +; CHECK-NEXT: mov.w r1, #0 +; CHECK-NEXT: csinc r0, zr, zr, hs +; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: rsbs r0, r0, #0 -; CHECK-NEXT: bfi r2, r0, #6, #2 -; CHECK-NEXT: vmsr p0, r2 +; CHECK-NEXT: bfi r1, r0, #6, #2 +; CHECK-NEXT: vmsr p0, r1 ; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: bx lr entry: @@ -111,20 +106,19 @@ ; CHECK-LABEL: build_varN_v8i1: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: cmp r0, r1 -; CHECK-NEXT: mov.w r0, #0 -; CHECK-NEXT: it lo -; CHECK-NEXT: movlo r0, #1 -; CHECK-NEXT: movs r2, #0 +; CHECK-NEXT: mov.w r1, #0 +; CHECK-NEXT: csinc r0, zr, zr, hs +; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: rsbs r0, r0, #0 -; CHECK-NEXT: bfi r2, r0, #0, #2 -; CHECK-NEXT: bfi r2, r0, #2, #2 -; CHECK-NEXT: bfi r2, r0, #4, #2 -; CHECK-NEXT: bfi r2, r0, #6, #2 -; CHECK-NEXT: bfi r2, r0, #8, #2 -; CHECK-NEXT: bfi r2, r0, #10, #2 -; CHECK-NEXT: bfi r2, r0, #12, #2 -; CHECK-NEXT: bfi r2, r0, #14, #2 -; CHECK-NEXT: vmsr p0, r2 +; CHECK-NEXT: bfi r1, r0, #0, #2 +; CHECK-NEXT: bfi r1, r0, #2, #2 +; CHECK-NEXT: bfi r1, r0, #4, #2 +; CHECK-NEXT: bfi r1, r0, #6, #2 +; CHECK-NEXT: bfi r1, r0, #8, #2 +; CHECK-NEXT: bfi r1, r0, #10, #2 +; CHECK-NEXT: bfi r1, r0, #12, #2 +; CHECK-NEXT: bfi r1, r0, #14, #2 +; CHECK-NEXT: vmsr p0, r1 ; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: bx lr entry: @@ -140,13 +134,12 @@ ; CHECK-LABEL: build_var0_v16i1: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: cmp r0, r1 -; CHECK-NEXT: mov.w r0, #0 -; CHECK-NEXT: it lo -; CHECK-NEXT: movlo r0, #1 -; CHECK-NEXT: movs r2, #0 +; CHECK-NEXT: mov.w r1, #0 +; CHECK-NEXT: csinc r0, zr, zr, hs +; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: rsbs r0, r0, #0 -; CHECK-NEXT: bfi r2, r0, #0, #1 -; CHECK-NEXT: vmsr p0, r2 +; CHECK-NEXT: bfi r1, r0, #0, #1 +; CHECK-NEXT: vmsr p0, r1 ; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: bx lr entry: @@ -160,13 +153,12 @@ ; CHECK-LABEL: build_var3_v16i1: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: cmp r0, r1 -; CHECK-NEXT: mov.w r0, #0 -; CHECK-NEXT: it lo -; CHECK-NEXT: movlo r0, #1 -; CHECK-NEXT: movs r2, #0 +; CHECK-NEXT: mov.w r1, #0 +; CHECK-NEXT: csinc r0, zr, zr, hs +; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: rsbs r0, r0, #0 -; CHECK-NEXT: bfi r2, r0, #3, #1 -; CHECK-NEXT: vmsr p0, r2 +; CHECK-NEXT: bfi r1, r0, #3, #1 +; CHECK-NEXT: vmsr p0, r1 ; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: bx lr entry: @@ -180,28 +172,27 @@ ; CHECK-LABEL: build_varN_v16i1: ; CHECK: @ %bb.0: @ %entry ; CHECK-NEXT: cmp r0, r1 -; CHECK-NEXT: mov.w r0, #0 -; CHECK-NEXT: it lo -; CHECK-NEXT: movlo r0, #1 -; CHECK-NEXT: movs r2, #0 +; CHECK-NEXT: mov.w r1, #0 +; CHECK-NEXT: csinc r0, zr, zr, hs +; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: rsbs r0, r0, #0 -; CHECK-NEXT: bfi r2, r0, #0, #1 -; CHECK-NEXT: bfi r2, r0, #1, #1 -; CHECK-NEXT: bfi r2, r0, #2, #1 -; CHECK-NEXT: bfi r2, r0, #3, #1 -; CHECK-NEXT: bfi r2, r0, #4, #1 -; CHECK-NEXT: bfi r2, r0, #5, #1 -; CHECK-NEXT: bfi r2, r0, #6, #1 -; CHECK-NEXT: bfi r2, r0, #7, #1 -; CHECK-NEXT: bfi r2, r0, #8, #1 -; CHECK-NEXT: bfi r2, r0, #9, #1 -; CHECK-NEXT: bfi r2, r0, #10, #1 -; CHECK-NEXT: bfi r2, r0, #11, #1 -; CHECK-NEXT: bfi r2, r0, #12, #1 -; CHECK-NEXT: bfi r2, r0, #13, #1 -; CHECK-NEXT: bfi r2, r0, #14, #1 -; CHECK-NEXT: bfi r2, r0, #15, #1 -; CHECK-NEXT: vmsr p0, r2 +; CHECK-NEXT: bfi r1, r0, #0, #1 +; CHECK-NEXT: bfi r1, r0, #1, #1 +; CHECK-NEXT: bfi r1, r0, #2, #1 +; CHECK-NEXT: bfi r1, r0, #3, #1 +; CHECK-NEXT: bfi r1, r0, #4, #1 +; CHECK-NEXT: bfi r1, r0, #5, #1 +; CHECK-NEXT: bfi r1, r0, #6, #1 +; CHECK-NEXT: bfi r1, r0, #7, #1 +; CHECK-NEXT: bfi r1, r0, #8, #1 +; CHECK-NEXT: bfi r1, r0, #9, #1 +; CHECK-NEXT: bfi r1, r0, #10, #1 +; CHECK-NEXT: bfi r1, r0, #11, #1 +; CHECK-NEXT: bfi r1, r0, #12, #1 +; CHECK-NEXT: bfi r1, r0, #13, #1 +; CHECK-NEXT: bfi r1, r0, #14, #1 +; CHECK-NEXT: bfi r1, r0, #15, #1 +; CHECK-NEXT: vmsr p0, r1 ; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: bx lr entry: @@ -216,11 +207,10 @@ define arm_aapcs_vfpcc <2 x i64> @build_var0_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) { ; CHECK-LABEL: build_var0_v2i1: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: movs r2, #0 ; CHECK-NEXT: cmp r0, r1 -; CHECK-NEXT: it lo -; CHECK-NEXT: movlo r2, #1 -; CHECK-NEXT: rsbs r0, r2, #0 +; CHECK-NEXT: csinc r0, zr, zr, hs +; CHECK-NEXT: and r0, r0, #1 +; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: vmov s8, r0 ; CHECK-NEXT: vldr s10, .LCPI9_0 ; CHECK-NEXT: vmov.f32 s9, s8 @@ -243,11 +233,10 @@ define arm_aapcs_vfpcc <2 x i64> @build_var1_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) { ; CHECK-LABEL: build_var1_v2i1: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: movs r2, #0 ; CHECK-NEXT: cmp r0, r1 -; CHECK-NEXT: it lo -; CHECK-NEXT: movlo r2, #1 -; CHECK-NEXT: rsbs r0, r2, #0 +; CHECK-NEXT: csinc r0, zr, zr, hs +; CHECK-NEXT: and r0, r0, #1 +; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: vmov s10, r0 ; CHECK-NEXT: vldr s8, .LCPI10_0 ; CHECK-NEXT: vmov.f32 s9, s8 @@ -270,11 +259,10 @@ define arm_aapcs_vfpcc <2 x i64> @build_varN_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) { ; CHECK-LABEL: build_varN_v2i1: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: movs r2, #0 ; CHECK-NEXT: cmp r0, r1 -; CHECK-NEXT: it lo -; CHECK-NEXT: movlo r2, #1 -; CHECK-NEXT: rsbs r0, r2, #0 +; CHECK-NEXT: csinc r0, zr, zr, hs +; CHECK-NEXT: and r0, r0, #1 +; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: vdup.32 q2, r0 ; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vand q0, q0, q2 Index: llvm/test/CodeGen/Thumb2/mve-pred-ext.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-pred-ext.ll +++ llvm/test/CodeGen/Thumb2/mve-pred-ext.ll @@ -57,17 +57,15 @@ ; CHECK-NEXT: it lt ; CHECK-NEXT: movlt r0, #1 ; CHECK-NEXT: cmp r0, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: rsbs r3, r3, #0 ; CHECK-NEXT: sbcs.w r1, r2, r1 ; CHECK-NEXT: it lt ; CHECK-NEXT: movlt r2, #1 ; CHECK-NEXT: cmp r2, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r2, #-1 -; CHECK-NEXT: vmov.32 q0[0], r2 -; CHECK-NEXT: vmov.32 q0[1], r2 +; CHECK-NEXT: csinv r1, zr, zr, eq +; CHECK-NEXT: vmov.32 q0[0], r1 +; CHECK-NEXT: vmov.32 q0[1], r1 ; CHECK-NEXT: vmov.32 q0[2], r0 ; CHECK-NEXT: vmov.32 q0[3], r0 ; CHECK-NEXT: bx lr @@ -136,15 +134,13 @@ ; CHECK-NEXT: it lt ; CHECK-NEXT: movlt r1, #1 ; CHECK-NEXT: cmp r1, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r1, #-1 +; CHECK-NEXT: csinv r1, zr, zr, eq ; CHECK-NEXT: rsbs r3, r3, #0 ; CHECK-NEXT: sbcs.w r2, r0, r2 ; CHECK-NEXT: it lt ; CHECK-NEXT: movlt r0, #1 ; CHECK-NEXT: cmp r0, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q0[0], r0 ; CHECK-NEXT: vmov.32 q0[2], r1 ; CHECK-NEXT: vand q0, q0, q1 Index: llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll +++ llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll @@ -167,11 +167,10 @@ ; CHECK-LE-NEXT: vmov r3, s2 ; CHECK-LE-NEXT: orrs r1, r2 ; CHECK-LE-NEXT: vmov r2, s3 -; CHECK-LE-NEXT: clz r1, r1 -; CHECK-LE-NEXT: lsrs r1, r1, #5 +; CHECK-LE-NEXT: csinc r1, zr, zr, ne ; CHECK-LE-NEXT: orrs r2, r3 -; CHECK-LE-NEXT: clz r2, r2 -; CHECK-LE-NEXT: lsrs r2, r2, #5 +; CHECK-LE-NEXT: csinc r2, zr, zr, ne +; CHECK-LE-NEXT: ands r2, r2, #1 ; CHECK-LE-NEXT: it ne ; CHECK-LE-NEXT: mvnne r2, #1 ; CHECK-LE-NEXT: bfi r2, r1, #0, #1 @@ -187,11 +186,10 @@ ; CHECK-BE-NEXT: vmov r3, s5 ; CHECK-BE-NEXT: orrs r1, r2 ; CHECK-BE-NEXT: vmov r2, s4 -; CHECK-BE-NEXT: clz r1, r1 -; CHECK-BE-NEXT: lsrs r1, r1, #5 +; CHECK-BE-NEXT: csinc r1, zr, zr, ne ; CHECK-BE-NEXT: orrs r2, r3 -; CHECK-BE-NEXT: clz r2, r2 -; CHECK-BE-NEXT: lsrs r2, r2, #5 +; CHECK-BE-NEXT: csinc r2, zr, zr, ne +; CHECK-BE-NEXT: ands r2, r2, #1 ; CHECK-BE-NEXT: it ne ; CHECK-BE-NEXT: mvnne r2, #1 ; CHECK-BE-NEXT: bfi r2, r1, #0, #1 Index: llvm/test/CodeGen/Thumb2/mve-pred-not.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-pred-not.ll +++ llvm/test/CodeGen/Thumb2/mve-pred-not.ll @@ -327,18 +327,16 @@ ; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s2 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q2[0], r0 ; CHECK-NEXT: vmov.32 q2[1], r0 ; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: orrs r0, r1 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q2[2], r0 ; CHECK-NEXT: vmov.32 q2[3], r0 ; CHECK-NEXT: vbic q0, q0, q2 @@ -359,18 +357,16 @@ ; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s2 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q2[0], r0 ; CHECK-NEXT: vmov.32 q2[1], r0 ; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: orrs r0, r1 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q2[2], r0 ; CHECK-NEXT: vmov.32 q2[3], r0 ; CHECK-NEXT: vbic q0, q0, q2 Index: llvm/test/CodeGen/Thumb2/mve-pred-or.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-pred-or.ll +++ llvm/test/CodeGen/Thumb2/mve-pred-or.ll @@ -425,36 +425,32 @@ ; CHECK-NEXT: vmov r1, s4 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s6 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q2[0], r0 ; CHECK-NEXT: vmov.32 q2[1], r0 ; CHECK-NEXT: vmov r0, s7 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s0 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q2[2], r0 ; CHECK-NEXT: vmov.32 q2[3], r0 ; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s2 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[0], r0 ; CHECK-NEXT: vmov.32 q3[1], r0 ; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: orrs r0, r1 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vorr q2, q3, q2 @@ -482,10 +478,9 @@ ; CHECK-NEXT: vmov r2, s6 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s7 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[0], r0 ; CHECK-NEXT: vmov.32 q3[1], r0 ; CHECK-NEXT: vmov r0, s11 @@ -494,27 +489,24 @@ ; CHECK-NEXT: eors r1, r2 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s0 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s2 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q2[0], r0 ; CHECK-NEXT: vmov.32 q2[1], r0 ; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: orrs r0, r1 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q2[2], r0 ; CHECK-NEXT: vmov.32 q2[3], r0 ; CHECK-NEXT: vorr q2, q2, q3 Index: llvm/test/CodeGen/Thumb2/mve-pred-xor.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-pred-xor.ll +++ llvm/test/CodeGen/Thumb2/mve-pred-xor.ll @@ -461,36 +461,32 @@ ; CHECK-NEXT: vmov r1, s4 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s6 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q2[0], r0 ; CHECK-NEXT: vmov.32 q2[1], r0 ; CHECK-NEXT: vmov r0, s7 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s0 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q2[2], r0 ; CHECK-NEXT: vmov.32 q2[3], r0 ; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s2 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[0], r0 ; CHECK-NEXT: vmov.32 q3[1], r0 ; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: orrs r0, r1 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: veor q2, q3, q2 @@ -518,10 +514,9 @@ ; CHECK-NEXT: vmov r2, s6 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s7 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[0], r0 ; CHECK-NEXT: vmov.32 q3[1], r0 ; CHECK-NEXT: vmov r0, s11 @@ -530,27 +525,24 @@ ; CHECK-NEXT: eors r1, r2 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s0 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s2 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q2[0], r0 ; CHECK-NEXT: vmov.32 q2[1], r0 ; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: orrs r0, r1 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q2[2], r0 ; CHECK-NEXT: vmov.32 q2[3], r0 ; CHECK-NEXT: veor q2, q2, q3 Index: llvm/test/CodeGen/Thumb2/mve-vcmp.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-vcmp.ll +++ llvm/test/CodeGen/Thumb2/mve-vcmp.ll @@ -378,10 +378,9 @@ ; CHECK-NEXT: vmov r2, s2 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s3 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q4[0], r0 ; CHECK-NEXT: vmov.32 q4[1], r0 ; CHECK-NEXT: vmov r0, s7 @@ -389,10 +388,9 @@ ; CHECK-NEXT: vmov r1, s6 ; CHECK-NEXT: eors r1, r2 ; CHECK-NEXT: orrs r0, r1 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q4[2], r0 ; CHECK-NEXT: vmov.32 q4[3], r0 ; CHECK-NEXT: vbic q0, q3, q4 @@ -420,10 +418,9 @@ ; CHECK-NEXT: vmov r2, s2 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s3 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q4[0], r0 ; CHECK-NEXT: vmov.32 q4[1], r0 ; CHECK-NEXT: vmov r0, s7 @@ -431,10 +428,9 @@ ; CHECK-NEXT: vmov r1, s6 ; CHECK-NEXT: eors r1, r2 ; CHECK-NEXT: orrs r0, r1 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q4[2], r0 ; CHECK-NEXT: vmov.32 q4[3], r0 ; CHECK-NEXT: vbic q0, q3, q4 @@ -459,79 +455,67 @@ ; CHECK-NEXT: movs r3, #0 ; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r2, s8 -; CHECK-NEXT: vmov lr, s10 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s2 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[0], r0 ; CHECK-NEXT: vmov.32 q3[1], r0 ; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: orrs r0, r1 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vbic q0, q2, q3 -; CHECK-NEXT: vmov r0, s0 -; CHECK-NEXT: subs r1, r0, r2 -; CHECK-NEXT: asr.w r12, r0, #31 +; CHECK-NEXT: vmov lr, s0 +; CHECK-NEXT: subs.w r1, lr, r2 +; CHECK-NEXT: asr.w r12, lr, #31 ; CHECK-NEXT: sbcs.w r1, r12, r2, asr #31 ; CHECK-NEXT: mov.w r1, #0 +; CHECK-NEXT: vmov r2, s10 ; CHECK-NEXT: it lt ; CHECK-NEXT: movlt r1, #1 ; CHECK-NEXT: cmp r1, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r1, #-1 +; CHECK-NEXT: csinv r1, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[0], r1 ; CHECK-NEXT: vmov.32 q3[1], r1 ; CHECK-NEXT: vmov r1, s2 -; CHECK-NEXT: subs.w r2, r1, lr +; CHECK-NEXT: subs r0, r1, r2 ; CHECK-NEXT: asr.w r12, r1, #31 -; CHECK-NEXT: sbcs.w r2, r12, lr, asr #31 +; CHECK-NEXT: sbcs.w r0, r12, r2, asr #31 ; CHECK-NEXT: it lt ; CHECK-NEXT: movlt r3, #1 ; CHECK-NEXT: cmp r3, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r3, #-1 -; CHECK-NEXT: cmp r0, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne r0, #1 -; CHECK-NEXT: cmp r0, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinv r0, zr, zr, eq +; CHECK-NEXT: cmp.w lr, #0 +; CHECK-NEXT: vmov.32 q3[2], r0 +; CHECK-NEXT: vmov.32 q3[3], r0 +; CHECK-NEXT: csinc r0, zr, zr, eq +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq +; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: vmov.32 q4[0], r0 ; CHECK-NEXT: vmov.32 q4[1], r0 +; CHECK-NEXT: csinc r0, zr, zr, eq +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq +; CHECK-NEXT: vmov.32 q4[2], r0 +; CHECK-NEXT: vmov.32 q4[3], r0 ; CHECK-NEXT: vmov r0, s4 -; CHECK-NEXT: cmp r1, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne r1, #1 -; CHECK-NEXT: cmp r1, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r1, #-1 -; CHECK-NEXT: vmov.32 q4[2], r1 -; CHECK-NEXT: vmov.32 q3[2], r3 -; CHECK-NEXT: vmov.32 q4[3], r1 -; CHECK-NEXT: vmov.32 q3[3], r3 ; CHECK-NEXT: cmp r0, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne r0, #1 -; CHECK-NEXT: cmp r0, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, eq +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q5[0], r0 ; CHECK-NEXT: vmov.32 q5[1], r0 ; CHECK-NEXT: vmov r0, s6 ; CHECK-NEXT: cmp r0, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne r0, #1 -; CHECK-NEXT: cmp r0, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, eq +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q5[2], r0 ; CHECK-NEXT: vmov.32 q5[3], r0 ; CHECK-NEXT: vand q1, q5, q4 Index: llvm/test/CodeGen/Thumb2/mve-vcmpf.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-vcmpf.ll +++ llvm/test/CodeGen/Thumb2/mve-vcmpf.ll @@ -5,45 +5,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_oeq_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmp.f32 s1, s5 +; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmp.f32 s0, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmp.f32 s1, s5 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmp.f32 s3, s7 +; CHECK-MVE-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmp.f32 s2, s6 +; CHECK-MVE-NEXT: vcmp.f32 s3, s7 ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -61,30 +57,28 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_one_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmp.f32 s1, s5 +; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr -; CHECK-MVE-NEXT: vcmp.f32 s1, s5 +; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmp.f32 s0, s4 +; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r2, #1 -; CHECK-MVE-NEXT: vcmp.f32 s3, s7 +; CHECK-MVE-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r3, #1 @@ -92,24 +86,22 @@ ; CHECK-MVE-NEXT: movgt r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: mov.w r0, #0 -; CHECK-MVE-NEXT: vcmp.f32 s2, s6 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: vcmp.f32 s3, s7 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -130,45 +122,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ogt_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_ogt_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 +; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 +; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 +; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -186,45 +174,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_oge_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_oge_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 +; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 +; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 ; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: movge r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 +; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 ; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: movge r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -242,45 +226,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_olt_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_olt_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 +; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 +; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 +; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -298,45 +278,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ole_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_ole_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 +; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 +; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 ; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: movls r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 +; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 ; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: movls r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -354,30 +330,28 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_ueq_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmp.f32 s1, s5 +; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr -; CHECK-MVE-NEXT: vcmp.f32 s1, s5 +; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmp.f32 s0, s4 +; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r2, #1 -; CHECK-MVE-NEXT: vcmp.f32 s3, s7 +; CHECK-MVE-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r3, #1 @@ -385,24 +359,22 @@ ; CHECK-MVE-NEXT: movvs r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: mov.w r0, #0 -; CHECK-MVE-NEXT: vcmp.f32 s2, s6 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: vcmp.f32 s3, s7 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -422,45 +394,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_une_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmp.f32 s1, s5 +; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmp.f32 s0, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmp.f32 s1, s5 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmp.f32 s3, s7 +; CHECK-MVE-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: movne r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmp.f32 s2, s6 +; CHECK-MVE-NEXT: vcmp.f32 s3, s7 ; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: movne r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -478,45 +446,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_ugt_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 +; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 +; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 ; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: movhi r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 +; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 ; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: movhi r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -535,45 +499,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_uge_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 +; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 +; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 ; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: movpl r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 +; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 ; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: movpl r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -592,45 +552,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_ult_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 +; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 +; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 ; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: movlt r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 +; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 ; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: movlt r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -649,45 +605,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_ule_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 +; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 +; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 ; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: movle r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 +; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 ; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: movle r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -706,45 +658,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_ord_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 +; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 +; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 ; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: movvc r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 +; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 ; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: movvc r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -765,45 +713,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_uno_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 +; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 +; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 +; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -827,72 +771,69 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} -; CHECK-MVE-NEXT: vmov.u16 r1, q1[1] -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r1, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vmov s16, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] ; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q3[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vmov.u16 r2, q3[0] +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 -; CHECK-MVE-NEXT: vmov.u16 r3, q0[0] +; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov s16, r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: movs r2, #0 -; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] ; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vmov s16, r3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q3[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q3[1] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r2, s16 -; CHECK-MVE-NEXT: vmov.16 q4[0], r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[2] -; CHECK-MVE-NEXT: vmov.16 q4[1], r1 +; CHECK-MVE-NEXT: vmov.16 q4[0], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[2] +; CHECK-MVE-NEXT: vmov.16 q4[1], r2 ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[2] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 -; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] ; CHECK-MVE-NEXT: vcmp.f16 s22, s20 -; CHECK-MVE-NEXT: vmov s20, r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s20, r2 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q3[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[3] +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] +; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[3] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[3] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -901,18 +842,17 @@ ; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[4] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] ; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[4] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[4] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -921,18 +861,17 @@ ; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[5] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] ; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[5] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[5] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -941,18 +880,17 @@ ; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[6] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] ; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[6] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[6] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -961,29 +899,27 @@ ; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[7] +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s2, r2 ; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[7] +; CHECK-MVE-NEXT: vmov s4, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[7] ; CHECK-MVE-NEXT: vmov s0, r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: vcmp.f16 s2, s0 +; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vmov s0, r1 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r1, q3[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0 @@ -1021,11 +957,10 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q3[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov.u16 r3, q0[0] ; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] @@ -1042,11 +977,10 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r3, q3[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 ; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov r2, s16 @@ -1066,11 +1000,10 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q3[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vmov.u16 r2, q0[3] ; CHECK-MVE-NEXT: vmov r1, s20 @@ -1088,11 +1021,10 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q3[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vmov.u16 r2, q0[4] ; CHECK-MVE-NEXT: vmov r1, s20 @@ -1110,11 +1042,10 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q3[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vmov.u16 r2, q0[5] ; CHECK-MVE-NEXT: vmov r1, s20 @@ -1132,11 +1063,10 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q3[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vmov.u16 r2, q0[6] ; CHECK-MVE-NEXT: vmov r1, s20 @@ -1154,11 +1084,10 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q3[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vmov.u16 r2, q0[7] ; CHECK-MVE-NEXT: vmov r1, s20 @@ -1175,11 +1104,10 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r1, q3[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0 @@ -1206,72 +1134,69 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} -; CHECK-MVE-NEXT: vmov.u16 r1, q1[1] -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r1, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vmov s16, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q3[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vmov.u16 r2, q3[0] +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 -; CHECK-MVE-NEXT: vmov.u16 r3, q0[0] +; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov s16, r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: movs r2, #0 -; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vmov s16, r3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q3[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q3[1] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r2, s16 -; CHECK-MVE-NEXT: vmov.16 q4[0], r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[2] -; CHECK-MVE-NEXT: vmov.16 q4[1], r1 +; CHECK-MVE-NEXT: vmov.16 q4[0], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[2] +; CHECK-MVE-NEXT: vmov.16 q4[1], r2 ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[2] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 -; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 -; CHECK-MVE-NEXT: vmov s20, r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s20, r2 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q3[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[3] +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] +; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[3] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[3] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -1280,18 +1205,17 @@ ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[4] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] ; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[4] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[4] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -1300,18 +1224,17 @@ ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[5] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] ; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[5] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[5] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -1320,18 +1243,17 @@ ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[6] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] ; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[6] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[6] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -1340,29 +1262,27 @@ ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[7] +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s2, r2 ; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[7] +; CHECK-MVE-NEXT: vmov s4, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[7] ; CHECK-MVE-NEXT: vmov s0, r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: vcmpe.f16 s2, s0 +; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vmov s0, r1 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r1, q3[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0 @@ -1386,72 +1306,69 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} -; CHECK-MVE-NEXT: vmov.u16 r1, q1[1] -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r1, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vmov s16, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q3[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vmov.u16 r2, q3[0] +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 -; CHECK-MVE-NEXT: vmov.u16 r3, q0[0] +; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov s16, r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: movs r2, #0 -; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vmov s16, r3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: movge r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q3[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q3[1] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r2, s16 -; CHECK-MVE-NEXT: vmov.16 q4[0], r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[2] -; CHECK-MVE-NEXT: vmov.16 q4[1], r1 +; CHECK-MVE-NEXT: vmov.16 q4[0], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[2] +; CHECK-MVE-NEXT: vmov.16 q4[1], r2 ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[2] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 -; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 -; CHECK-MVE-NEXT: vmov s20, r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s20, r2 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q3[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[3] +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] +; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[3] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[3] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -1460,18 +1377,17 @@ ; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[4] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] ; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[4] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[4] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -1480,18 +1396,17 @@ ; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[5] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] ; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[5] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[5] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -1500,18 +1415,17 @@ ; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[6] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] ; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[6] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[6] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -1520,29 +1434,27 @@ ; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[7] +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s2, r2 ; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[7] +; CHECK-MVE-NEXT: vmov s4, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[7] ; CHECK-MVE-NEXT: vmov s0, r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: vcmpe.f16 s2, s0 +; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vmov s0, r1 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r1, q3[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0 @@ -1566,72 +1478,69 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} -; CHECK-MVE-NEXT: vmov.u16 r1, q1[1] -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r1, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vmov s16, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q3[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vmov.u16 r2, q3[0] +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 -; CHECK-MVE-NEXT: vmov.u16 r3, q0[0] +; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov s16, r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: movs r2, #0 -; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vmov s16, r3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q3[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q3[1] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r2, s16 -; CHECK-MVE-NEXT: vmov.16 q4[0], r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[2] -; CHECK-MVE-NEXT: vmov.16 q4[1], r1 +; CHECK-MVE-NEXT: vmov.16 q4[0], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[2] +; CHECK-MVE-NEXT: vmov.16 q4[1], r2 ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[2] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 -; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 -; CHECK-MVE-NEXT: vmov s20, r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s20, r2 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q3[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[3] +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] +; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[3] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[3] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -1640,18 +1549,17 @@ ; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[4] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] ; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[4] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[4] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -1660,18 +1568,17 @@ ; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[5] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] ; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[5] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[5] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -1680,18 +1587,17 @@ ; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[6] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] ; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[6] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[6] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -1700,29 +1606,27 @@ ; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[7] +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s2, r2 ; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[7] +; CHECK-MVE-NEXT: vmov s4, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[7] ; CHECK-MVE-NEXT: vmov s0, r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: vcmpe.f16 s2, s0 +; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vmov s0, r1 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r1, q3[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0 @@ -1746,72 +1650,69 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} -; CHECK-MVE-NEXT: vmov.u16 r1, q1[1] -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r1, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vmov s16, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ls -; CHECK-MVE-NEXT: movls r1, #1 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q3[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 -; CHECK-MVE-NEXT: vmov s18, r2 +; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q3[0] +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq +; CHECK-MVE-NEXT: vmov s18, r2 +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 -; CHECK-MVE-NEXT: vmov.u16 r3, q0[0] +; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov s16, r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: movs r2, #0 -; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vmov s16, r3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: movls r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q3[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q3[1] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r2, s16 -; CHECK-MVE-NEXT: vmov.16 q4[0], r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[2] -; CHECK-MVE-NEXT: vmov.16 q4[1], r1 +; CHECK-MVE-NEXT: vmov.16 q4[0], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[2] +; CHECK-MVE-NEXT: vmov.16 q4[1], r2 ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[2] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 -; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 -; CHECK-MVE-NEXT: vmov s20, r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s20, r2 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q3[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[3] +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] +; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[3] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[3] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -1820,18 +1721,17 @@ ; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[4] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] ; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[4] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[4] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -1840,18 +1740,17 @@ ; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[5] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] ; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[5] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[5] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -1860,18 +1759,17 @@ ; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[6] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] ; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[6] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[6] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -1880,29 +1778,27 @@ ; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[7] +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s2, r2 ; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[7] +; CHECK-MVE-NEXT: vmov s4, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[7] ; CHECK-MVE-NEXT: vmov s0, r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: vcmpe.f16 s2, s0 +; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vmov s0, r1 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r1, q3[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0 @@ -1940,11 +1836,10 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q3[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov.u16 r3, q0[0] ; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] @@ -1961,11 +1856,10 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r3, q3[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 ; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov r2, s16 @@ -1985,11 +1879,10 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q3[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vmov.u16 r2, q0[3] ; CHECK-MVE-NEXT: vmov r1, s20 @@ -2007,11 +1900,10 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q3[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vmov.u16 r2, q0[4] ; CHECK-MVE-NEXT: vmov r1, s20 @@ -2029,11 +1921,10 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q3[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vmov.u16 r2, q0[5] ; CHECK-MVE-NEXT: vmov r1, s20 @@ -2051,11 +1942,10 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q3[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vmov.u16 r2, q0[6] ; CHECK-MVE-NEXT: vmov r1, s20 @@ -2073,11 +1963,10 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q3[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vmov.u16 r2, q0[7] ; CHECK-MVE-NEXT: vmov r1, s20 @@ -2094,11 +1983,10 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r1, q3[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0 @@ -2124,72 +2012,69 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} -; CHECK-MVE-NEXT: vmov.u16 r1, q1[1] -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r1, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vmov s16, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] ; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q3[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vmov.u16 r2, q3[0] +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 -; CHECK-MVE-NEXT: vmov.u16 r3, q0[0] +; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov s16, r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: movs r2, #0 -; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] ; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vmov s16, r3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: movne r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q3[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q3[1] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r2, s16 -; CHECK-MVE-NEXT: vmov.16 q4[0], r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[2] -; CHECK-MVE-NEXT: vmov.16 q4[1], r1 +; CHECK-MVE-NEXT: vmov.16 q4[0], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[2] +; CHECK-MVE-NEXT: vmov.16 q4[1], r2 ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[2] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 -; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] ; CHECK-MVE-NEXT: vcmp.f16 s22, s20 -; CHECK-MVE-NEXT: vmov s20, r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s20, r2 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q3[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[3] +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] +; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[3] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[3] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -2198,18 +2083,17 @@ ; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[4] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] ; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[4] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[4] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -2218,18 +2102,17 @@ ; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[5] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] ; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[5] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[5] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -2238,18 +2121,17 @@ ; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[6] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] ; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[6] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[6] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -2258,29 +2140,27 @@ ; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[7] +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s2, r2 ; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[7] +; CHECK-MVE-NEXT: vmov s4, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[7] ; CHECK-MVE-NEXT: vmov s0, r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: vcmp.f16 s2, s0 +; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vmov s0, r1 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r1, q3[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0 @@ -2304,72 +2184,69 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} -; CHECK-MVE-NEXT: vmov.u16 r1, q1[1] -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r1, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vmov s16, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q3[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vmov.u16 r2, q3[0] +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 -; CHECK-MVE-NEXT: vmov.u16 r3, q0[0] +; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov s16, r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: movs r2, #0 -; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vmov s16, r3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: movhi r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q3[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q3[1] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r2, s16 -; CHECK-MVE-NEXT: vmov.16 q4[0], r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[2] -; CHECK-MVE-NEXT: vmov.16 q4[1], r1 +; CHECK-MVE-NEXT: vmov.16 q4[0], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[2] +; CHECK-MVE-NEXT: vmov.16 q4[1], r2 ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[2] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 -; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 -; CHECK-MVE-NEXT: vmov s20, r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s20, r2 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q3[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[3] +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] +; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[3] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[3] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -2378,18 +2255,17 @@ ; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[4] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] ; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[4] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[4] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -2398,18 +2274,17 @@ ; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[5] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] ; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[5] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[5] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -2418,18 +2293,17 @@ ; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[6] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] ; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[6] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[6] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -2438,29 +2312,27 @@ ; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[7] +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s2, r2 ; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[7] +; CHECK-MVE-NEXT: vmov s4, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[7] ; CHECK-MVE-NEXT: vmov s0, r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: vcmpe.f16 s2, s0 +; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vmov s0, r1 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r1, q3[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0 @@ -2485,72 +2357,69 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} -; CHECK-MVE-NEXT: vmov.u16 r1, q1[1] -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r1, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vmov s16, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q3[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vmov.u16 r2, q3[0] +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 -; CHECK-MVE-NEXT: vmov.u16 r3, q0[0] +; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov s16, r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: movs r2, #0 -; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vmov s16, r3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: movpl r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q3[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q3[1] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r2, s16 -; CHECK-MVE-NEXT: vmov.16 q4[0], r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[2] -; CHECK-MVE-NEXT: vmov.16 q4[1], r1 +; CHECK-MVE-NEXT: vmov.16 q4[0], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[2] +; CHECK-MVE-NEXT: vmov.16 q4[1], r2 ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[2] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 -; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 -; CHECK-MVE-NEXT: vmov s20, r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s20, r2 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q3[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[3] +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] +; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[3] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[3] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -2559,18 +2428,17 @@ ; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[4] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] ; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[4] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[4] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -2579,18 +2447,17 @@ ; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[5] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] ; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[5] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[5] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -2598,19 +2465,18 @@ ; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q3[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 -; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[6] -; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 +; CHECK-MVE-NEXT: vmov.u16 r2, q3[5] +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: vmov r1, s20 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] +; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 +; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[6] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[6] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -2619,29 +2485,27 @@ ; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[7] +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s2, r2 ; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[7] +; CHECK-MVE-NEXT: vmov s4, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[7] ; CHECK-MVE-NEXT: vmov s0, r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: vcmpe.f16 s2, s0 +; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vmov s0, r1 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r1, q3[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0 @@ -2666,72 +2530,69 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} -; CHECK-MVE-NEXT: vmov.u16 r1, q1[1] -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r1, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vmov s16, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q3[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vmov.u16 r2, q3[0] +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 -; CHECK-MVE-NEXT: vmov.u16 r3, q0[0] +; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov s16, r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: movs r2, #0 -; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vmov s16, r3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: movlt r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q3[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q3[1] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r2, s16 -; CHECK-MVE-NEXT: vmov.16 q4[0], r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[2] -; CHECK-MVE-NEXT: vmov.16 q4[1], r1 +; CHECK-MVE-NEXT: vmov.16 q4[0], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[2] +; CHECK-MVE-NEXT: vmov.16 q4[1], r2 ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[2] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 -; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 -; CHECK-MVE-NEXT: vmov s20, r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s20, r2 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q3[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[3] +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] +; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[3] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[3] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -2740,18 +2601,17 @@ ; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[4] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] ; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[4] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[4] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -2760,18 +2620,17 @@ ; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[5] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] ; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[5] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[5] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -2780,18 +2639,17 @@ ; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[6] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] ; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[6] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[6] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -2800,29 +2658,27 @@ ; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[7] +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s2, r2 ; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[7] +; CHECK-MVE-NEXT: vmov s4, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[7] ; CHECK-MVE-NEXT: vmov s0, r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: vcmpe.f16 s2, s0 +; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vmov s0, r1 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r1, q3[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0 @@ -2847,72 +2703,69 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} -; CHECK-MVE-NEXT: vmov.u16 r1, q1[1] -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r1, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vmov s16, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q3[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vmov.u16 r2, q3[0] +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 -; CHECK-MVE-NEXT: vmov.u16 r3, q0[0] +; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov s16, r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: movs r2, #0 -; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vmov s16, r3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: movle r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q3[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q3[1] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r2, s16 -; CHECK-MVE-NEXT: vmov.16 q4[0], r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[2] -; CHECK-MVE-NEXT: vmov.16 q4[1], r1 +; CHECK-MVE-NEXT: vmov.16 q4[0], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[2] +; CHECK-MVE-NEXT: vmov.16 q4[1], r2 ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[2] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 -; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 -; CHECK-MVE-NEXT: vmov s20, r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s20, r2 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q3[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[3] +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] +; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[3] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[3] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -2921,18 +2774,17 @@ ; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[4] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] ; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[4] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[4] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -2941,18 +2793,17 @@ ; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[5] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] ; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[5] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[5] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -2961,18 +2812,17 @@ ; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[6] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] ; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[6] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[6] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -2981,29 +2831,27 @@ ; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[7] +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s2, r2 ; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[7] +; CHECK-MVE-NEXT: vmov s4, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[7] ; CHECK-MVE-NEXT: vmov s0, r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: vcmpe.f16 s2, s0 +; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vmov s0, r1 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r1, q3[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0 @@ -3028,72 +2876,69 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} -; CHECK-MVE-NEXT: vmov.u16 r1, q1[1] -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r1, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vmov s16, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q3[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vmov.u16 r2, q3[0] +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 -; CHECK-MVE-NEXT: vmov.u16 r3, q0[0] +; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov s16, r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: movs r2, #0 -; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vmov s16, r3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: movvc r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q3[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q3[1] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r2, s16 -; CHECK-MVE-NEXT: vmov.16 q4[0], r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[2] -; CHECK-MVE-NEXT: vmov.16 q4[1], r1 +; CHECK-MVE-NEXT: vmov.16 q4[0], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[2] +; CHECK-MVE-NEXT: vmov.16 q4[1], r2 ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[2] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 -; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 -; CHECK-MVE-NEXT: vmov s20, r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s20, r2 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q3[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[3] +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] +; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[3] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[3] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -3102,18 +2947,17 @@ ; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[4] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] ; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[4] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[4] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -3122,18 +2966,17 @@ ; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[5] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] ; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[5] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[5] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -3142,18 +2985,17 @@ ; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[6] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] ; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[6] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[6] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -3162,29 +3004,27 @@ ; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[7] +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s2, r2 ; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[7] +; CHECK-MVE-NEXT: vmov s4, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[7] ; CHECK-MVE-NEXT: vmov s0, r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: vcmpe.f16 s2, s0 +; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vmov s0, r1 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r1, q3[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0 @@ -3211,72 +3051,69 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} -; CHECK-MVE-NEXT: vmov.u16 r1, q1[1] -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r1, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vmov s16, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q3[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vmov.u16 r2, q3[0] +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 -; CHECK-MVE-NEXT: vmov.u16 r3, q0[0] +; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov s16, r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: movs r2, #0 -; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vmov s16, r3 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q3[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q3[1] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r2, s16 -; CHECK-MVE-NEXT: vmov.16 q4[0], r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[2] -; CHECK-MVE-NEXT: vmov.16 q4[1], r1 +; CHECK-MVE-NEXT: vmov.16 q4[0], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[2] +; CHECK-MVE-NEXT: vmov.16 q4[1], r2 ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[2] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 -; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 -; CHECK-MVE-NEXT: vmov s20, r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s20, r2 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q3[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[3] +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] +; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[3] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[3] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -3285,18 +3122,17 @@ ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[4] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] ; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[4] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[4] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -3305,18 +3141,17 @@ ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[5] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] ; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[5] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[5] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -3325,18 +3160,17 @@ ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[6] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s22, r2 ; CHECK-MVE-NEXT: vmov r1, s20 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] ; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[6] ; CHECK-MVE-NEXT: vmov s20, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[6] +; CHECK-MVE-NEXT: vmov s22, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vmov s20, r2 @@ -3345,29 +3179,27 @@ ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q3[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s22, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[7] +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 -; CHECK-MVE-NEXT: vmov s2, r2 ; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q1[7] +; CHECK-MVE-NEXT: vmov s4, r1 +; CHECK-MVE-NEXT: vmov.u16 r1, q0[7] ; CHECK-MVE-NEXT: vmov s0, r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: vcmpe.f16 s2, s0 +; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vmov s0, r1 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r1, q3[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0 Index: llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll +++ llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll @@ -5,45 +5,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_oeq_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmp.f32 s1, s4 +; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmp.f32 s0, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmp.f32 s1, s4 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmp.f32 s3, s4 +; CHECK-MVE-NEXT: vcmp.f32 s2, s4 ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmp.f32 s2, s4 +; CHECK-MVE-NEXT: vcmp.f32 s3, s4 ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -64,30 +60,28 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_one_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmp.f32 s1, s4 +; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr -; CHECK-MVE-NEXT: vcmp.f32 s1, s4 +; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmp.f32 s0, s4 +; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r2, #1 -; CHECK-MVE-NEXT: vcmp.f32 s3, s4 +; CHECK-MVE-NEXT: vcmp.f32 s2, s4 ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r3, #1 @@ -95,24 +89,22 @@ ; CHECK-MVE-NEXT: movgt r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: mov.w r0, #0 -; CHECK-MVE-NEXT: vcmp.f32 s2, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: vcmp.f32 s3, s4 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -137,45 +129,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ogt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_ogt_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -196,45 +184,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_oge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_oge_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 ; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: movge r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 ; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: movge r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -255,45 +239,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_olt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_olt_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -315,45 +295,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ole_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_ole_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 ; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: movls r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 ; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: movls r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -375,30 +351,28 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_ueq_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmp.f32 s1, s4 +; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr -; CHECK-MVE-NEXT: vcmp.f32 s1, s4 +; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmp.f32 s0, s4 +; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r2, #1 -; CHECK-MVE-NEXT: vcmp.f32 s3, s4 +; CHECK-MVE-NEXT: vcmp.f32 s2, s4 ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r3, #1 @@ -406,24 +380,22 @@ ; CHECK-MVE-NEXT: movvs r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: mov.w r0, #0 -; CHECK-MVE-NEXT: vcmp.f32 s2, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: vcmp.f32 s3, s4 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -447,45 +419,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_une_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmp.f32 s1, s4 +; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmp.f32 s0, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmp.f32 s1, s4 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmp.f32 s3, s4 +; CHECK-MVE-NEXT: vcmp.f32 s2, s4 ; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: movne r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmp.f32 s2, s4 +; CHECK-MVE-NEXT: vcmp.f32 s3, s4 ; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: movne r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -506,45 +474,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_ugt_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 ; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: movhi r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 ; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: movhi r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -567,45 +531,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_uge_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 ; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: movpl r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 ; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: movpl r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -628,45 +588,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_ult_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 ; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: movlt r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 ; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: movlt r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -688,45 +644,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_ule_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 ; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: movle r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 ; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: movle r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -748,45 +700,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_ord_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 ; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: movvc r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 ; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: movvc r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -811,45 +759,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_uno_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 +; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: bx lr ; @@ -877,26 +821,25 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9, d10} ; CHECK-MVE-NEXT: vpush {d8, d9, d10} -; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] ; CHECK-MVE-NEXT: vldr.16 s16, [r0] ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov s12, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vmov r0, s12 -; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] +; CHECK-MVE-NEXT: vmov.u16 r3, q1[0] ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: movs r2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, s16 @@ -905,33 +848,31 @@ ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 -; CHECK-MVE-NEXT: vmov.16 q3[0], r0 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[2] -; CHECK-MVE-NEXT: vmov.16 q3[1], r2 ; CHECK-MVE-NEXT: vmov s18, r0 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[3] @@ -944,10 +885,9 @@ ; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -962,10 +902,9 @@ ; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -980,10 +919,9 @@ ; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -998,10 +936,9 @@ ; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0 @@ -1013,12 +950,11 @@ ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r1, #1 -; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r0, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 -; CHECK-MVE-NEXT: vmov s2, r0 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s2, r0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -1059,12 +995,11 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] @@ -1080,11 +1015,10 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov.16 q3[0], r0 @@ -1100,12 +1034,11 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -1121,11 +1054,10 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vmov r0, s18 @@ -1141,11 +1073,10 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vmov r0, s18 @@ -1161,11 +1092,10 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vmov r0, s18 @@ -1181,11 +1111,10 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0 @@ -1199,12 +1128,11 @@ ; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r1, #1 -; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r0, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 -; CHECK-MVE-NEXT: vmov s2, r0 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s2, r0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -1237,26 +1165,25 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9, d10} ; CHECK-MVE-NEXT: vpush {d8, d9, d10} -; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] ; CHECK-MVE-NEXT: vldr.16 s16, [r0] ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov s12, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vmov r0, s12 -; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] +; CHECK-MVE-NEXT: vmov.u16 r3, q1[0] ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: movs r2, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 @@ -1265,33 +1192,31 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 -; CHECK-MVE-NEXT: vmov.16 q3[0], r0 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[2] -; CHECK-MVE-NEXT: vmov.16 q3[1], r2 ; CHECK-MVE-NEXT: vmov s18, r0 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[3] @@ -1304,10 +1229,9 @@ ; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -1322,10 +1246,9 @@ ; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -1340,10 +1263,9 @@ ; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -1358,10 +1280,9 @@ ; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0 @@ -1373,12 +1294,11 @@ ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r1, #1 -; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r0, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 -; CHECK-MVE-NEXT: vmov s2, r0 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s2, r0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -1407,26 +1327,25 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9, d10} ; CHECK-MVE-NEXT: vpush {d8, d9, d10} -; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] ; CHECK-MVE-NEXT: vldr.16 s16, [r0] ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov s12, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vmov r0, s12 -; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] +; CHECK-MVE-NEXT: vmov.u16 r3, q1[0] ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: movs r2, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 @@ -1435,33 +1354,31 @@ ; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: movge r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 -; CHECK-MVE-NEXT: vmov.16 q3[0], r0 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[2] -; CHECK-MVE-NEXT: vmov.16 q3[1], r2 ; CHECK-MVE-NEXT: vmov s18, r0 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[3] @@ -1474,10 +1391,9 @@ ; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -1492,10 +1408,9 @@ ; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -1510,10 +1425,9 @@ ; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -1528,10 +1442,9 @@ ; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0 @@ -1543,12 +1456,11 @@ ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: movge r1, #1 -; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r0, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 -; CHECK-MVE-NEXT: vmov s2, r0 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s2, r0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -1577,26 +1489,25 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9, d10} ; CHECK-MVE-NEXT: vpush {d8, d9, d10} -; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] ; CHECK-MVE-NEXT: vldr.16 s16, [r0] ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov s12, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vmov r0, s12 -; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] +; CHECK-MVE-NEXT: vmov.u16 r3, q1[0] ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: movs r2, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 @@ -1605,33 +1516,31 @@ ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 -; CHECK-MVE-NEXT: vmov.16 q3[0], r0 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[2] -; CHECK-MVE-NEXT: vmov.16 q3[1], r2 ; CHECK-MVE-NEXT: vmov s18, r0 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[3] @@ -1644,10 +1553,9 @@ ; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -1662,10 +1570,9 @@ ; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -1680,10 +1587,9 @@ ; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -1698,10 +1604,9 @@ ; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0 @@ -1713,12 +1618,11 @@ ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r1, #1 -; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r0, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 -; CHECK-MVE-NEXT: vmov s2, r0 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s2, r0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -1748,26 +1652,25 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9, d10} ; CHECK-MVE-NEXT: vpush {d8, d9, d10} -; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] ; CHECK-MVE-NEXT: vldr.16 s16, [r0] ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov s12, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vmov r0, s12 -; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] +; CHECK-MVE-NEXT: vmov.u16 r3, q1[0] ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: movs r2, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 @@ -1776,33 +1679,31 @@ ; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: movls r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 -; CHECK-MVE-NEXT: vmov.16 q3[0], r0 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[2] -; CHECK-MVE-NEXT: vmov.16 q3[1], r2 ; CHECK-MVE-NEXT: vmov s18, r0 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[3] @@ -1815,10 +1716,9 @@ ; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -1833,10 +1733,9 @@ ; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -1851,10 +1750,9 @@ ; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -1869,10 +1767,9 @@ ; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0 @@ -1884,12 +1781,11 @@ ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: movls r1, #1 -; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r0, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 -; CHECK-MVE-NEXT: vmov s2, r0 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s2, r0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -1931,12 +1827,11 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] @@ -1952,11 +1847,10 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov.16 q3[0], r0 @@ -1972,12 +1866,11 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -1993,11 +1886,10 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vmov r0, s18 @@ -2013,11 +1905,10 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vmov r0, s18 @@ -2033,11 +1924,10 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vmov r0, s18 @@ -2053,11 +1943,10 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0 @@ -2071,12 +1960,11 @@ ; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r1, #1 -; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r0, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 -; CHECK-MVE-NEXT: vmov s2, r0 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s2, r0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -2108,26 +1996,25 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9, d10} ; CHECK-MVE-NEXT: vpush {d8, d9, d10} -; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] ; CHECK-MVE-NEXT: vldr.16 s16, [r0] ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov s12, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vmov r0, s12 -; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] +; CHECK-MVE-NEXT: vmov.u16 r3, q1[0] ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: movs r2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, s16 @@ -2136,33 +2023,31 @@ ; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: movne r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 -; CHECK-MVE-NEXT: vmov.16 q3[0], r0 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[2] -; CHECK-MVE-NEXT: vmov.16 q3[1], r2 ; CHECK-MVE-NEXT: vmov s18, r0 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[3] @@ -2175,10 +2060,9 @@ ; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -2193,10 +2077,9 @@ ; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -2211,10 +2094,9 @@ ; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -2229,10 +2111,9 @@ ; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0 @@ -2241,15 +2122,14 @@ ; CHECK-MVE-NEXT: vmov.u16 r0, q1[7] ; CHECK-MVE-NEXT: vcmp.f16 s0, s16 ; CHECK-MVE-NEXT: vmov s0, r0 -; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r0, q2[7] +; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: movne r1, #1 -; CHECK-MVE-NEXT: vmov s2, r0 +; CHECK-MVE-NEXT: vmov.u16 r0, q2[7] ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s2, r0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -2278,26 +2158,25 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9, d10} ; CHECK-MVE-NEXT: vpush {d8, d9, d10} -; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] ; CHECK-MVE-NEXT: vldr.16 s16, [r0] ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov s12, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vmov r0, s12 -; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] +; CHECK-MVE-NEXT: vmov.u16 r3, q1[0] ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: movs r2, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 @@ -2306,33 +2185,31 @@ ; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: movhi r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 -; CHECK-MVE-NEXT: vmov.16 q3[0], r0 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[2] -; CHECK-MVE-NEXT: vmov.16 q3[1], r2 ; CHECK-MVE-NEXT: vmov s18, r0 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[3] @@ -2345,10 +2222,9 @@ ; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -2363,10 +2239,9 @@ ; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -2381,10 +2256,9 @@ ; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -2399,10 +2273,9 @@ ; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0 @@ -2414,12 +2287,11 @@ ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: movhi r1, #1 -; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r0, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 -; CHECK-MVE-NEXT: vmov s2, r0 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s2, r0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -2450,26 +2322,25 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9, d10} ; CHECK-MVE-NEXT: vpush {d8, d9, d10} -; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] ; CHECK-MVE-NEXT: vldr.16 s16, [r0] ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov s12, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vmov r0, s12 -; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] +; CHECK-MVE-NEXT: vmov.u16 r3, q1[0] ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: movs r2, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 @@ -2478,33 +2349,31 @@ ; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: movpl r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 -; CHECK-MVE-NEXT: vmov.16 q3[0], r0 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[2] -; CHECK-MVE-NEXT: vmov.16 q3[1], r2 ; CHECK-MVE-NEXT: vmov s18, r0 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[3] @@ -2517,10 +2386,9 @@ ; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -2535,10 +2403,9 @@ ; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -2553,10 +2420,9 @@ ; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -2571,10 +2437,9 @@ ; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0 @@ -2586,12 +2451,11 @@ ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: movpl r1, #1 -; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r0, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 -; CHECK-MVE-NEXT: vmov s2, r0 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s2, r0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -2622,26 +2486,25 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9, d10} ; CHECK-MVE-NEXT: vpush {d8, d9, d10} -; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] ; CHECK-MVE-NEXT: vldr.16 s16, [r0] ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov s12, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vmov r0, s12 -; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] +; CHECK-MVE-NEXT: vmov.u16 r3, q1[0] ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: movs r2, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 @@ -2650,33 +2513,31 @@ ; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: movlt r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 -; CHECK-MVE-NEXT: vmov.16 q3[0], r0 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[2] -; CHECK-MVE-NEXT: vmov.16 q3[1], r2 ; CHECK-MVE-NEXT: vmov s18, r0 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[3] @@ -2689,10 +2550,9 @@ ; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -2707,10 +2567,9 @@ ; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -2725,10 +2584,9 @@ ; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -2743,10 +2601,9 @@ ; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0 @@ -2758,12 +2615,11 @@ ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: movlt r1, #1 -; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r0, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 -; CHECK-MVE-NEXT: vmov s2, r0 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s2, r0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -2793,26 +2649,25 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9, d10} ; CHECK-MVE-NEXT: vpush {d8, d9, d10} -; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] ; CHECK-MVE-NEXT: vldr.16 s16, [r0] ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov s12, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vmov r0, s12 -; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] +; CHECK-MVE-NEXT: vmov.u16 r3, q1[0] ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: movs r2, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 @@ -2821,33 +2676,31 @@ ; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: movle r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 -; CHECK-MVE-NEXT: vmov.16 q3[0], r0 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[2] -; CHECK-MVE-NEXT: vmov.16 q3[1], r2 ; CHECK-MVE-NEXT: vmov s18, r0 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[3] @@ -2860,10 +2713,9 @@ ; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -2878,10 +2730,9 @@ ; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -2896,10 +2747,9 @@ ; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -2914,10 +2764,9 @@ ; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0 @@ -2929,12 +2778,11 @@ ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: movle r1, #1 -; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r0, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 -; CHECK-MVE-NEXT: vmov s2, r0 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s2, r0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -2964,26 +2812,25 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9, d10} ; CHECK-MVE-NEXT: vpush {d8, d9, d10} -; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] ; CHECK-MVE-NEXT: vldr.16 s16, [r0] ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov s12, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vmov r0, s12 -; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] +; CHECK-MVE-NEXT: vmov.u16 r3, q1[0] ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: movs r2, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 @@ -2992,33 +2839,31 @@ ; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: movvc r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 -; CHECK-MVE-NEXT: vmov.16 q3[0], r0 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[2] -; CHECK-MVE-NEXT: vmov.16 q3[1], r2 ; CHECK-MVE-NEXT: vmov s18, r0 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[3] @@ -3031,10 +2876,9 @@ ; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -3049,10 +2893,9 @@ ; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -3067,10 +2910,9 @@ ; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -3085,10 +2927,9 @@ ; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0 @@ -3100,12 +2941,11 @@ ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: movvc r1, #1 -; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r0, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 -; CHECK-MVE-NEXT: vmov s2, r0 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s2, r0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -3138,26 +2978,25 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9, d10} ; CHECK-MVE-NEXT: vpush {d8, d9, d10} -; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] ; CHECK-MVE-NEXT: vldr.16 s16, [r0] ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov s12, r2 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vmov r0, s12 -; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] +; CHECK-MVE-NEXT: vmov.u16 r3, q1[0] ; CHECK-MVE-NEXT: vmov s12, r2 ; CHECK-MVE-NEXT: movs r2, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 @@ -3166,33 +3005,31 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 -; CHECK-MVE-NEXT: vmov.16 q3[0], r0 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[2] -; CHECK-MVE-NEXT: vmov.16 q3[1], r2 ; CHECK-MVE-NEXT: vmov s18, r0 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: vmov s18, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] +; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.u16 r0, q0[3] @@ -3205,10 +3042,9 @@ ; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -3223,10 +3059,9 @@ ; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -3241,10 +3076,9 @@ ; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 @@ -3259,10 +3093,9 @@ ; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s20, r2 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0 @@ -3274,12 +3107,11 @@ ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r1, #1 -; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r0, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 -; CHECK-MVE-NEXT: vmov s2, r0 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: vmov s2, r0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 Index: llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll +++ llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll @@ -5,45 +5,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_oeq_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmp.f32 s1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmp.f32 s0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmp.f32 s1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmp.f32 s3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmp.f32 s2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: bx lr ; @@ -61,30 +57,28 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_one_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmp.f32 s1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr -; CHECK-MVE-NEXT: vcmp.f32 s1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmp.f32 s0, #0 +; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r2, #1 -; CHECK-MVE-NEXT: vcmp.f32 s3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r3, #1 @@ -92,24 +86,22 @@ ; CHECK-MVE-NEXT: movgt r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: mov.w r0, #0 -; CHECK-MVE-NEXT: vcmp.f32 s2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: vcmp.f32 s3, #0 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: bx lr ; @@ -131,45 +123,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ogt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_ogt_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, #0 +; CHECK-MVE-NEXT: vcmpe.f32 s0, #0 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, #0 +; CHECK-MVE-NEXT: vcmpe.f32 s2, #0 ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, #0 +; CHECK-MVE-NEXT: vcmpe.f32 s3, #0 ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: bx lr ; @@ -187,45 +175,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_oge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_oge_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, #0 +; CHECK-MVE-NEXT: vcmpe.f32 s0, #0 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, #0 +; CHECK-MVE-NEXT: vcmpe.f32 s2, #0 ; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: movge r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, #0 +; CHECK-MVE-NEXT: vcmpe.f32 s3, #0 ; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: movge r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: bx lr ; @@ -243,45 +227,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_olt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_olt_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, #0 +; CHECK-MVE-NEXT: vcmpe.f32 s0, #0 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, #0 +; CHECK-MVE-NEXT: vcmpe.f32 s2, #0 ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, #0 +; CHECK-MVE-NEXT: vcmpe.f32 s3, #0 ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: bx lr ; @@ -299,45 +279,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ole_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_ole_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, #0 +; CHECK-MVE-NEXT: vcmpe.f32 s0, #0 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, #0 +; CHECK-MVE-NEXT: vcmpe.f32 s2, #0 ; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: movls r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, #0 +; CHECK-MVE-NEXT: vcmpe.f32 s3, #0 ; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: movls r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: bx lr ; @@ -355,30 +331,28 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_ueq_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmp.f32 s1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr -; CHECK-MVE-NEXT: vcmp.f32 s1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmp.f32 s0, #0 +; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r2, #1 -; CHECK-MVE-NEXT: vcmp.f32 s3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r3, #1 @@ -386,24 +360,22 @@ ; CHECK-MVE-NEXT: movvs r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: mov.w r0, #0 -; CHECK-MVE-NEXT: vcmp.f32 s2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: vcmp.f32 s3, #0 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: bx lr ; @@ -424,45 +396,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_une_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmp.f32 s1, #0 +; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmp.f32 s0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmp.f32 s1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmp.f32 s3, #0 +; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: movne r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmp.f32 s2, #0 +; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: movne r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: bx lr ; @@ -480,45 +448,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ugt_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_ugt_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, #0 +; CHECK-MVE-NEXT: vcmpe.f32 s0, #0 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, #0 +; CHECK-MVE-NEXT: vcmpe.f32 s2, #0 ; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: movhi r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, #0 +; CHECK-MVE-NEXT: vcmpe.f32 s3, #0 ; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: movhi r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: bx lr ; @@ -537,45 +501,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_uge_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_uge_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, #0 +; CHECK-MVE-NEXT: vcmpe.f32 s0, #0 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, #0 +; CHECK-MVE-NEXT: vcmpe.f32 s2, #0 ; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: movpl r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, #0 +; CHECK-MVE-NEXT: vcmpe.f32 s3, #0 ; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: movpl r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: bx lr ; @@ -594,45 +554,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ult_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_ult_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, #0 +; CHECK-MVE-NEXT: vcmpe.f32 s0, #0 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, #0 +; CHECK-MVE-NEXT: vcmpe.f32 s2, #0 ; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: movlt r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, #0 +; CHECK-MVE-NEXT: vcmpe.f32 s3, #0 ; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: movlt r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: bx lr ; @@ -651,45 +607,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ule_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_ule_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, #0 +; CHECK-MVE-NEXT: vcmpe.f32 s0, #0 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, #0 +; CHECK-MVE-NEXT: vcmpe.f32 s2, #0 ; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: movle r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, #0 +; CHECK-MVE-NEXT: vcmpe.f32 s3, #0 ; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: movle r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: bx lr ; @@ -708,45 +660,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ord_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_ord_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, s1 +; CHECK-MVE-NEXT: vcmpe.f32 s0, s0 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, s0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, s1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, s3 +; CHECK-MVE-NEXT: vcmpe.f32 s2, s2 ; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: movvc r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, s2 +; CHECK-MVE-NEXT: vcmpe.f32 s3, s3 ; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: movvc r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: bx lr ; @@ -768,45 +716,41 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_uno_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { ; CHECK-MVE-LABEL: vcmp_uno_v4f32: ; CHECK-MVE: @ %bb.0: @ %entry -; CHECK-MVE-NEXT: vcmpe.f32 s1, s1 +; CHECK-MVE-NEXT: vcmpe.f32 s0, s0 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s0, s0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vcmpe.f32 s1, s1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r2, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s3, s3 +; CHECK-MVE-NEXT: vcmpe.f32 s2, s2 ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: mov.w r3, #0 -; CHECK-MVE-NEXT: vcmpe.f32 s2, s2 +; CHECK-MVE-NEXT: vcmpe.f32 s3, s3 ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r3, #1 ; CHECK-MVE-NEXT: cmp r3, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r3, #1 +; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 -; CHECK-MVE-NEXT: cmp r3, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: bx lr ; @@ -831,8 +775,8 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9} -; CHECK-MVE-NEXT: vmov.u16 r1, q0[0] -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r1, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vmov s12, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0 @@ -841,14 +785,13 @@ ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 -; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] +; CHECK-MVE-NEXT: vmov.u16 r3, q1[0] ; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov s12, r2 @@ -859,32 +802,30 @@ ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 -; CHECK-MVE-NEXT: vmov.16 q3[0], r1 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[2] -; CHECK-MVE-NEXT: vmov.16 q3[1], r2 ; CHECK-MVE-NEXT: vmov s16, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[3] @@ -897,10 +838,9 @@ ; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -915,10 +855,9 @@ ; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -933,10 +872,9 @@ ; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -951,10 +889,9 @@ ; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1 @@ -968,10 +905,9 @@ ; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -1007,11 +943,10 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] ; CHECK-MVE-NEXT: vmov r1, s12 @@ -1026,11 +961,10 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov r2, s12 @@ -1047,12 +981,11 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -1068,11 +1001,10 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vmov r1, s16 @@ -1088,11 +1020,10 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vmov r1, s16 @@ -1108,11 +1039,10 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vmov r1, s16 @@ -1128,11 +1058,10 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1 @@ -1147,11 +1076,10 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -1179,8 +1107,8 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9} -; CHECK-MVE-NEXT: vmov.u16 r1, q0[0] -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r1, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vmov s12, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, #0 @@ -1189,14 +1117,13 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 -; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] +; CHECK-MVE-NEXT: vmov.u16 r3, q1[0] ; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov s12, r2 @@ -1207,32 +1134,30 @@ ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 -; CHECK-MVE-NEXT: vmov.16 q3[0], r1 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[2] -; CHECK-MVE-NEXT: vmov.16 q3[1], r2 ; CHECK-MVE-NEXT: vmov s16, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[3] @@ -1245,10 +1170,9 @@ ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -1263,10 +1187,9 @@ ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -1281,10 +1204,9 @@ ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -1299,10 +1221,9 @@ ; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1 @@ -1316,10 +1237,9 @@ ; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -1343,8 +1263,8 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9} -; CHECK-MVE-NEXT: vmov.u16 r1, q0[0] -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r1, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vmov s12, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, #0 @@ -1353,14 +1273,13 @@ ; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 -; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] +; CHECK-MVE-NEXT: vmov.u16 r3, q1[0] ; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov s12, r2 @@ -1371,32 +1290,30 @@ ; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: movge r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 -; CHECK-MVE-NEXT: vmov.16 q3[0], r1 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[2] -; CHECK-MVE-NEXT: vmov.16 q3[1], r2 ; CHECK-MVE-NEXT: vmov s16, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[3] @@ -1409,10 +1326,9 @@ ; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -1427,10 +1343,9 @@ ; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -1445,10 +1360,9 @@ ; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -1463,10 +1377,9 @@ ; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1 @@ -1480,10 +1393,9 @@ ; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -1507,8 +1419,8 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9} -; CHECK-MVE-NEXT: vmov.u16 r1, q0[0] -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r1, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vmov s12, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, #0 @@ -1517,14 +1429,13 @@ ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 -; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] +; CHECK-MVE-NEXT: vmov.u16 r3, q1[0] ; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov s12, r2 @@ -1535,32 +1446,30 @@ ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 -; CHECK-MVE-NEXT: vmov.16 q3[0], r1 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[2] -; CHECK-MVE-NEXT: vmov.16 q3[1], r2 ; CHECK-MVE-NEXT: vmov s16, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[3] @@ -1573,10 +1482,9 @@ ; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -1591,10 +1499,9 @@ ; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -1609,10 +1516,9 @@ ; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -1627,10 +1533,9 @@ ; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1 @@ -1644,10 +1549,9 @@ ; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -1671,8 +1575,8 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9} -; CHECK-MVE-NEXT: vmov.u16 r1, q0[0] -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r1, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vmov s12, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, #0 @@ -1681,14 +1585,13 @@ ; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 -; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] +; CHECK-MVE-NEXT: vmov.u16 r3, q1[0] ; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov s12, r2 @@ -1699,32 +1602,30 @@ ; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: movls r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 -; CHECK-MVE-NEXT: vmov.16 q3[0], r1 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[2] -; CHECK-MVE-NEXT: vmov.16 q3[1], r2 ; CHECK-MVE-NEXT: vmov s16, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[3] @@ -1737,10 +1638,9 @@ ; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -1755,10 +1655,9 @@ ; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -1773,10 +1672,9 @@ ; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -1791,10 +1689,9 @@ ; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1 @@ -1808,10 +1705,9 @@ ; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -1847,11 +1743,10 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] ; CHECK-MVE-NEXT: vmov r1, s12 @@ -1866,11 +1761,10 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov r2, s12 @@ -1887,12 +1781,11 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -1908,11 +1801,10 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vmov r1, s16 @@ -1928,11 +1820,10 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vmov r1, s16 @@ -1948,11 +1839,10 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vmov r1, s16 @@ -1968,11 +1858,10 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1 @@ -1987,11 +1876,10 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -2018,8 +1906,8 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9} -; CHECK-MVE-NEXT: vmov.u16 r1, q0[0] -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r1, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vmov s12, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0 @@ -2028,14 +1916,13 @@ ; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 -; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] +; CHECK-MVE-NEXT: vmov.u16 r3, q1[0] ; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov s12, r2 @@ -2046,32 +1933,30 @@ ; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: movne r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 -; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq +; CHECK-MVE-NEXT: vmov s14, r3 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 -; CHECK-MVE-NEXT: vmov.16 q3[0], r1 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[2] -; CHECK-MVE-NEXT: vmov.16 q3[1], r2 ; CHECK-MVE-NEXT: vmov s16, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[3] @@ -2084,10 +1969,9 @@ ; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -2102,10 +1986,9 @@ ; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -2120,10 +2003,9 @@ ; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -2138,10 +2020,9 @@ ; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1 @@ -2155,10 +2036,9 @@ ; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -2182,8 +2062,8 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9} -; CHECK-MVE-NEXT: vmov.u16 r1, q0[0] -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r1, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vmov s12, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, #0 @@ -2192,14 +2072,13 @@ ; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 -; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] +; CHECK-MVE-NEXT: vmov.u16 r3, q1[0] ; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov s12, r2 @@ -2210,32 +2089,30 @@ ; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: movhi r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 -; CHECK-MVE-NEXT: vmov.16 q3[0], r1 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[2] -; CHECK-MVE-NEXT: vmov.16 q3[1], r2 ; CHECK-MVE-NEXT: vmov s16, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[3] @@ -2248,10 +2125,9 @@ ; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -2266,10 +2142,9 @@ ; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -2284,10 +2159,9 @@ ; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -2302,10 +2176,9 @@ ; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1 @@ -2319,10 +2192,9 @@ ; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -2347,8 +2219,8 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9} -; CHECK-MVE-NEXT: vmov.u16 r1, q0[0] -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r1, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vmov s12, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, #0 @@ -2357,14 +2229,13 @@ ; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 -; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] +; CHECK-MVE-NEXT: vmov.u16 r3, q1[0] ; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov s12, r2 @@ -2375,32 +2246,30 @@ ; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: movpl r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 -; CHECK-MVE-NEXT: vmov.16 q3[0], r1 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[2] -; CHECK-MVE-NEXT: vmov.16 q3[1], r2 ; CHECK-MVE-NEXT: vmov s16, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[3] @@ -2413,10 +2282,9 @@ ; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -2431,10 +2299,9 @@ ; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -2449,10 +2316,9 @@ ; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -2467,10 +2333,9 @@ ; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1 @@ -2484,10 +2349,9 @@ ; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -2512,8 +2376,8 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9} -; CHECK-MVE-NEXT: vmov.u16 r1, q0[0] -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r1, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vmov s12, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, #0 @@ -2522,14 +2386,13 @@ ; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 -; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] +; CHECK-MVE-NEXT: vmov.u16 r3, q1[0] ; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov s12, r2 @@ -2540,32 +2403,30 @@ ; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: movlt r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 -; CHECK-MVE-NEXT: vmov.16 q3[0], r1 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[2] -; CHECK-MVE-NEXT: vmov.16 q3[1], r2 ; CHECK-MVE-NEXT: vmov s16, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[3] @@ -2578,10 +2439,9 @@ ; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -2596,10 +2456,9 @@ ; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -2614,10 +2473,9 @@ ; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -2632,10 +2490,9 @@ ; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1 @@ -2649,10 +2506,9 @@ ; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -2677,8 +2533,8 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9} -; CHECK-MVE-NEXT: vmov.u16 r1, q0[0] -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r1, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vmov s12, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, #0 @@ -2687,14 +2543,13 @@ ; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 -; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] +; CHECK-MVE-NEXT: vmov.u16 r3, q1[0] ; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov s12, r2 @@ -2705,32 +2560,30 @@ ; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: movle r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 -; CHECK-MVE-NEXT: vmov.16 q3[0], r1 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[2] -; CHECK-MVE-NEXT: vmov.16 q3[1], r2 ; CHECK-MVE-NEXT: vmov s16, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[3] @@ -2743,10 +2596,9 @@ ; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -2761,10 +2613,9 @@ ; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -2779,10 +2630,9 @@ ; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -2797,10 +2647,9 @@ ; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1 @@ -2814,10 +2663,9 @@ ; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -2842,8 +2690,8 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9} -; CHECK-MVE-NEXT: vmov.u16 r1, q0[0] -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r1, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vmov s12, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s12 @@ -2852,14 +2700,13 @@ ; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 -; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] +; CHECK-MVE-NEXT: vmov.u16 r3, q1[0] ; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov s12, r2 @@ -2870,32 +2717,30 @@ ; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: movvc r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 -; CHECK-MVE-NEXT: vmov.16 q3[0], r1 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[2] -; CHECK-MVE-NEXT: vmov.16 q3[1], r2 ; CHECK-MVE-NEXT: vmov s16, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[3] @@ -2908,10 +2753,9 @@ ; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -2926,10 +2770,9 @@ ; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -2944,10 +2787,9 @@ ; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -2962,10 +2804,9 @@ ; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1 @@ -2979,10 +2820,9 @@ ; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 @@ -3010,8 +2850,8 @@ ; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE-NEXT: .vsave {d8, d9} ; CHECK-MVE-NEXT: vpush {d8, d9} -; CHECK-MVE-NEXT: vmov.u16 r1, q0[0] -; CHECK-MVE-NEXT: vmov.u16 r2, q1[0] +; CHECK-MVE-NEXT: vmov.u16 r1, q0[1] +; CHECK-MVE-NEXT: vmov.u16 r2, q1[1] ; CHECK-MVE-NEXT: vmov s12, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s12 @@ -3020,14 +2860,13 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q2[0] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: vmov.u16 r2, q2[1] +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov.u16 r2, q0[1] +; CHECK-MVE-NEXT: lsls r1, r1, #31 +; CHECK-MVE-NEXT: vmov.u16 r2, q0[0] ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 -; CHECK-MVE-NEXT: vmov.u16 r3, q1[1] +; CHECK-MVE-NEXT: vmov.u16 r3, q1[0] ; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: vmov s12, r2 @@ -3038,32 +2877,30 @@ ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: cmp r2, #0 -; CHECK-MVE-NEXT: vmov.u16 r3, q2[1] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r2, #1 +; CHECK-MVE-NEXT: vmov.u16 r3, q2[0] +; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: vmov s14, r3 -; CHECK-MVE-NEXT: cmp r2, #0 +; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vmov r2, s12 -; CHECK-MVE-NEXT: vmov.16 q3[0], r1 +; CHECK-MVE-NEXT: vmov.16 q3[0], r2 +; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[2] -; CHECK-MVE-NEXT: vmov.16 q3[1], r2 ; CHECK-MVE-NEXT: vmov s16, r1 ; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, s16 -; CHECK-MVE-NEXT: vmov.u16 r2, q1[2] +; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vmov s16, r2 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[2] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 -; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[3] +; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.u16 r1, q0[3] @@ -3076,10 +2913,9 @@ ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[3] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[4] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -3094,10 +2930,9 @@ ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[4] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[5] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -3112,10 +2947,9 @@ ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[5] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vmov.u16 r2, q1[6] ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 @@ -3130,10 +2964,9 @@ ; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: vmov.u16 r2, q2[6] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r1, #1 +; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: vmov s18, r2 -; CHECK-MVE-NEXT: cmp r1, #0 +; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1 @@ -3147,10 +2980,9 @@ ; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: vmov.u16 r1, q2[7] -; CHECK-MVE-NEXT: it ne -; CHECK-MVE-NEXT: movne r0, #1 +; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: vmov s2, r1 -; CHECK-MVE-NEXT: cmp r0, #0 +; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0 Index: llvm/test/CodeGen/Thumb2/mve-vcmpr.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-vcmpr.ll +++ llvm/test/CodeGen/Thumb2/mve-vcmpr.ll @@ -444,10 +444,9 @@ ; CHECK-NEXT: eors r2, r1 ; CHECK-NEXT: eors r3, r0 ; CHECK-NEXT: orrs r2, r3 -; CHECK-NEXT: clz r2, r2 -; CHECK-NEXT: lsrs r2, r2, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r2, #-1 +; CHECK-NEXT: csinc r2, zr, zr, ne +; CHECK-NEXT: tst.w r2, #1 +; CHECK-NEXT: csinv r2, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[0], r2 ; CHECK-NEXT: vmov.32 q3[1], r2 ; CHECK-NEXT: vmov r2, s3 @@ -455,10 +454,9 @@ ; CHECK-NEXT: vmov r2, s2 ; CHECK-NEXT: eors r0, r2 ; CHECK-NEXT: orrs r0, r1 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vbic q0, q2, q3 @@ -481,10 +479,9 @@ ; CHECK-NEXT: eors r2, r1 ; CHECK-NEXT: eors r3, r0 ; CHECK-NEXT: orrs r2, r3 -; CHECK-NEXT: clz r2, r2 -; CHECK-NEXT: lsrs r2, r2, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r2, #-1 +; CHECK-NEXT: csinc r2, zr, zr, ne +; CHECK-NEXT: tst.w r2, #1 +; CHECK-NEXT: csinv r2, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[0], r2 ; CHECK-NEXT: vmov.32 q3[1], r2 ; CHECK-NEXT: vmov r2, s3 @@ -492,10 +489,9 @@ ; CHECK-NEXT: vmov r2, s2 ; CHECK-NEXT: eors r0, r2 ; CHECK-NEXT: orrs r0, r1 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vbic q0, q2, q3 @@ -521,79 +517,67 @@ ; CHECK-NEXT: movs r3, #0 ; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r2, s8 -; CHECK-NEXT: vmov lr, s10 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s2 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[0], r0 ; CHECK-NEXT: vmov.32 q3[1], r0 ; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: orrs r0, r1 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vbic q0, q2, q3 -; CHECK-NEXT: vmov r0, s0 -; CHECK-NEXT: subs r1, r0, r2 -; CHECK-NEXT: asr.w r12, r0, #31 +; CHECK-NEXT: vmov lr, s0 +; CHECK-NEXT: subs.w r1, lr, r2 +; CHECK-NEXT: asr.w r12, lr, #31 ; CHECK-NEXT: sbcs.w r1, r12, r2, asr #31 ; CHECK-NEXT: mov.w r1, #0 +; CHECK-NEXT: vmov r2, s10 ; CHECK-NEXT: it lt ; CHECK-NEXT: movlt r1, #1 ; CHECK-NEXT: cmp r1, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r1, #-1 +; CHECK-NEXT: csinv r1, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[0], r1 ; CHECK-NEXT: vmov.32 q3[1], r1 ; CHECK-NEXT: vmov r1, s2 -; CHECK-NEXT: subs.w r2, r1, lr +; CHECK-NEXT: subs r0, r1, r2 ; CHECK-NEXT: asr.w r12, r1, #31 -; CHECK-NEXT: sbcs.w r2, r12, lr, asr #31 +; CHECK-NEXT: sbcs.w r0, r12, r2, asr #31 ; CHECK-NEXT: it lt ; CHECK-NEXT: movlt r3, #1 ; CHECK-NEXT: cmp r3, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r3, #-1 -; CHECK-NEXT: cmp r0, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne r0, #1 -; CHECK-NEXT: cmp r0, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinv r0, zr, zr, eq +; CHECK-NEXT: cmp.w lr, #0 +; CHECK-NEXT: vmov.32 q3[2], r0 +; CHECK-NEXT: vmov.32 q3[3], r0 +; CHECK-NEXT: csinc r0, zr, zr, eq +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq +; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: vmov.32 q4[0], r0 ; CHECK-NEXT: vmov.32 q4[1], r0 +; CHECK-NEXT: csinc r0, zr, zr, eq +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq +; CHECK-NEXT: vmov.32 q4[2], r0 +; CHECK-NEXT: vmov.32 q4[3], r0 ; CHECK-NEXT: vmov r0, s4 -; CHECK-NEXT: cmp r1, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne r1, #1 -; CHECK-NEXT: cmp r1, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r1, #-1 -; CHECK-NEXT: vmov.32 q4[2], r1 -; CHECK-NEXT: vmov.32 q3[2], r3 -; CHECK-NEXT: vmov.32 q4[3], r1 -; CHECK-NEXT: vmov.32 q3[3], r3 ; CHECK-NEXT: cmp r0, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne r0, #1 -; CHECK-NEXT: cmp r0, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, eq +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q5[0], r0 ; CHECK-NEXT: vmov.32 q5[1], r0 ; CHECK-NEXT: vmov r0, s6 ; CHECK-NEXT: cmp r0, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne r0, #1 -; CHECK-NEXT: cmp r0, #0 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, eq +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q5[2], r0 ; CHECK-NEXT: vmov.32 q5[3], r0 ; CHECK-NEXT: vand q1, q5, q4 Index: llvm/test/CodeGen/Thumb2/mve-vcmpz.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-vcmpz.ll +++ llvm/test/CodeGen/Thumb2/mve-vcmpz.ll @@ -365,18 +365,16 @@ ; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s2 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[0], r0 ; CHECK-NEXT: vmov.32 q3[1], r0 ; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: orrs r0, r1 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vbic q0, q2, q3 @@ -396,18 +394,16 @@ ; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: vmov r1, s2 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[0], r0 ; CHECK-NEXT: vmov.32 q3[1], r0 ; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: orrs r0, r1 -; CHECK-NEXT: clz r0, r0 -; CHECK-NEXT: lsrs r0, r0, #5 -; CHECK-NEXT: it ne -; CHECK-NEXT: movne.w r0, #-1 +; CHECK-NEXT: csinc r0, zr, zr, ne +; CHECK-NEXT: tst.w r0, #1 +; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vbic q0, q2, q3 Index: llvm/test/CodeGen/Thumb2/mve-vfma.ll =================================================================== --- llvm/test/CodeGen/Thumb2/mve-vfma.ll +++ llvm/test/CodeGen/Thumb2/mve-vfma.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s define arm_aapcs_vfpcc <4 x float> @fma_v4f32(<4 x float> %dst, <4 x float> %s1, <4 x float> %s2) {