Index: llvm/include/llvm/Target/TargetSelectionDAG.td =================================================================== --- llvm/include/llvm/Target/TargetSelectionDAG.td +++ llvm/include/llvm/Target/TargetSelectionDAG.td @@ -419,6 +419,8 @@ def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; def vecreduce_add : SDNode<"ISD::VECREDUCE_ADD", SDTVecReduce>; +def vecreduce_smax : SDNode<"ISD::VECREDUCE_SMAX", SDTVecReduce>; +def vecreduce_umax : SDNode<"ISD::VECREDUCE_UMAX", SDTVecReduce>; def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; Index: llvm/lib/Target/ARM/ARMISelLowering.cpp =================================================================== --- llvm/lib/Target/ARM/ARMISelLowering.cpp +++ llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -269,6 +269,8 @@ // Vector reductions setOperationAction(ISD::VECREDUCE_ADD, VT, Legal); + setOperationAction(ISD::VECREDUCE_SMAX, VT, Legal); + setOperationAction(ISD::VECREDUCE_UMAX, VT, Legal); if (!HasMVEFP) { setOperationAction(ISD::SINT_TO_FP, VT, Expand); Index: llvm/lib/Target/ARM/ARMInstrMVE.td =================================================================== --- llvm/lib/Target/ARM/ARMInstrMVE.td +++ llvm/lib/Target/ARM/ARMInstrMVE.td @@ -667,6 +667,22 @@ defm MVE_VMINV : MVE_VMINMAXV_ty<"vminv", 0b1>; defm MVE_VMAXV : MVE_VMINMAXV_ty<"vmaxv", 0b0>; +let Predicates = [HasMVEInt] in { + def : Pat<(i32 (vecreduce_smax (v16i8 MQPR:$src))), + (i32 (MVE_VMAXVs8 (t2MVNi (i32 127)), $src))>; + def : Pat<(i32 (vecreduce_smax (v8i16 MQPR:$src))), + (i32 (MVE_VMAXVs16 (t2MOVi32imm (i32 -32768)), $src))>; + def : Pat<(i32 (vecreduce_smax (v4i32 MQPR:$src))), + (i32 (MVE_VMAXVs32 (t2MOVi (i32 -2147483648)), $src))>; + def : Pat<(i32 (vecreduce_umax (v16i8 MQPR:$src))), + (i32 (MVE_VMAXVu8 (t2MOVi (i32 0)), $src))>; + def : Pat<(i32 (vecreduce_umax (v8i16 MQPR:$src))), + (i32 (MVE_VMAXVu16 (t2MOVi (i32 0)), $src))>; + def : Pat<(i32 (vecreduce_umax (v4i32 MQPR:$src))), + (i32 (MVE_VMAXVu32 (t2MOVi (i32 0)), $src))>; + +} + multiclass MVE_VMINMAXAV_ty pattern=[]> { def s8 : MVE_VMINMAXV; def s16 : MVE_VMINMAXV; Index: llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp =================================================================== --- llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp +++ llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp @@ -1059,11 +1059,11 @@ case Instruction::Or: case Instruction::Xor: case Instruction::Mul: - case Instruction::ICmp: case Instruction::FCmp: return false; + case Instruction::ICmp: case Instruction::Add: - return ScalarBits * Ty->getVectorNumElements() == 128; + return ScalarBits < 64 && ScalarBits * Ty->getVectorNumElements() == 128; default: llvm_unreachable("Unhandled reduction opcode"); } Index: llvm/test/CodeGen/Thumb2/mve-vmaxv.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/Thumb2/mve-vmaxv.ll @@ -0,0 +1,69 @@ +; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s + +declare i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8>) +declare i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16>) +declare i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32>) +declare i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8>) +declare i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16>) +declare i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32>) + +define arm_aapcs_vfpcc i8 @vmaxv_s_v16i8_i32(<16 x i8> %s1) { +; CHECK-LABEL: vmaxv_s_v16i8_i32: +; CHECK: @ %bb.0: +; CHECK-NEXT: mvn r0, #127 +; CHECK-NEXT: vmaxv.s8 r0, q0 +; CHECK-NEXT: bx lr + %r = call i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8> %s1) + ret i8 %r +} + +define arm_aapcs_vfpcc i16 @vmaxv_s_v8i16_i32(<8 x i16> %s1) { +; CHECK-LABEL: vmaxv_s_v8i16_i32: +; CHECK: @ %bb.0: +; CHECK-NEXT: movw r0, #32768 +; CHECK-NEXT: movt r0, #65535 +; CHECK-NEXT: vmaxv.s16 r0, q0 +; CHECK-NEXT: bx lr + %r = call i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16> %s1) + ret i16 %r +} + +define arm_aapcs_vfpcc i32 @vmaxv_s_v4i32_i32(<4 x i32> %s1) { +; CHECK-LABEL: vmaxv_s_v4i32_i32: +; CHECK: @ %bb.0: +; CHECK-NEXT: mov.w r0, #-2147483648 +; CHECK-NEXT: vmaxv.s32 r0, q0 +; CHECK-NEXT: bx lr + %r = call i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> %s1) + ret i32 %r +} + +define arm_aapcs_vfpcc i8 @vmaxv_u_v16i8_i32(<16 x i8> %s1) { +; CHECK-LABEL: vmaxv_u_v16i8_i32: +; CHECK: @ %bb.0: +; CHECK-NEXT: movs r0, #0 +; CHECK-NEXT: vmaxv.u8 r0, q0 +; CHECK-NEXT: bx lr + %r = call i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8> %s1) + ret i8 %r +} + +define arm_aapcs_vfpcc i16 @vmaxv_u_v8i16_i32(<8 x i16> %s1) { +; CHECK-LABEL: vmaxv_u_v8i16_i32: +; CHECK: @ %bb.0: +; CHECK-NEXT: movs r0, #0 +; CHECK-NEXT: vmaxv.u16 r0, q0 +; CHECK-NEXT: bx lr + %r = call i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16> %s1) + ret i16 %r +} + +define arm_aapcs_vfpcc i32 @vmaxv_u_v4i32_i32(<4 x i32> %s1) { +; CHECK-LABEL: vmaxv_u_v4i32_i32: +; CHECK: @ %bb.0: +; CHECK-NEXT: movs r0, #0 +; CHECK-NEXT: vmaxv.u32 r0, q0 +; CHECK-NEXT: bx lr + %r = call i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32> %s1) + ret i32 %r +}