Index: lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp =================================================================== --- lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -867,8 +867,9 @@ Register QueuePtr = MRI.createGenericVirtualRegister( LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64)); - // FIXME: Placeholder until we can track the input registers. - MIRBuilder.buildConstant(QueuePtr, 0xdeadbeef); + const SIMachineFunctionInfo *MFI = MF.getInfo(); + if (!loadInputValue(QueuePtr, MIRBuilder, &MFI->getArgInfo().QueuePtr)) + return Register(); // Offset into amd_queue_t for group_segment_aperture_base_hi / // private_segment_aperture_base_hi. @@ -954,6 +955,8 @@ MIRBuilder.buildConstant(DstTy, TM.getNullPointerValue(DestAS)); Register ApertureReg = getSegmentAperture(DestAS, MRI, MIRBuilder); + if (!ApertureReg.isValid()) + return false; Register CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1)); MIRBuilder.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, SegmentNull.getReg(0)); @@ -1233,10 +1236,9 @@ bool AMDGPULegalizerInfo::loadInputValue(Register DstReg, MachineIRBuilder &B, const ArgDescriptor *Arg) const { - if (!Arg->isRegister()) + if (!Arg->isRegister() || !Arg->getRegister().isValid()) return false; // TODO: Handle these - assert(Arg->getRegister() != 0); assert(Arg->getRegister().isPhysical()); MachineRegisterInfo &MRI = *B.getMRI(); Index: test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir =================================================================== --- test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir +++ test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir @@ -1,9 +1,13 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -march=amdgcn -mcpu=fiji -O0 -run-pass=legalizer -global-isel-abort=0 -o - %s | FileCheck -check-prefix=VI %s -# RUN: llc -march=amdgcn -mcpu=gfx900 -O0 -run-pass=legalizer -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s +# RUN: llc -march=amdgcn -mcpu=fiji -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=VI %s +# RUN: llc -march=amdgcn -mcpu=gfx900 -O0 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s --- name: test_addrspacecast_p0_to_p1 +machineFunctionInfo: + argumentInfo: + queuePtr: { reg: '$sgpr4_sgpr5' } + body: | bb.0: liveins: $vgpr0_vgpr1 @@ -23,6 +27,10 @@ --- name: test_addrspacecast_p1_to_p0 +machineFunctionInfo: + argumentInfo: + queuePtr: { reg: '$sgpr4_sgpr5' } + body: | bb.0: liveins: $vgpr0_vgpr1 @@ -42,6 +50,9 @@ --- name: test_addrspacecast_p0_to_p4 +machineFunctionInfo: + argumentInfo: + queuePtr: { reg: '$sgpr4_sgpr5' } body: | bb.0: liveins: $vgpr0_vgpr1 @@ -61,6 +72,9 @@ --- name: test_addrspacecast_p4_to_p0 +machineFunctionInfo: + argumentInfo: + queuePtr: { reg: '$sgpr4_sgpr5' } body: | bb.0: liveins: $vgpr0_vgpr1 @@ -80,6 +94,9 @@ --- name: test_addrspacecast_p0_to_p999 +machineFunctionInfo: + argumentInfo: + queuePtr: { reg: '$sgpr4_sgpr5' } body: | bb.0: liveins: $vgpr0_vgpr1 @@ -99,6 +116,9 @@ --- name: test_addrspacecast_p999_to_p0 +machineFunctionInfo: + argumentInfo: + queuePtr: { reg: '$sgpr4_sgpr5' } body: | bb.0: liveins: $vgpr0_vgpr1 @@ -118,22 +138,26 @@ --- name: test_addrspacecast_p5_to_p0 +machineFunctionInfo: + argumentInfo: + queuePtr: { reg: '$sgpr4_sgpr5' } body: | bb.0: liveins: $vgpr0 ; VI-LABEL: name: test_addrspacecast_p5_to_p0 - ; VI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0 - ; VI: [[C:%[0-9]+]]:_(p5) = G_CONSTANT i32 0 - ; VI: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0 - ; VI: [[C2:%[0-9]+]]:_(p4) = G_CONSTANT i64 3735928559 - ; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 68 - ; VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[C2]], [[C3]](s64) + ; VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 + ; VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 68 + ; VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP %4, [[C]](s64) ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GEP]](p4) :: (dereferenceable invariant load 4 from `i8 addrspace(4)* undef` + 68, addrspace 4) - ; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p5), [[C]] - ; VI: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p5) + ; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), %0(p5), %2 + ; VI: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT %0(p5) ; VI: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[PTRTOINT]](s32), [[LOAD]](s32) - ; VI: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[MV]], [[C1]] + ; VI: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[MV]], %3 + ; VI: [[COPY1:%[0-9]+]]:_(p5) = COPY $vgpr0 + ; VI: [[C1:%[0-9]+]]:_(p5) = G_CONSTANT i32 0 + ; VI: [[C2:%[0-9]+]]:_(p0) = G_CONSTANT i64 0 + ; VI: [[COPY2:%[0-9]+]]:_(p4) = COPY [[COPY]](p4) ; VI: $vgpr0_vgpr1 = COPY [[SELECT]](p0) ; GFX9-LABEL: name: test_addrspacecast_p5_to_p0 ; GFX9: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0 @@ -154,6 +178,9 @@ --- name: test_addrspacecast_p0_to_p5 +machineFunctionInfo: + argumentInfo: + queuePtr: { reg: '$sgpr4_sgpr5' } body: | bb.0: liveins: $vgpr0_vgpr1 @@ -181,22 +208,27 @@ --- name: test_addrspacecast_p3_to_p0 +machineFunctionInfo: + argumentInfo: + queuePtr: { reg: '$sgpr4_sgpr5' } + body: | bb.0: liveins: $vgpr0 ; VI-LABEL: name: test_addrspacecast_p3_to_p0 - ; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0 - ; VI: [[C:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1 - ; VI: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0 - ; VI: [[C2:%[0-9]+]]:_(p4) = G_CONSTANT i64 3735928559 - ; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 68 - ; VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[C2]], [[C3]](s64) + ; VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 + ; VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 68 + ; VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP %4, [[C]](s64) ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GEP]](p4) :: (dereferenceable invariant load 4 from `i8 addrspace(4)* undef` + 68, addrspace 4) - ; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p3), [[C]] - ; VI: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p3) + ; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), %0(p3), %2 + ; VI: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT %0(p3) ; VI: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[PTRTOINT]](s32), [[LOAD]](s32) - ; VI: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[MV]], [[C1]] + ; VI: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[MV]], %3 + ; VI: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr0 + ; VI: [[C1:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1 + ; VI: [[C2:%[0-9]+]]:_(p0) = G_CONSTANT i64 0 + ; VI: [[COPY2:%[0-9]+]]:_(p4) = COPY [[COPY]](p4) ; VI: $vgpr0_vgpr1 = COPY [[SELECT]](p0) ; GFX9-LABEL: name: test_addrspacecast_p3_to_p0 ; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0 @@ -217,6 +249,9 @@ --- name: test_addrspacecast_p0_to_p3 +machineFunctionInfo: + argumentInfo: + queuePtr: { reg: '$sgpr4_sgpr5' } body: | bb.0: liveins: $vgpr0_vgpr1 @@ -244,6 +279,9 @@ --- name: test_addrspacecast_v2p0_to_v2p1 +machineFunctionInfo: + argumentInfo: + queuePtr: { reg: '$sgpr4_sgpr5' } body: | bb.0: liveins: $vgpr0_vgpr1_vgpr2_vgpr3 @@ -269,6 +307,9 @@ --- name: test_addrspacecast_v2p1_to_v2p0 +machineFunctionInfo: + argumentInfo: + queuePtr: { reg: '$sgpr4_sgpr5' } body: | bb.0: liveins: $vgpr0_vgpr1_vgpr2_vgpr3 @@ -294,6 +335,9 @@ --- name: test_addrspacecast_v2p0_to_v2p3 +machineFunctionInfo: + argumentInfo: + queuePtr: { reg: '$sgpr4_sgpr5' } body: | bb.0: liveins: $vgpr0_vgpr1_vgpr2_vgpr3 @@ -331,31 +375,35 @@ --- name: test_addrspacecast_v2p3_to_v2p0 +machineFunctionInfo: + argumentInfo: + queuePtr: { reg: '$sgpr4_sgpr5' } body: | bb.0: liveins: $vgpr0_vgpr1 ; VI-LABEL: name: test_addrspacecast_v2p3_to_v2p0 - ; VI: [[COPY:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1 - ; VI: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY]](<2 x p3>) - ; VI: [[C:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1 - ; VI: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0 - ; VI: [[C2:%[0-9]+]]:_(p4) = G_CONSTANT i64 3735928559 - ; VI: [[COPY1:%[0-9]+]]:_(p4) = COPY [[C2]](p4) - ; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 68 - ; VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY1]], [[C3]](s64) + ; VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5 + ; VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 68 + ; VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP %8, [[C]](s64) ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GEP]](p4) :: (dereferenceable invariant load 4 from `i8 addrspace(4)* undef` + 68, addrspace 4) - ; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p3), [[C]] - ; VI: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[UV]](p3) + ; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), %3(p3), %6 + ; VI: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT %3(p3) ; VI: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[PTRTOINT]](s32), [[LOAD]](s32) - ; VI: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[MV]], [[C1]] - ; VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[C2]], [[C3]](s64) + ; VI: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[MV]], %7 + ; VI: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1 + ; VI: [[UV:%[0-9]+]]:_(p3), [[UV1:%[0-9]+]]:_(p3) = G_UNMERGE_VALUES [[COPY1]](<2 x p3>) + ; VI: [[C1:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1 + ; VI: [[C2:%[0-9]+]]:_(p0) = G_CONSTANT i64 0 + ; VI: [[COPY2:%[0-9]+]]:_(p4) = COPY [[COPY]](p4) + ; VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY2]], [[C]](s64) ; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p4) :: (dereferenceable invariant load 4 from `i8 addrspace(4)* undef` + 68, addrspace 4) - ; VI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p3), [[C]] - ; VI: [[PTRTOINT1:%[0-9]+]]:_(s32) = G_PTRTOINT [[UV1]](p3) + ; VI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p3), [[C1]] + ; VI: [[PTRTOINT1:%[0-9]+]]:_(s32) = G_PTRTOINT [[UV]](p3) ; VI: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[PTRTOINT1]](s32), [[LOAD1]](s32) - ; VI: [[SELECT1:%[0-9]+]]:_(p0) = G_SELECT [[ICMP1]](s1), [[MV1]], [[C1]] - ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[SELECT]](p0), [[SELECT1]](p0) + ; VI: [[SELECT1:%[0-9]+]]:_(p0) = G_SELECT [[ICMP1]](s1), [[MV1]], [[C2]] + ; VI: [[COPY3:%[0-9]+]]:_(p4) = COPY [[COPY]](p4) + ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[SELECT1]](p0), [[SELECT]](p0) ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x p0>) ; GFX9-LABEL: name: test_addrspacecast_v2p3_to_v2p0 ; GFX9: [[COPY:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr0_vgpr1