diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
@@ -48,8 +48,8 @@
   void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
                                unsigned PrintMethodIdx,
                                const MCSubtargetInfo &STI, raw_ostream &O);
-  static const char *getRegisterName(unsigned RegNo,
-                                     unsigned AltIdx = RISCV::ABIRegAltName);
+  static const char *getRegisterName(unsigned RegNo);
+  static const char *getRegisterName(unsigned RegNo, unsigned AltIdx);
 };
 } // namespace llvm
 
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -39,6 +39,12 @@
               cl::desc("Disable the emission of assembler pseudo instructions"),
               cl::init(false), cl::Hidden);
 
+static cl::opt<bool>
+    ArchRegNames("riscv-arch-reg-names",
+                 cl::desc("Print architectural register names such as x0-x31 "
+                          "rather than the ABI name"),
+                 cl::init(false), cl::Hidden);
+
 void RISCVInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
                                  StringRef Annot, const MCSubtargetInfo &STI) {
   bool Res = false;
@@ -124,3 +130,8 @@
   O << ")";
   return;
 }
+
+const char *RISCVInstPrinter::getRegisterName(unsigned RegNo) {
+  return getRegisterName(RegNo, ArchRegNames ? RISCV::NoRegAltName
+                                             : RISCV::ABIRegAltName);
+}
diff --git a/llvm/test/CodeGen/RISCV/inline-asm-abi-names.ll b/llvm/test/CodeGen/RISCV/inline-asm-abi-names.ll
--- a/llvm/test/CodeGen/RISCV/inline-asm-abi-names.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm-abi-names.ll
@@ -3,6 +3,10 @@
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs -riscv-arch-reg-names < %s \
+; RUN:   | FileCheck -check-prefix=RV32I-NO-ABI %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs -riscv-arch-reg-names < %s \
+; RUN:   | FileCheck -check-prefix=RV64I-NO-ABI %s
 
 ; These test that we can use both the architectural names (x*) and the ABI names
 ; (a*, s*, t* etc) to refer to registers in inline asm constraint lists. In each
@@ -10,7 +14,9 @@
 ; It is very likely that `a0` will be chosen as the designation register, but
 ; this is left to the compiler to choose.
 ;
-; The inline assembly will, by default, contain the ABI names for the registers.
+; The inline assembly will, by default, contain the ABI names for the registers,
+; unless `-riscv-arch-reg-names` is passed to llc to print the architectural
+; names.
 ;
 ; Parenthesised registers in comments are the other aliases for this register.
 
@@ -30,6 +36,20 @@
 ; RV64I-NEXT:    addi a0, zero, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x0:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x0, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x0:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x0, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x0}"(i32 0)
   ret i32 %1
 }
@@ -50,6 +70,20 @@
 ; RV64I-NEXT:    addi a0, zero, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_zero:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x0, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_zero:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x0, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{zero}"(i32 0)
   ret i32 %1
 }
@@ -79,6 +113,30 @@
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x1:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x1, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x1, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x1, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x1, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x1:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x1, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x1, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x1, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x1, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x1}"(i32 %a)
   ret i32 %1
 }
@@ -108,6 +166,30 @@
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_ra:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x1, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x1, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x1, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x1, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_ra:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x1, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x1, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x1, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x1, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{ra}"(i32 %a)
   ret i32 %1
 }
@@ -128,6 +210,22 @@
 ; RV64I-NEXT:    addi a0, sp, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x2:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x2, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x2, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x2:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x2, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x2, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x2}"(i32 %a)
   ret i32 %1
 }
@@ -148,6 +246,22 @@
 ; RV64I-NEXT:    addi a0, sp, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_sp:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x2, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x2, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_sp:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x2, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x2, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{sp}"(i32 %a)
   ret i32 %1
 }
@@ -177,6 +291,30 @@
 ; RV64I-NEXT:    ld gp, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x3:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x3, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x3, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x3, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x3, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x3:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x3, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x3, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x3, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x3, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x3}"(i32 %a)
   ret i32 %1
 }
@@ -206,6 +344,30 @@
 ; RV64I-NEXT:    ld gp, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_gp:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x3, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x3, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x3, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x3, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_gp:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x3, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x3, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x3, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x3, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{gp}"(i32 %a)
   ret i32 %1
 }
@@ -235,6 +397,30 @@
 ; RV64I-NEXT:    ld tp, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x4:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x4, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x4, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x4, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x4, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x4:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x4, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x4, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x4, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x4, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x4}"(i32 %a)
   ret i32 %1
 }
@@ -264,6 +450,30 @@
 ; RV64I-NEXT:    ld tp, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_tp:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x4, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x4, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x4, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x4, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_tp:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x4, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x4, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x4, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x4, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{tp}"(i32 %a)
   ret i32 %1
 }
@@ -284,6 +494,22 @@
 ; RV64I-NEXT:    addi a0, t0, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x5:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x5, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x5, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x5:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x5, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x5, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x5}"(i32 %a)
   ret i32 %1
 }
@@ -304,6 +530,22 @@
 ; RV64I-NEXT:    addi a0, t0, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_t0:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x5, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x5, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_t0:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x5, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x5, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t0}"(i32 %a)
   ret i32 %1
 }
@@ -324,6 +566,22 @@
 ; RV64I-NEXT:    addi a0, t1, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x6:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x6, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x6, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x6:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x6, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x6, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x6}"(i32 %a)
   ret i32 %1
 }
@@ -344,6 +602,22 @@
 ; RV64I-NEXT:    addi a0, t1, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_t1:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x6, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x6, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_t1:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x6, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x6, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t1}"(i32 %a)
   ret i32 %1
 }
@@ -364,6 +638,22 @@
 ; RV64I-NEXT:    addi a0, t2, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x7:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x7, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x7, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x7:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x7, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x7, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x7}"(i32 %a)
   ret i32 %1
 }
@@ -384,6 +674,22 @@
 ; RV64I-NEXT:    addi a0, t2, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_t2:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x7, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x7, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_t2:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x7, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x7, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t2}"(i32 %a)
   ret i32 %1
 }
@@ -413,6 +719,30 @@
 ; RV64I-NEXT:    ld s0, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x8:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x8, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x8, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x8, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x8, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x8:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x8, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x8, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x8, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x8, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x8}"(i32 %a)
   ret i32 %1
 }
@@ -442,6 +772,30 @@
 ; RV64I-NEXT:    ld s0, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_s0:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x8, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x8, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x8, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x8, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_s0:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x8, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x8, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x8, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x8, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s0}"(i32 %a)
   ret i32 %1
 }
@@ -471,6 +825,30 @@
 ; RV64I-NEXT:    ld s0, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_fp:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x8, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x8, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x8, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x8, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_fp:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x8, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x8, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x8, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x8, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{fp}"(i32 %a)
   ret i32 %1
 }
@@ -500,6 +878,30 @@
 ; RV64I-NEXT:    ld s1, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x9:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x9, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x9, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x9, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x9, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x9:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x9, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x9, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x9, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x9, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x9}"(i32 %a)
   ret i32 %1
 }
@@ -529,6 +931,30 @@
 ; RV64I-NEXT:    ld s1, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_s1:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x9, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x9, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x9, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x9, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_s1:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x9, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x9, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x9, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x9, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s1}"(i32 %a)
   ret i32 %1
 }
@@ -547,6 +973,20 @@
 ; RV64I-NEXT:    addi a0, a0, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x10:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x10, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x10:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x10, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x10}"(i32 %a)
   ret i32 %1
 }
@@ -565,6 +1005,20 @@
 ; RV64I-NEXT:    addi a0, a0, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_a0:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x10, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_a0:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x10, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a0}"(i32 %a)
   ret i32 %1
 }
@@ -585,6 +1039,22 @@
 ; RV64I-NEXT:    addi a0, a1, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x11:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x11, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x11, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x11:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x11, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x11, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x11}"(i32 %a)
   ret i32 %1
 }
@@ -605,6 +1075,22 @@
 ; RV64I-NEXT:    addi a0, a1, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_a1:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x11, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x11, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_a1:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x11, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x11, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a1}"(i32 %a)
   ret i32 %1
 }
@@ -625,6 +1111,22 @@
 ; RV64I-NEXT:    addi a0, a2, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x12:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x12, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x12, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x12:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x12, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x12, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x12}"(i32 %a)
   ret i32 %1
 }
@@ -645,6 +1147,22 @@
 ; RV64I-NEXT:    addi a0, a2, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_a2:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x12, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x12, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_a2:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x12, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x12, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a2}"(i32 %a)
   ret i32 %1
 }
@@ -665,6 +1183,22 @@
 ; RV64I-NEXT:    addi a0, a3, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x13:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x13, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x13, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x13:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x13, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x13, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x13}"(i32 %a)
   ret i32 %1
 }
@@ -685,6 +1219,22 @@
 ; RV64I-NEXT:    addi a0, a3, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_a3:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x13, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x13, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_a3:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x13, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x13, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a3}"(i32 %a)
   ret i32 %1
 }
@@ -705,6 +1255,22 @@
 ; RV64I-NEXT:    addi a0, a4, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x14:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x14, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x14, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x14:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x14, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x14, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x14}"(i32 %a)
   ret i32 %1
 }
@@ -725,6 +1291,22 @@
 ; RV64I-NEXT:    addi a0, a4, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_a4:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x14, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x14, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_a4:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x14, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x14, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a4}"(i32 %a)
   ret i32 %1
 }
@@ -745,6 +1327,22 @@
 ; RV64I-NEXT:    addi a0, a5, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x15:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x15, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x15, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x15:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x15, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x15, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x15}"(i32 %a)
   ret i32 %1
 }
@@ -765,6 +1363,22 @@
 ; RV64I-NEXT:    addi a0, a5, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_a5:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x15, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x15, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_a5:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x15, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x15, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a5}"(i32 %a)
   ret i32 %1
 }
@@ -785,6 +1399,22 @@
 ; RV64I-NEXT:    addi a0, a6, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x16:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x16, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x16, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x16:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x16, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x16, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x16}"(i32 %a)
   ret i32 %1
 }
@@ -805,6 +1435,22 @@
 ; RV64I-NEXT:    addi a0, a6, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_a6:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x16, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x16, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_a6:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x16, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x16, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a6}"(i32 %a)
   ret i32 %1
 }
@@ -825,6 +1471,22 @@
 ; RV64I-NEXT:    addi a0, a7, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x17:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x17, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x17, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x17:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x17, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x17, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x17}"(i32 %a)
   ret i32 %1
 }
@@ -845,6 +1507,22 @@
 ; RV64I-NEXT:    addi a0, a7, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_a7:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x17, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x17, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_a7:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x17, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x17, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a7}"(i32 %a)
   ret i32 %1
 }
@@ -874,6 +1552,30 @@
 ; RV64I-NEXT:    ld s2, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x18:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x18, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x18, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x18, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x18, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x18:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x18, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x18, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x18, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x18, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x18}"(i32 %a)
   ret i32 %1
 }
@@ -903,6 +1605,30 @@
 ; RV64I-NEXT:    ld s2, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_s2:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x18, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x18, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x18, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x18, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_s2:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x18, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x18, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x18, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x18, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s2}"(i32 %a)
   ret i32 %1
 }
@@ -932,6 +1658,30 @@
 ; RV64I-NEXT:    ld s3, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x19:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x19, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x19, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x19, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x19, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x19:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x19, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x19, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x19, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x19, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x19}"(i32 %a)
   ret i32 %1
 }
@@ -961,6 +1711,30 @@
 ; RV64I-NEXT:    ld s3, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_s3:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x19, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x19, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x19, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x19, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_s3:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x19, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x19, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x19, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x19, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s3}"(i32 %a)
   ret i32 %1
 }
@@ -990,6 +1764,30 @@
 ; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x20:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x20, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x20, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x20, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x20, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x20:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x20, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x20, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x20, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x20, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x20}"(i32 %a)
   ret i32 %1
 }
@@ -1019,6 +1817,30 @@
 ; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_s4:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x20, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x20, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x20, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x20, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_s4:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x20, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x20, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x20, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x20, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s4}"(i32 %a)
   ret i32 %1
 }
@@ -1048,6 +1870,30 @@
 ; RV64I-NEXT:    ld s5, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x21:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x21, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x21, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x21, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x21, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x21:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x21, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x21, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x21, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x21, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x21}"(i32 %a)
   ret i32 %1
 }
@@ -1077,6 +1923,30 @@
 ; RV64I-NEXT:    ld s5, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_s5:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x21, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x21, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x21, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x21, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_s5:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x21, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x21, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x21, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x21, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s5}"(i32 %a)
   ret i32 %1
 }
@@ -1106,6 +1976,30 @@
 ; RV64I-NEXT:    ld s6, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x22:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x22, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x22, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x22, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x22, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x22:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x22, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x22, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x22, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x22, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x22}"(i32 %a)
   ret i32 %1
 }
@@ -1135,6 +2029,30 @@
 ; RV64I-NEXT:    ld s6, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_s6:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x22, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x22, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x22, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x22, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_s6:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x22, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x22, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x22, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x22, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s6}"(i32 %a)
   ret i32 %1
 }
@@ -1164,6 +2082,30 @@
 ; RV64I-NEXT:    ld s7, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x23:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x23, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x23, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x23, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x23, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x23:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x23, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x23, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x23, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x23, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x23}"(i32 %a)
   ret i32 %1
 }
@@ -1193,6 +2135,30 @@
 ; RV64I-NEXT:    ld s7, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_s7:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x23, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x23, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x23, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x23, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_s7:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x23, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x23, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x23, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x23, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s7}"(i32 %a)
   ret i32 %1
 }
@@ -1222,6 +2188,30 @@
 ; RV64I-NEXT:    ld s8, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x24:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x24, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x24, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x24, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x24, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x24:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x24, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x24, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x24, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x24, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x24}"(i32 %a)
   ret i32 %1
 }
@@ -1251,6 +2241,30 @@
 ; RV64I-NEXT:    ld s8, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_s8:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x24, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x24, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x24, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x24, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_s8:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x24, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x24, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x24, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x24, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s8}"(i32 %a)
   ret i32 %1
 }
@@ -1280,6 +2294,30 @@
 ; RV64I-NEXT:    ld s9, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x25:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x25, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x25, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x25, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x25, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x25:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x25, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x25, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x25, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x25, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x25}"(i32 %a)
   ret i32 %1
 }
@@ -1309,6 +2347,30 @@
 ; RV64I-NEXT:    ld s9, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_s9:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x25, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x25, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x25, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x25, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_s9:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x25, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x25, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x25, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x25, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s9}"(i32 %a)
   ret i32 %1
 }
@@ -1338,6 +2400,30 @@
 ; RV64I-NEXT:    ld s10, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x26:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x26, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x26, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x26, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x26, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x26:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x26, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x26, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x26, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x26, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x26}"(i32 %a)
   ret i32 %1
 }
@@ -1367,6 +2453,30 @@
 ; RV64I-NEXT:    ld s10, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_s10:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x26, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x26, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x26, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x26, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_s10:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x26, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x26, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x26, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x26, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s10}"(i32 %a)
   ret i32 %1
 }
@@ -1396,6 +2506,30 @@
 ; RV64I-NEXT:    ld s11, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x27:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x27, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x27, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x27, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x27, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x27:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x27, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x27, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x27, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x27, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x27}"(i32 %a)
   ret i32 %1
 }
@@ -1425,6 +2559,30 @@
 ; RV64I-NEXT:    ld s11, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_s11:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32I-NO-ABI-NEXT:    sw x27, 12(x2)
+; RV32I-NO-ABI-NEXT:    mv x27, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x27, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    lw x27, 12(x2)
+; RV32I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_s11:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64I-NO-ABI-NEXT:    sd x27, 8(x2)
+; RV64I-NO-ABI-NEXT:    mv x27, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x27, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ld x27, 8(x2)
+; RV64I-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s11}"(i32 %a)
   ret i32 %1
 }
@@ -1445,6 +2603,22 @@
 ; RV64I-NEXT:    addi a0, t3, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x28:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x28, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x28, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x28:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x28, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x28, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x28}"(i32 %a)
   ret i32 %1
 }
@@ -1465,6 +2639,22 @@
 ; RV64I-NEXT:    addi a0, t3, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_t3:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x28, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x28, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_t3:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x28, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x28, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t3}"(i32 %a)
   ret i32 %1
 }
@@ -1485,6 +2675,22 @@
 ; RV64I-NEXT:    addi a0, t4, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x29:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x29, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x29, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x29:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x29, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x29, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x29}"(i32 %a)
   ret i32 %1
 }
@@ -1505,6 +2711,22 @@
 ; RV64I-NEXT:    addi a0, t4, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_t4:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x29, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x29, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_t4:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x29, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x29, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t4}"(i32 %a)
   ret i32 %1
 }
@@ -1525,6 +2747,22 @@
 ; RV64I-NEXT:    addi a0, t5, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x30:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x30, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x30, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x30:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x30, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x30, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x30}"(i32 %a)
   ret i32 %1
 }
@@ -1545,6 +2783,22 @@
 ; RV64I-NEXT:    addi a0, t5, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_t5:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x30, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x30, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_t5:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x30, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x30, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t5}"(i32 %a)
   ret i32 %1
 }
@@ -1565,6 +2819,22 @@
 ; RV64I-NEXT:    addi a0, t6, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_x31:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x31, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x31, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_x31:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x31, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x31, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x31}"(i32 %a)
   ret i32 %1
 }
@@ -1585,6 +2855,22 @@
 ; RV64I-NEXT:    addi a0, t6, 0
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
+;
+; RV32I-NO-ABI-LABEL: explicit_register_t6:
+; RV32I-NO-ABI:       # %bb.0:
+; RV32I-NO-ABI-NEXT:    mv x31, x10
+; RV32I-NO-ABI-NEXT:    #APP
+; RV32I-NO-ABI-NEXT:    addi x10, x31, 0
+; RV32I-NO-ABI-NEXT:    #NO_APP
+; RV32I-NO-ABI-NEXT:    ret
+;
+; RV64I-NO-ABI-LABEL: explicit_register_t6:
+; RV64I-NO-ABI:       # %bb.0:
+; RV64I-NO-ABI-NEXT:    mv x31, x10
+; RV64I-NO-ABI-NEXT:    #APP
+; RV64I-NO-ABI-NEXT:    addi x10, x31, 0
+; RV64I-NO-ABI-NEXT:    #NO_APP
+; RV64I-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t6}"(i32 %a)
   ret i32 %1
 }
diff --git a/llvm/test/CodeGen/RISCV/inline-asm-d-abi-names.ll b/llvm/test/CodeGen/RISCV/inline-asm-d-abi-names.ll
--- a/llvm/test/CodeGen/RISCV/inline-asm-d-abi-names.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm-d-abi-names.ll
@@ -3,6 +3,10 @@
 ; RUN:   | FileCheck -check-prefix=RV32IFD %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f,+d -target-abi lp64d -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64IFD %s
+; RUN: llc -mtriple=riscv32 -mattr=+f,+d -target-abi ilp32d -verify-machineinstrs -riscv-arch-reg-names < %s \
+; RUN:   | FileCheck -check-prefix=RV32IFD-NO-ABI %s
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d -target-abi lp64d -verify-machineinstrs -riscv-arch-reg-names < %s \
+; RUN:   | FileCheck -check-prefix=RV64IFD-NO-ABI %s
 
 ; These test that we can use both the architectural names (x*) and the ABI names
 ; (a*, s*, t* etc) to refer to registers in inline asm constraint lists. In each
@@ -10,7 +14,9 @@
 ; It is very likely that `a0` will be chosen as the designation register, but
 ; this is left to the compiler to choose.
 ;
-; The inline assembly will, by default, contain the ABI names for the registers.
+; The inline assembly will, by default, contain the ABI names for the registers,
+; unless `-riscv-arch-reg-names` is passed to llc to print the architectural
+; names.
 ;
 ; Parenthesised registers in comments are the other aliases for this register.
 
@@ -31,6 +37,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, ft0
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f0:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f0, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f0
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f0:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f0, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f0
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f0}"(double %a)
   ret i32 %1
 }
@@ -51,6 +73,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, ft0
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_ft0:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f0, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f0
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_ft0:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f0, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f0
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft0}"(double %a)
   ret i32 %1
 }
@@ -71,6 +109,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, ft1
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f1:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f1, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f1
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f1:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f1, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f1
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f1}"(double %a)
   ret i32 %1
 }
@@ -91,6 +145,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, ft1
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_ft1:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f1, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f1
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_ft1:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f1, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f1
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft1}"(double %a)
   ret i32 %1
 }
@@ -111,6 +181,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, ft2
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f2:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f2, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f2
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f2:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f2, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f2
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f2}"(double %a)
   ret i32 %1
 }
@@ -131,6 +217,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, ft2
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_ft2:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f2, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f2
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_ft2:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f2, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f2
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft2}"(double %a)
   ret i32 %1
 }
@@ -151,6 +253,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, ft3
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f3:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f3, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f3
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f3:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f3, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f3
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f3}"(double %a)
   ret i32 %1
 }
@@ -171,6 +289,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, ft3
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_ft3:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f3, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f3
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_ft3:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f3, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f3
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft3}"(double %a)
   ret i32 %1
 }
@@ -191,6 +325,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, ft4
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f4:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f4, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f4
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f4:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f4, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f4
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f4}"(double %a)
   ret i32 %1
 }
@@ -211,6 +361,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, ft4
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_ft4:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f4, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f4
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_ft4:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f4, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f4
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft4}"(double %a)
   ret i32 %1
 }
@@ -231,6 +397,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, ft5
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f5:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f5, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f5
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f5:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f5, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f5
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f5}"(double %a)
   ret i32 %1
 }
@@ -251,6 +433,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, ft5
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_ft5:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f5, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f5
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_ft5:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f5, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f5
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft5}"(double %a)
   ret i32 %1
 }
@@ -271,6 +469,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, ft6
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f6:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f6, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f6
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f6:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f6, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f6
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f6}"(double %a)
   ret i32 %1
 }
@@ -291,6 +505,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, ft6
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_ft6:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f6, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f6
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_ft6:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f6, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f6
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft6}"(double %a)
   ret i32 %1
 }
@@ -311,6 +541,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, ft7
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f7:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f7, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f7
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f7:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f7, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f7
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f7}"(double %a)
   ret i32 %1
 }
@@ -331,6 +577,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, ft7
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_ft7:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f7, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f7
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_ft7:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f7, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f7
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft7}"(double %a)
   ret i32 %1
 }
@@ -361,6 +623,30 @@
 ; RV64IFD-NEXT:    fld fs0, 8(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 16
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f8:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IFD-NO-ABI-NEXT:    fsd f8, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    fmv.d f8, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f8
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    fld f8, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f8:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IFD-NO-ABI-NEXT:    fsd f8, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    fmv.d f8, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f8
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    fld f8, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f8}"(double %a)
   ret i32 %1
 }
@@ -390,6 +676,30 @@
 ; RV64IFD-NEXT:    fld fs0, 8(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 16
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_fs0:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IFD-NO-ABI-NEXT:    fsd f8, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    fmv.d f8, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f8
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    fld f8, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_fs0:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IFD-NO-ABI-NEXT:    fsd f8, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    fmv.d f8, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f8
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    fld f8, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs0}"(double %a)
   ret i32 %1
 }
@@ -419,6 +729,30 @@
 ; RV64IFD-NEXT:    fld fs1, 8(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 16
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f9:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IFD-NO-ABI-NEXT:    fsd f9, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    fmv.d f9, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f9
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    fld f9, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f9:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IFD-NO-ABI-NEXT:    fsd f9, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    fmv.d f9, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f9
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    fld f9, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f9}"(double %a)
   ret i32 %1
 }
@@ -448,6 +782,30 @@
 ; RV64IFD-NEXT:    fld fs1, 8(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 16
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_fs1:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IFD-NO-ABI-NEXT:    fsd f9, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    fmv.d f9, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f9
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    fld f9, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_fs1:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IFD-NO-ABI-NEXT:    fsd f9, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    fmv.d f9, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f9
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    fld f9, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs1}"(double %a)
   ret i32 %1
 }
@@ -466,6 +824,20 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, fa0
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f10:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f10
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f10:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f10
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f10}"(double %a)
   ret i32 %1
 }
@@ -484,6 +856,20 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, fa0
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_fa0:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f10
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_fa0:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f10
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fa0}"(double %a)
   ret i32 %1
 }
@@ -504,6 +890,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, fa1
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f11:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f11, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f11
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f11:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f11, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f11
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f11}"(double %a)
   ret i32 %1
 }
@@ -524,6 +926,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, fa1
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_fa1:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f11, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f11
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_fa1:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f11, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f11
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fa1}"(double %a)
   ret i32 %1
 }
@@ -544,6 +962,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, fa2
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f12:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f12, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f12
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f12:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f12, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f12
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f12}"(double %a)
   ret i32 %1
 }
@@ -564,6 +998,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, fa2
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_fa2:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f12, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f12
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_fa2:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f12, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f12
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fa2}"(double %a)
   ret i32 %1
 }
@@ -584,6 +1034,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, fa3
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f13:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f13, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f13
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f13:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f13, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f13
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f13}"(double %a)
   ret i32 %1
 }
@@ -604,6 +1070,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, fa3
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_fa3:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f13, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f13
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_fa3:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f13, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f13
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fa3}"(double %a)
   ret i32 %1
 }
@@ -624,6 +1106,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, fa4
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f14:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f14, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f14
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f14:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f14, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f14
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f14}"(double %a)
   ret i32 %1
 }
@@ -644,6 +1142,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, fa4
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_fa4:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f14, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f14
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_fa4:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f14, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f14
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fa4}"(double %a)
   ret i32 %1
 }
@@ -664,6 +1178,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, fa5
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f15:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f15, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f15
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f15:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f15, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f15
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f15}"(double %a)
   ret i32 %1
 }
@@ -684,6 +1214,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, fa5
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_fa5:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f15, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f15
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_fa5:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f15, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f15
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fa5}"(double %a)
   ret i32 %1
 }
@@ -704,6 +1250,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, fa6
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f16:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f16, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f16
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f16:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f16, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f16
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f16}"(double %a)
   ret i32 %1
 }
@@ -724,6 +1286,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, fa6
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_fa6:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f16, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f16
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_fa6:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f16, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f16
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fa6}"(double %a)
   ret i32 %1
 }
@@ -744,6 +1322,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, fa7
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f17:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f17, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f17
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f17:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f17, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f17
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f17}"(double %a)
   ret i32 %1
 }
@@ -764,6 +1358,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, fa7
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_fa7:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f17, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f17
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_fa7:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f17, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f17
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fa7}"(double %a)
   ret i32 %1
 }
@@ -793,6 +1403,30 @@
 ; RV64IFD-NEXT:    fld fs2, 8(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 16
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f18:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IFD-NO-ABI-NEXT:    fsd f18, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    fmv.d f18, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f18
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    fld f18, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f18:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IFD-NO-ABI-NEXT:    fsd f18, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    fmv.d f18, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f18
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    fld f18, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f18}"(double %a)
   ret i32 %1
 }
@@ -822,6 +1456,30 @@
 ; RV64IFD-NEXT:    fld fs2, 8(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 16
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_fs2:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IFD-NO-ABI-NEXT:    fsd f18, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    fmv.d f18, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f18
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    fld f18, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_fs2:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IFD-NO-ABI-NEXT:    fsd f18, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    fmv.d f18, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f18
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    fld f18, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs2}"(double %a)
   ret i32 %1
 }
@@ -851,6 +1509,30 @@
 ; RV64IFD-NEXT:    fld fs3, 8(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 16
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f19:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IFD-NO-ABI-NEXT:    fsd f19, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    fmv.d f19, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f19
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    fld f19, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f19:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IFD-NO-ABI-NEXT:    fsd f19, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    fmv.d f19, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f19
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    fld f19, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f19}"(double %a)
   ret i32 %1
 }
@@ -880,6 +1562,30 @@
 ; RV64IFD-NEXT:    fld fs3, 8(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 16
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_fs3:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IFD-NO-ABI-NEXT:    fsd f19, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    fmv.d f19, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f19
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    fld f19, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_fs3:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IFD-NO-ABI-NEXT:    fsd f19, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    fmv.d f19, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f19
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    fld f19, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs3}"(double %a)
   ret i32 %1
 }
@@ -909,6 +1615,30 @@
 ; RV64IFD-NEXT:    fld fs4, 8(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 16
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f20:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IFD-NO-ABI-NEXT:    fsd f20, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    fmv.d f20, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f20
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    fld f20, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f20:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IFD-NO-ABI-NEXT:    fsd f20, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    fmv.d f20, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f20
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    fld f20, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f20}"(double %a)
   ret i32 %1
 }
@@ -938,6 +1668,30 @@
 ; RV64IFD-NEXT:    fld fs4, 8(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 16
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_fs4:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IFD-NO-ABI-NEXT:    fsd f20, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    fmv.d f20, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f20
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    fld f20, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_fs4:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IFD-NO-ABI-NEXT:    fsd f20, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    fmv.d f20, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f20
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    fld f20, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs4}"(double %a)
   ret i32 %1
 }
@@ -967,6 +1721,30 @@
 ; RV64IFD-NEXT:    fld fs5, 8(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 16
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f21:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IFD-NO-ABI-NEXT:    fsd f21, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    fmv.d f21, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f21
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    fld f21, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f21:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IFD-NO-ABI-NEXT:    fsd f21, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    fmv.d f21, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f21
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    fld f21, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f21}"(double %a)
   ret i32 %1
 }
@@ -996,6 +1774,30 @@
 ; RV64IFD-NEXT:    fld fs5, 8(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 16
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_fs5:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IFD-NO-ABI-NEXT:    fsd f21, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    fmv.d f21, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f21
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    fld f21, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_fs5:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IFD-NO-ABI-NEXT:    fsd f21, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    fmv.d f21, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f21
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    fld f21, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs5}"(double %a)
   ret i32 %1
 }
@@ -1025,6 +1827,30 @@
 ; RV64IFD-NEXT:    fld fs6, 8(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 16
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f22:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IFD-NO-ABI-NEXT:    fsd f22, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    fmv.d f22, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f22
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    fld f22, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f22:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IFD-NO-ABI-NEXT:    fsd f22, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    fmv.d f22, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f22
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    fld f22, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f22}"(double %a)
   ret i32 %1
 }
@@ -1054,6 +1880,30 @@
 ; RV64IFD-NEXT:    fld fs6, 8(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 16
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_fs6:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IFD-NO-ABI-NEXT:    fsd f22, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    fmv.d f22, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f22
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    fld f22, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_fs6:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IFD-NO-ABI-NEXT:    fsd f22, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    fmv.d f22, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f22
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    fld f22, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs6}"(double %a)
   ret i32 %1
 }
@@ -1083,6 +1933,30 @@
 ; RV64IFD-NEXT:    fld fs7, 8(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 16
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f23:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IFD-NO-ABI-NEXT:    fsd f23, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    fmv.d f23, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f23
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    fld f23, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f23:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IFD-NO-ABI-NEXT:    fsd f23, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    fmv.d f23, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f23
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    fld f23, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f23}"(double %a)
   ret i32 %1
 }
@@ -1112,6 +1986,30 @@
 ; RV64IFD-NEXT:    fld fs7, 8(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 16
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_fs7:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IFD-NO-ABI-NEXT:    fsd f23, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    fmv.d f23, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f23
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    fld f23, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_fs7:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IFD-NO-ABI-NEXT:    fsd f23, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    fmv.d f23, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f23
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    fld f23, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs7}"(double %a)
   ret i32 %1
 }
@@ -1141,6 +2039,30 @@
 ; RV64IFD-NEXT:    fld fs8, 8(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 16
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f24:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IFD-NO-ABI-NEXT:    fsd f24, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    fmv.d f24, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f24
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    fld f24, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f24:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IFD-NO-ABI-NEXT:    fsd f24, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    fmv.d f24, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f24
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    fld f24, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f24}"(double %a)
   ret i32 %1
 }
@@ -1170,6 +2092,30 @@
 ; RV64IFD-NEXT:    fld fs8, 8(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 16
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_fs8:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IFD-NO-ABI-NEXT:    fsd f24, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    fmv.d f24, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f24
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    fld f24, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_fs8:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IFD-NO-ABI-NEXT:    fsd f24, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    fmv.d f24, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f24
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    fld f24, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs8}"(double %a)
   ret i32 %1
 }
@@ -1199,6 +2145,30 @@
 ; RV64IFD-NEXT:    fld fs9, 8(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 16
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f25:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IFD-NO-ABI-NEXT:    fsd f25, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    fmv.d f25, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f25
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    fld f25, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f25:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IFD-NO-ABI-NEXT:    fsd f25, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    fmv.d f25, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f25
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    fld f25, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f25}"(double %a)
   ret i32 %1
 }
@@ -1228,6 +2198,30 @@
 ; RV64IFD-NEXT:    fld fs9, 8(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 16
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_fs9:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IFD-NO-ABI-NEXT:    fsd f25, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    fmv.d f25, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f25
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    fld f25, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_fs9:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IFD-NO-ABI-NEXT:    fsd f25, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    fmv.d f25, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f25
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    fld f25, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs9}"(double %a)
   ret i32 %1
 }
@@ -1257,6 +2251,30 @@
 ; RV64IFD-NEXT:    fld fs10, 8(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 16
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f26:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IFD-NO-ABI-NEXT:    fsd f26, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    fmv.d f26, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f26
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    fld f26, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f26:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IFD-NO-ABI-NEXT:    fsd f26, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    fmv.d f26, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f26
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    fld f26, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f26}"(double %a)
   ret i32 %1
 }
@@ -1286,6 +2304,30 @@
 ; RV64IFD-NEXT:    fld fs10, 8(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 16
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_fs10:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IFD-NO-ABI-NEXT:    fsd f26, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    fmv.d f26, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f26
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    fld f26, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_fs10:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IFD-NO-ABI-NEXT:    fsd f26, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    fmv.d f26, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f26
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    fld f26, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs10}"(double %a)
   ret i32 %1
 }
@@ -1315,6 +2357,30 @@
 ; RV64IFD-NEXT:    fld fs11, 8(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 16
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f27:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IFD-NO-ABI-NEXT:    fsd f27, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    fmv.d f27, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f27
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    fld f27, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f27:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IFD-NO-ABI-NEXT:    fsd f27, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    fmv.d f27, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f27
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    fld f27, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f27}"(double %a)
   ret i32 %1
 }
@@ -1344,6 +2410,30 @@
 ; RV64IFD-NEXT:    fld fs11, 8(sp)
 ; RV64IFD-NEXT:    addi sp, sp, 16
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_fs11:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IFD-NO-ABI-NEXT:    fsd f27, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    fmv.d f27, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f27
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    fld f27, 8(x2)
+; RV32IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_fs11:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IFD-NO-ABI-NEXT:    fsd f27, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    fmv.d f27, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f27
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    fld f27, 8(x2)
+; RV64IFD-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs11}"(double %a)
   ret i32 %1
 }
@@ -1364,6 +2454,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, ft8
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f28:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f28, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f28
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f28:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f28, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f28
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f28}"(double %a)
   ret i32 %1
 }
@@ -1384,6 +2490,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, ft8
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_ft8:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f28, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f28
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_ft8:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f28, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f28
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft8}"(double %a)
   ret i32 %1
 }
@@ -1404,6 +2526,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, ft9
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f29:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f29, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f29
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f29:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f29, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f29
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f29}"(double %a)
   ret i32 %1
 }
@@ -1424,6 +2562,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, ft9
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_ft9:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f29, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f29
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_ft9:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f29, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f29
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft9}"(double %a)
   ret i32 %1
 }
@@ -1444,6 +2598,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, ft10
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f30:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f30, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f30
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f30:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f30, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f30
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f30}"(double %a)
   ret i32 %1
 }
@@ -1464,6 +2634,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, ft10
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_ft10:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f30, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f30
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_ft10:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f30, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f30
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft10}"(double %a)
   ret i32 %1
 }
@@ -1484,6 +2670,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, ft11
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_f31:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f31, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f31
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_f31:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f31, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f31
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f31}"(double %a)
   ret i32 %1
 }
@@ -1504,6 +2706,22 @@
 ; RV64IFD-NEXT:    fcvt.w.d a0, ft11
 ; RV64IFD-NEXT:    #NO_APP
 ; RV64IFD-NEXT:    ret
+;
+; RV32IFD-NO-ABI-LABEL: explicit_register_ft11:
+; RV32IFD-NO-ABI:       # %bb.0:
+; RV32IFD-NO-ABI-NEXT:    fmv.d f31, f10
+; RV32IFD-NO-ABI-NEXT:    #APP
+; RV32IFD-NO-ABI-NEXT:    fcvt.w.d x10, f31
+; RV32IFD-NO-ABI-NEXT:    #NO_APP
+; RV32IFD-NO-ABI-NEXT:    ret
+;
+; RV64IFD-NO-ABI-LABEL: explicit_register_ft11:
+; RV64IFD-NO-ABI:       # %bb.0:
+; RV64IFD-NO-ABI-NEXT:    fmv.d f31, f10
+; RV64IFD-NO-ABI-NEXT:    #APP
+; RV64IFD-NO-ABI-NEXT:    fcvt.w.d x10, f31
+; RV64IFD-NO-ABI-NEXT:    #NO_APP
+; RV64IFD-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft11}"(double %a)
   ret i32 %1
 }
diff --git a/llvm/test/CodeGen/RISCV/inline-asm-f-abi-names.ll b/llvm/test/CodeGen/RISCV/inline-asm-f-abi-names.ll
--- a/llvm/test/CodeGen/RISCV/inline-asm-f-abi-names.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm-f-abi-names.ll
@@ -3,6 +3,10 @@
 ; RUN:   | FileCheck -check-prefix=RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64IF %s
+; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs -riscv-arch-reg-names < %s \
+; RUN:   | FileCheck -check-prefix=RV32IF-NO-ABI %s
+; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs -riscv-arch-reg-names < %s \
+; RUN:   | FileCheck -check-prefix=RV64IF-NO-ABI %s
 
 ; These test that we can use both the architectural names (x*) and the ABI names
 ; (a*, s*, t* etc) to refer to registers in inline asm constraint lists. In each
@@ -10,7 +14,9 @@
 ; It is very likely that `a0` will be chosen as the designation register, but
 ; this is left to the compiler to choose.
 ;
-; The inline assembly will, by default, contain the ABI names for the registers.
+; The inline assembly will, by default, contain the ABI names for the registers,
+; unless `-riscv-arch-reg-names` is passed to llc to print the architectural
+; names.
 ;
 ; Parenthesised registers in comments are the other aliases for this register.
 
@@ -31,6 +37,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, ft0
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f0:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f0, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f0
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f0:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f0, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f0
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f0}"(float %a)
   ret i32 %1
 }
@@ -51,6 +73,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, ft0
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_ft0:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f0, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f0
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_ft0:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f0, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f0
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft0}"(float %a)
   ret i32 %1
 }
@@ -71,6 +109,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, ft1
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f1:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f1, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f1
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f1:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f1, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f1
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f1}"(float %a)
   ret i32 %1
 }
@@ -91,6 +145,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, ft1
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_ft1:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f1, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f1
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_ft1:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f1, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f1
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft1}"(float %a)
   ret i32 %1
 }
@@ -111,6 +181,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, ft2
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f2:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f2, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f2
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f2:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f2, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f2
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f2}"(float %a)
   ret i32 %1
 }
@@ -131,6 +217,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, ft2
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_ft2:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f2, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f2
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_ft2:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f2, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f2
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft2}"(float %a)
   ret i32 %1
 }
@@ -151,6 +253,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, ft3
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f3:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f3, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f3
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f3:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f3, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f3
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f3}"(float %a)
   ret i32 %1
 }
@@ -171,6 +289,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, ft3
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_ft3:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f3, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f3
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_ft3:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f3, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f3
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft3}"(float %a)
   ret i32 %1
 }
@@ -191,6 +325,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, ft4
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f4:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f4, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f4
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f4:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f4, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f4
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f4}"(float %a)
   ret i32 %1
 }
@@ -211,6 +361,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, ft4
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_ft4:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f4, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f4
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_ft4:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f4, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f4
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft4}"(float %a)
   ret i32 %1
 }
@@ -231,6 +397,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, ft5
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f5:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f5, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f5
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f5:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f5, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f5
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f5}"(float %a)
   ret i32 %1
 }
@@ -251,6 +433,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, ft5
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_ft5:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f5, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f5
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_ft5:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f5, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f5
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft5}"(float %a)
   ret i32 %1
 }
@@ -271,6 +469,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, ft6
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f6:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f6, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f6
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f6:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f6, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f6
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f6}"(float %a)
   ret i32 %1
 }
@@ -291,6 +505,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, ft6
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_ft6:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f6, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f6
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_ft6:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f6, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f6
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft6}"(float %a)
   ret i32 %1
 }
@@ -311,6 +541,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, ft7
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f7:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f7, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f7
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f7:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f7, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f7
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f7}"(float %a)
   ret i32 %1
 }
@@ -331,6 +577,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, ft7
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_ft7:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f7, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f7
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_ft7:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f7, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f7
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft7}"(float %a)
   ret i32 %1
 }
@@ -361,6 +623,30 @@
 ; RV64IF-NEXT:    flw fs0, 12(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f8:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IF-NO-ABI-NEXT:    fsw f8, 12(x2)
+; RV32IF-NO-ABI-NEXT:    fmv.s f8, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f8
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    flw f8, 12(x2)
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f8:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IF-NO-ABI-NEXT:    fsw f8, 12(x2)
+; RV64IF-NO-ABI-NEXT:    fmv.s f8, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f8
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    flw f8, 12(x2)
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f8}"(float %a)
   ret i32 %1
 }
@@ -390,6 +676,30 @@
 ; RV64IF-NEXT:    flw fs0, 12(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_fs0:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IF-NO-ABI-NEXT:    fsw f8, 12(x2)
+; RV32IF-NO-ABI-NEXT:    fmv.s f8, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f8
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    flw f8, 12(x2)
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_fs0:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IF-NO-ABI-NEXT:    fsw f8, 12(x2)
+; RV64IF-NO-ABI-NEXT:    fmv.s f8, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f8
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    flw f8, 12(x2)
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs0}"(float %a)
   ret i32 %1
 }
@@ -419,6 +729,30 @@
 ; RV64IF-NEXT:    flw fs1, 12(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f9:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IF-NO-ABI-NEXT:    fsw f9, 12(x2)
+; RV32IF-NO-ABI-NEXT:    fmv.s f9, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f9
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    flw f9, 12(x2)
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f9:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IF-NO-ABI-NEXT:    fsw f9, 12(x2)
+; RV64IF-NO-ABI-NEXT:    fmv.s f9, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f9
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    flw f9, 12(x2)
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f9}"(float %a)
   ret i32 %1
 }
@@ -448,6 +782,30 @@
 ; RV64IF-NEXT:    flw fs1, 12(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_fs1:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IF-NO-ABI-NEXT:    fsw f9, 12(x2)
+; RV32IF-NO-ABI-NEXT:    fmv.s f9, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f9
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    flw f9, 12(x2)
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_fs1:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IF-NO-ABI-NEXT:    fsw f9, 12(x2)
+; RV64IF-NO-ABI-NEXT:    fmv.s f9, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f9
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    flw f9, 12(x2)
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs1}"(float %a)
   ret i32 %1
 }
@@ -466,6 +824,20 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, fa0
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f10:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f10
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f10:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f10
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f10}"(float %a)
   ret i32 %1
 }
@@ -484,6 +856,20 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, fa0
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_fa0:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f10
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_fa0:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f10
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa0}"(float %a)
   ret i32 %1
 }
@@ -504,6 +890,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, fa1
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f11:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f11, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f11
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f11:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f11, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f11
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f11}"(float %a)
   ret i32 %1
 }
@@ -524,6 +926,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, fa1
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_fa1:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f11, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f11
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_fa1:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f11, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f11
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa1}"(float %a)
   ret i32 %1
 }
@@ -544,6 +962,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, fa2
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f12:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f12, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f12
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f12:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f12, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f12
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f12}"(float %a)
   ret i32 %1
 }
@@ -564,6 +998,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, fa2
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_fa2:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f12, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f12
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_fa2:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f12, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f12
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa2}"(float %a)
   ret i32 %1
 }
@@ -584,6 +1034,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, fa3
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f13:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f13, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f13
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f13:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f13, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f13
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f13}"(float %a)
   ret i32 %1
 }
@@ -604,6 +1070,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, fa3
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_fa3:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f13, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f13
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_fa3:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f13, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f13
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa3}"(float %a)
   ret i32 %1
 }
@@ -624,6 +1106,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, fa4
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f14:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f14, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f14
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f14:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f14, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f14
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f14}"(float %a)
   ret i32 %1
 }
@@ -644,6 +1142,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, fa4
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_fa4:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f14, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f14
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_fa4:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f14, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f14
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa4}"(float %a)
   ret i32 %1
 }
@@ -664,6 +1178,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, fa5
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f15:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f15, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f15
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f15:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f15, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f15
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f15}"(float %a)
   ret i32 %1
 }
@@ -684,6 +1214,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, fa5
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_fa5:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f15, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f15
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_fa5:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f15, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f15
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa5}"(float %a)
   ret i32 %1
 }
@@ -704,6 +1250,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, fa6
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f16:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f16, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f16
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f16:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f16, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f16
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f16}"(float %a)
   ret i32 %1
 }
@@ -724,6 +1286,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, fa6
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_fa6:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f16, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f16
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_fa6:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f16, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f16
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa6}"(float %a)
   ret i32 %1
 }
@@ -744,6 +1322,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, fa7
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f17:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f17, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f17
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f17:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f17, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f17
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f17}"(float %a)
   ret i32 %1
 }
@@ -764,6 +1358,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, fa7
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_fa7:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f17, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f17
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_fa7:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f17, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f17
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa7}"(float %a)
   ret i32 %1
 }
@@ -793,6 +1403,30 @@
 ; RV64IF-NEXT:    flw fs2, 12(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f18:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IF-NO-ABI-NEXT:    fsw f18, 12(x2)
+; RV32IF-NO-ABI-NEXT:    fmv.s f18, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f18
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    flw f18, 12(x2)
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f18:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IF-NO-ABI-NEXT:    fsw f18, 12(x2)
+; RV64IF-NO-ABI-NEXT:    fmv.s f18, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f18
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    flw f18, 12(x2)
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f18}"(float %a)
   ret i32 %1
 }
@@ -822,6 +1456,30 @@
 ; RV64IF-NEXT:    flw fs2, 12(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_fs2:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IF-NO-ABI-NEXT:    fsw f18, 12(x2)
+; RV32IF-NO-ABI-NEXT:    fmv.s f18, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f18
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    flw f18, 12(x2)
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_fs2:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IF-NO-ABI-NEXT:    fsw f18, 12(x2)
+; RV64IF-NO-ABI-NEXT:    fmv.s f18, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f18
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    flw f18, 12(x2)
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs2}"(float %a)
   ret i32 %1
 }
@@ -851,6 +1509,30 @@
 ; RV64IF-NEXT:    flw fs3, 12(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f19:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IF-NO-ABI-NEXT:    fsw f19, 12(x2)
+; RV32IF-NO-ABI-NEXT:    fmv.s f19, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f19
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    flw f19, 12(x2)
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f19:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IF-NO-ABI-NEXT:    fsw f19, 12(x2)
+; RV64IF-NO-ABI-NEXT:    fmv.s f19, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f19
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    flw f19, 12(x2)
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f19}"(float %a)
   ret i32 %1
 }
@@ -880,6 +1562,30 @@
 ; RV64IF-NEXT:    flw fs3, 12(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_fs3:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IF-NO-ABI-NEXT:    fsw f19, 12(x2)
+; RV32IF-NO-ABI-NEXT:    fmv.s f19, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f19
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    flw f19, 12(x2)
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_fs3:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IF-NO-ABI-NEXT:    fsw f19, 12(x2)
+; RV64IF-NO-ABI-NEXT:    fmv.s f19, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f19
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    flw f19, 12(x2)
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs3}"(float %a)
   ret i32 %1
 }
@@ -909,6 +1615,30 @@
 ; RV64IF-NEXT:    flw fs4, 12(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f20:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IF-NO-ABI-NEXT:    fsw f20, 12(x2)
+; RV32IF-NO-ABI-NEXT:    fmv.s f20, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f20
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    flw f20, 12(x2)
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f20:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IF-NO-ABI-NEXT:    fsw f20, 12(x2)
+; RV64IF-NO-ABI-NEXT:    fmv.s f20, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f20
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    flw f20, 12(x2)
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f20}"(float %a)
   ret i32 %1
 }
@@ -938,6 +1668,30 @@
 ; RV64IF-NEXT:    flw fs4, 12(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_fs4:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IF-NO-ABI-NEXT:    fsw f20, 12(x2)
+; RV32IF-NO-ABI-NEXT:    fmv.s f20, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f20
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    flw f20, 12(x2)
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_fs4:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IF-NO-ABI-NEXT:    fsw f20, 12(x2)
+; RV64IF-NO-ABI-NEXT:    fmv.s f20, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f20
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    flw f20, 12(x2)
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs4}"(float %a)
   ret i32 %1
 }
@@ -967,6 +1721,30 @@
 ; RV64IF-NEXT:    flw fs5, 12(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f21:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IF-NO-ABI-NEXT:    fsw f21, 12(x2)
+; RV32IF-NO-ABI-NEXT:    fmv.s f21, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f21
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    flw f21, 12(x2)
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f21:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IF-NO-ABI-NEXT:    fsw f21, 12(x2)
+; RV64IF-NO-ABI-NEXT:    fmv.s f21, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f21
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    flw f21, 12(x2)
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f21}"(float %a)
   ret i32 %1
 }
@@ -996,6 +1774,30 @@
 ; RV64IF-NEXT:    flw fs5, 12(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_fs5:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IF-NO-ABI-NEXT:    fsw f21, 12(x2)
+; RV32IF-NO-ABI-NEXT:    fmv.s f21, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f21
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    flw f21, 12(x2)
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_fs5:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IF-NO-ABI-NEXT:    fsw f21, 12(x2)
+; RV64IF-NO-ABI-NEXT:    fmv.s f21, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f21
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    flw f21, 12(x2)
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs5}"(float %a)
   ret i32 %1
 }
@@ -1025,6 +1827,30 @@
 ; RV64IF-NEXT:    flw fs6, 12(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f22:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IF-NO-ABI-NEXT:    fsw f22, 12(x2)
+; RV32IF-NO-ABI-NEXT:    fmv.s f22, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f22
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    flw f22, 12(x2)
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f22:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IF-NO-ABI-NEXT:    fsw f22, 12(x2)
+; RV64IF-NO-ABI-NEXT:    fmv.s f22, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f22
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    flw f22, 12(x2)
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f22}"(float %a)
   ret i32 %1
 }
@@ -1054,6 +1880,30 @@
 ; RV64IF-NEXT:    flw fs6, 12(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_fs6:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IF-NO-ABI-NEXT:    fsw f22, 12(x2)
+; RV32IF-NO-ABI-NEXT:    fmv.s f22, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f22
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    flw f22, 12(x2)
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_fs6:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IF-NO-ABI-NEXT:    fsw f22, 12(x2)
+; RV64IF-NO-ABI-NEXT:    fmv.s f22, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f22
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    flw f22, 12(x2)
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs6}"(float %a)
   ret i32 %1
 }
@@ -1083,6 +1933,30 @@
 ; RV64IF-NEXT:    flw fs7, 12(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f23:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IF-NO-ABI-NEXT:    fsw f23, 12(x2)
+; RV32IF-NO-ABI-NEXT:    fmv.s f23, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f23
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    flw f23, 12(x2)
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f23:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IF-NO-ABI-NEXT:    fsw f23, 12(x2)
+; RV64IF-NO-ABI-NEXT:    fmv.s f23, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f23
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    flw f23, 12(x2)
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f23}"(float %a)
   ret i32 %1
 }
@@ -1112,6 +1986,30 @@
 ; RV64IF-NEXT:    flw fs7, 12(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_fs7:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IF-NO-ABI-NEXT:    fsw f23, 12(x2)
+; RV32IF-NO-ABI-NEXT:    fmv.s f23, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f23
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    flw f23, 12(x2)
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_fs7:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IF-NO-ABI-NEXT:    fsw f23, 12(x2)
+; RV64IF-NO-ABI-NEXT:    fmv.s f23, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f23
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    flw f23, 12(x2)
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs7}"(float %a)
   ret i32 %1
 }
@@ -1141,6 +2039,30 @@
 ; RV64IF-NEXT:    flw fs8, 12(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f24:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IF-NO-ABI-NEXT:    fsw f24, 12(x2)
+; RV32IF-NO-ABI-NEXT:    fmv.s f24, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f24
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    flw f24, 12(x2)
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f24:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IF-NO-ABI-NEXT:    fsw f24, 12(x2)
+; RV64IF-NO-ABI-NEXT:    fmv.s f24, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f24
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    flw f24, 12(x2)
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f24}"(float %a)
   ret i32 %1
 }
@@ -1170,6 +2092,30 @@
 ; RV64IF-NEXT:    flw fs8, 12(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_fs8:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IF-NO-ABI-NEXT:    fsw f24, 12(x2)
+; RV32IF-NO-ABI-NEXT:    fmv.s f24, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f24
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    flw f24, 12(x2)
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_fs8:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IF-NO-ABI-NEXT:    fsw f24, 12(x2)
+; RV64IF-NO-ABI-NEXT:    fmv.s f24, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f24
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    flw f24, 12(x2)
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs8}"(float %a)
   ret i32 %1
 }
@@ -1199,6 +2145,30 @@
 ; RV64IF-NEXT:    flw fs9, 12(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f25:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IF-NO-ABI-NEXT:    fsw f25, 12(x2)
+; RV32IF-NO-ABI-NEXT:    fmv.s f25, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f25
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    flw f25, 12(x2)
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f25:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IF-NO-ABI-NEXT:    fsw f25, 12(x2)
+; RV64IF-NO-ABI-NEXT:    fmv.s f25, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f25
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    flw f25, 12(x2)
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f25}"(float %a)
   ret i32 %1
 }
@@ -1228,6 +2198,30 @@
 ; RV64IF-NEXT:    flw fs9, 12(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_fs9:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IF-NO-ABI-NEXT:    fsw f25, 12(x2)
+; RV32IF-NO-ABI-NEXT:    fmv.s f25, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f25
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    flw f25, 12(x2)
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_fs9:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IF-NO-ABI-NEXT:    fsw f25, 12(x2)
+; RV64IF-NO-ABI-NEXT:    fmv.s f25, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f25
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    flw f25, 12(x2)
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs9}"(float %a)
   ret i32 %1
 }
@@ -1257,6 +2251,30 @@
 ; RV64IF-NEXT:    flw fs10, 12(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f26:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IF-NO-ABI-NEXT:    fsw f26, 12(x2)
+; RV32IF-NO-ABI-NEXT:    fmv.s f26, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f26
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    flw f26, 12(x2)
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f26:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IF-NO-ABI-NEXT:    fsw f26, 12(x2)
+; RV64IF-NO-ABI-NEXT:    fmv.s f26, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f26
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    flw f26, 12(x2)
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f26}"(float %a)
   ret i32 %1
 }
@@ -1286,6 +2304,30 @@
 ; RV64IF-NEXT:    flw fs10, 12(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_fs10:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IF-NO-ABI-NEXT:    fsw f26, 12(x2)
+; RV32IF-NO-ABI-NEXT:    fmv.s f26, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f26
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    flw f26, 12(x2)
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_fs10:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IF-NO-ABI-NEXT:    fsw f26, 12(x2)
+; RV64IF-NO-ABI-NEXT:    fmv.s f26, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f26
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    flw f26, 12(x2)
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs10}"(float %a)
   ret i32 %1
 }
@@ -1315,6 +2357,30 @@
 ; RV64IF-NEXT:    flw fs11, 12(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f27:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IF-NO-ABI-NEXT:    fsw f27, 12(x2)
+; RV32IF-NO-ABI-NEXT:    fmv.s f27, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f27
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    flw f27, 12(x2)
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f27:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IF-NO-ABI-NEXT:    fsw f27, 12(x2)
+; RV64IF-NO-ABI-NEXT:    fmv.s f27, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f27
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    flw f27, 12(x2)
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f27}"(float %a)
   ret i32 %1
 }
@@ -1344,6 +2410,30 @@
 ; RV64IF-NEXT:    flw fs11, 12(sp)
 ; RV64IF-NEXT:    addi sp, sp, 16
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_fs11:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV32IF-NO-ABI-NEXT:    fsw f27, 12(x2)
+; RV32IF-NO-ABI-NEXT:    fmv.s f27, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f27
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    flw f27, 12(x2)
+; RV32IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_fs11:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, -16
+; RV64IF-NO-ABI-NEXT:    fsw f27, 12(x2)
+; RV64IF-NO-ABI-NEXT:    fmv.s f27, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f27
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    flw f27, 12(x2)
+; RV64IF-NO-ABI-NEXT:    addi x2, x2, 16
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs11}"(float %a)
   ret i32 %1
 }
@@ -1364,6 +2454,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, ft8
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f28:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f28, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f28
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f28:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f28, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f28
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f28}"(float %a)
   ret i32 %1
 }
@@ -1384,6 +2490,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, ft8
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_ft8:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f28, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f28
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_ft8:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f28, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f28
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft8}"(float %a)
   ret i32 %1
 }
@@ -1404,6 +2526,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, ft9
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f29:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f29, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f29
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f29:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f29, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f29
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f29}"(float %a)
   ret i32 %1
 }
@@ -1424,6 +2562,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, ft9
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_ft9:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f29, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f29
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_ft9:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f29, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f29
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft9}"(float %a)
   ret i32 %1
 }
@@ -1444,6 +2598,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, ft10
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f30:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f30, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f30
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f30:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f30, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f30
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f30}"(float %a)
   ret i32 %1
 }
@@ -1464,6 +2634,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, ft10
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_ft10:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f30, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f30
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_ft10:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f30, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f30
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft10}"(float %a)
   ret i32 %1
 }
@@ -1484,6 +2670,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, ft11
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_f31:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f31, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f31
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_f31:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f31, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f31
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f31}"(float %a)
   ret i32 %1
 }
@@ -1504,6 +2706,22 @@
 ; RV64IF-NEXT:    fcvt.w.s a0, ft11
 ; RV64IF-NEXT:    #NO_APP
 ; RV64IF-NEXT:    ret
+;
+; RV32IF-NO-ABI-LABEL: explicit_register_ft11:
+; RV32IF-NO-ABI:       # %bb.0:
+; RV32IF-NO-ABI-NEXT:    fmv.s f31, f10
+; RV32IF-NO-ABI-NEXT:    #APP
+; RV32IF-NO-ABI-NEXT:    fcvt.w.s x10, f31
+; RV32IF-NO-ABI-NEXT:    #NO_APP
+; RV32IF-NO-ABI-NEXT:    ret
+;
+; RV64IF-NO-ABI-LABEL: explicit_register_ft11:
+; RV64IF-NO-ABI:       # %bb.0:
+; RV64IF-NO-ABI-NEXT:    fmv.s f31, f10
+; RV64IF-NO-ABI-NEXT:    #APP
+; RV64IF-NO-ABI-NEXT:    fcvt.w.s x10, f31
+; RV64IF-NO-ABI-NEXT:    #NO_APP
+; RV64IF-NO-ABI-NEXT:    ret
   %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft11}"(float %a)
   ret i32 %1
 }