Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -205,6 +205,7 @@
   setOperationAction(ISD::UREM, VT, Expand);
   setOperationAction(ISD::FREM, VT, Expand);
 
+
   if (!VT.isFloatingPoint() &&
       VT != MVT::v2i64 && VT != MVT::v1i64)
     for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
@@ -265,6 +266,7 @@
     setOperationAction(ISD::SDIV, VT, Expand);
     setOperationAction(ISD::UREM, VT, Expand);
     setOperationAction(ISD::SREM, VT, Expand);
+    setOperationAction(ISD::CTPOP, VT, Expand);
 
     if (!HasMVEFP) {
       setOperationAction(ISD::SINT_TO_FP, VT, Expand);
Index: llvm/test/CodeGen/Thumb2/ctpop.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/Thumb2/ctpop.ll
@@ -0,0 +1,78 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE
+
+define <2 x i32> @ctpop_i32_t(<2 x i32> %src){
+; CHECK-LABEL: ctpop_i32_t:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r4, lr}
+; CHECK-NEXT:    push {r4, lr}
+; CHECK-NEXT:    vmov d1, r2, r3
+; CHECK-NEXT:    mov.w lr, #858993459
+; CHECK-NEXT:    vmov d0, r0, r1
+; CHECK-NEXT:    adr r0, .LCPI0_0
+; CHECK-NEXT:    vldrw.u32 q1, [r0]
+; CHECK-NEXT:    mov.w r1, #1431655765
+; CHECK-NEXT:    mov.w r4, #16843009
+; CHECK-NEXT:    vand q0, q0, q1
+; CHECK-NEXT:    vmov r0, s3
+; CHECK-NEXT:    and.w r2, r1, r0, lsr #1
+; CHECK-NEXT:    subs r0, r0, r2
+; CHECK-NEXT:    and.w r3, lr, r0, lsr #2
+; CHECK-NEXT:    bic r0, r0, #-858993460
+; CHECK-NEXT:    add r0, r3
+; CHECK-NEXT:    vmov r3, s0
+; CHECK-NEXT:    add.w r0, r0, r0, lsr #4
+; CHECK-NEXT:    bic r12, r0, #-252645136
+; CHECK-NEXT:    and.w r0, r1, r3, lsr #1
+; CHECK-NEXT:    subs r0, r3, r0
+; CHECK-NEXT:    and.w r3, lr, r0, lsr #2
+; CHECK-NEXT:    bic r0, r0, #-858993460
+; CHECK-NEXT:    add r0, r3
+; CHECK-NEXT:    vmov r3, s1
+; CHECK-NEXT:    add.w r0, r0, r0, lsr #4
+; CHECK-NEXT:    bic r0, r0, #-252645136
+; CHECK-NEXT:    muls r0, r4, r0
+; CHECK-NEXT:    and.w r2, r1, r3, lsr #1
+; CHECK-NEXT:    subs r2, r3, r2
+; CHECK-NEXT:    and.w r3, lr, r2, lsr #2
+; CHECK-NEXT:    bic r2, r2, #-858993460
+; CHECK-NEXT:    add r2, r3
+; CHECK-NEXT:    vmov r3, s2
+; CHECK-NEXT:    vldr s1, .LCPI0_1
+; CHECK-NEXT:    add.w r2, r2, r2, lsr #4
+; CHECK-NEXT:    bic r2, r2, #-252645136
+; CHECK-NEXT:    muls r2, r4, r2
+; CHECK-NEXT:    orrs r0, r2
+; CHECK-NEXT:    lsrs r0, r0, #24
+; CHECK-NEXT:    and.w r1, r1, r3, lsr #1
+; CHECK-NEXT:    subs r1, r3, r1
+; CHECK-NEXT:    and.w r3, lr, r1, lsr #2
+; CHECK-NEXT:    bic r1, r1, #-858993460
+; CHECK-NEXT:    add r1, r3
+; CHECK-NEXT:    mul r3, r12, r4
+; CHECK-NEXT:    add.w r1, r1, r1, lsr #4
+; CHECK-NEXT:    bic r1, r1, #-252645136
+; CHECK-NEXT:    muls r1, r4, r1
+; CHECK-NEXT:    orrs r1, r3
+; CHECK-NEXT:    lsrs r1, r1, #24
+; CHECK-NEXT:    vmov s2, r1
+; CHECK-NEXT:    vmov s0, r0
+; CHECK-NEXT:    vmov.f32 s3, s1
+; CHECK-NEXT:    vmov r0, r1, d0
+; CHECK-NEXT:    vmov r2, r3, d1
+; CHECK-NEXT:    pop {r4, pc}
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  @ %bb.1:
+; CHECK-NEXT:  .LCPI0_0:
+; CHECK-NEXT:    .long 4294967295 @ 0xffffffff
+; CHECK-NEXT:    .long 0 @ 0x0
+; CHECK-NEXT:    .long 4294967295 @ 0xffffffff
+; CHECK-NEXT:    .long 0 @ 0x0
+; CHECK-NEXT:  .LCPI0_1:
+; CHECK-NEXT:    .long 0 @ float 0
+entry:
+  %0 = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %src)
+  ret <2 x i32> %0
+}
+
+declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>)