Index: llvm/test/CodeGen/AArch64/cmp-bool.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/cmp-bool.ll
@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
+
+define void @bool_eq(i1 zeroext %a, i1 zeroext %b, void ()* nocapture %c) nounwind {
+; CHECK-LABEL: bool_eq:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmp w0, w1
+; CHECK-NEXT:    b.eq .LBB0_2
+; CHECK-NEXT:  // %bb.1: // %if.end
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB0_2: // %if.then
+; CHECK-NEXT:    br x2
+entry:
+  %0 = xor i1 %a, %b
+  br i1 %0, label %if.end, label %if.then
+
+if.then:
+  tail call void %c() #1
+  br label %if.end
+
+if.end:
+  ret void
+}
+
+define void @bool_ne(i1 zeroext %a, i1 zeroext %b, void ()* nocapture %c) nounwind {
+; CHECK-LABEL: bool_ne:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    eor w8, w0, w1
+; CHECK-NEXT:    cmp w8, #1 // =1
+; CHECK-NEXT:    b.ne .LBB1_2
+; CHECK-NEXT:  // %bb.1: // %if.then
+; CHECK-NEXT:    br x2
+; CHECK-NEXT:  .LBB1_2: // %if.end
+; CHECK-NEXT:    ret
+entry:
+  %cmp = xor i1 %a, %b
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+  tail call void %c() #1
+  br label %if.end
+
+if.end:
+  ret void
+}
Index: llvm/test/CodeGen/ARM/cmp-bool.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/ARM/cmp-bool.ll
@@ -0,0 +1,77 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=armv7a < %s | FileCheck %s --check-prefix=ARM
+; RUN: llc -mtriple=armv6m < %s | FileCheck %s --check-prefix=THUMB
+; RUN: llc -mtriple=armv7m < %s | FileCheck %s --check-prefix=THUMB2
+
+define void @bool_eq(i1 zeroext %a, i1 zeroext %b, void ()* nocapture %c) nounwind {
+; ARM-LABEL: bool_eq:
+; ARM:       @ %bb.0: @ %entry
+; ARM-NEXT:    cmp r0, r1
+; ARM-NEXT:    bxne lr
+; ARM-NEXT:    bx r2
+;
+; THUMB-LABEL: bool_eq:
+; THUMB:       @ %bb.0: @ %entry
+; THUMB-NEXT:    push {r7, lr}
+; THUMB-NEXT:    cmp r0, r1
+; THUMB-NEXT:    bne .LBB0_2
+; THUMB-NEXT:  @ %bb.1: @ %if.then
+; THUMB-NEXT:    blx r2
+; THUMB-NEXT:  .LBB0_2: @ %if.end
+; THUMB-NEXT:    pop {r7, pc}
+;
+; THUMB2-LABEL: bool_eq:
+; THUMB2:       @ %bb.0: @ %entry
+; THUMB2-NEXT:    cmp r0, r1
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    bxne lr
+; THUMB2-NEXT:    bx r2
+entry:
+  %0 = xor i1 %a, %b
+  br i1 %0, label %if.end, label %if.then
+
+if.then:
+  tail call void %c() #1
+  br label %if.end
+
+if.end:
+  ret void
+}
+
+define void @bool_ne(i1 zeroext %a, i1 zeroext %b, void ()* nocapture %c) nounwind {
+; ARM-LABEL: bool_ne:
+; ARM:       @ %bb.0: @ %entry
+; ARM-NEXT:    eor r0, r0, r1
+; ARM-NEXT:    cmp r0, #1
+; ARM-NEXT:    bxne lr
+; ARM-NEXT:    bx r2
+;
+; THUMB-LABEL: bool_ne:
+; THUMB:       @ %bb.0: @ %entry
+; THUMB-NEXT:    push {r7, lr}
+; THUMB-NEXT:    eors r0, r1
+; THUMB-NEXT:    cmp r0, #1
+; THUMB-NEXT:    bne .LBB1_2
+; THUMB-NEXT:  @ %bb.1: @ %if.then
+; THUMB-NEXT:    blx r2
+; THUMB-NEXT:  .LBB1_2: @ %if.end
+; THUMB-NEXT:    pop {r7, pc}
+;
+; THUMB2-LABEL: bool_ne:
+; THUMB2:       @ %bb.0: @ %entry
+; THUMB2-NEXT:    eors r0, r1
+; THUMB2-NEXT:    cmp r0, #1
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    bxne lr
+; THUMB2-NEXT:    bx r2
+entry:
+  %cmp = xor i1 %a, %b
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+  tail call void %c() #1
+  br label %if.end
+
+if.end:
+  ret void
+}
Index: llvm/test/CodeGen/RISCV/cmp-bool.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/cmp-bool.ll
@@ -0,0 +1,79 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 < %s | FileCheck --check-prefix=RV32 %s
+; RUN: llc -mtriple=riscv64 < %s | FileCheck --check-prefix=RV64 %s
+
+define void @bool_eq(i1 zeroext %a, i1 zeroext %b, void ()* nocapture %c) nounwind {
+; RV32-LABEL: bool_eq:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    addi sp, sp, -16
+; RV32-NEXT:    sw ra, 12(sp)
+; RV32-NEXT:    bne a0, a1, .LBB0_2
+; RV32-NEXT:  # %bb.1: # %if.then
+; RV32-NEXT:    jalr a2
+; RV32-NEXT:  .LBB0_2: # %if.end
+; RV32-NEXT:    lw ra, 12(sp)
+; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: bool_eq:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:    addi sp, sp, -16
+; RV64-NEXT:    sd ra, 8(sp)
+; RV64-NEXT:    bne a0, a1, .LBB0_2
+; RV64-NEXT:  # %bb.1: # %if.then
+; RV64-NEXT:    jalr a2
+; RV64-NEXT:  .LBB0_2: # %if.end
+; RV64-NEXT:    ld ra, 8(sp)
+; RV64-NEXT:    addi sp, sp, 16
+; RV64-NEXT:    ret
+entry:
+  %0 = xor i1 %a, %b
+  br i1 %0, label %if.end, label %if.then
+
+if.then:
+  tail call void %c() #1
+  br label %if.end
+
+if.end:
+  ret void
+}
+
+define void @bool_ne(i1 zeroext %a, i1 zeroext %b, void ()* nocapture %c) nounwind {
+; RV32-LABEL: bool_ne:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    addi sp, sp, -16
+; RV32-NEXT:    sw ra, 12(sp)
+; RV32-NEXT:    xor a0, a0, a1
+; RV32-NEXT:    addi a1, zero, 1
+; RV32-NEXT:    bne a0, a1, .LBB1_2
+; RV32-NEXT:  # %bb.1: # %if.then
+; RV32-NEXT:    jalr a2
+; RV32-NEXT:  .LBB1_2: # %if.end
+; RV32-NEXT:    lw ra, 12(sp)
+; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: bool_ne:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:    addi sp, sp, -16
+; RV64-NEXT:    sd ra, 8(sp)
+; RV64-NEXT:    xor a0, a0, a1
+; RV64-NEXT:    addi a1, zero, 1
+; RV64-NEXT:    bne a0, a1, .LBB1_2
+; RV64-NEXT:  # %bb.1: # %if.then
+; RV64-NEXT:    jalr a2
+; RV64-NEXT:  .LBB1_2: # %if.end
+; RV64-NEXT:    ld ra, 8(sp)
+; RV64-NEXT:    addi sp, sp, 16
+; RV64-NEXT:    ret
+entry:
+  %cmp = xor i1 %a, %b
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+  tail call void %c() #1
+  br label %if.end
+
+if.end:
+  ret void
+}
Index: llvm/test/CodeGen/X86/cmp-bool.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/cmp-bool.ll
@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64 < %s | FileCheck %s
+
+define void @bool_eq(i1 zeroext %a, i1 zeroext %b, void ()* nocapture %c) nounwind {
+; CHECK-LABEL: bool_eq:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xorl %esi, %edi
+; CHECK-NEXT:    je .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %if.end
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  .LBB0_2: # %if.then
+; CHECK-NEXT:    jmpq *%rdx # TAILCALL
+entry:
+  %0 = xor i1 %a, %b
+  br i1 %0, label %if.end, label %if.then
+
+if.then:
+  tail call void %c() #1
+  br label %if.end
+
+if.end:
+  ret void
+}
+
+define void @bool_ne(i1 zeroext %a, i1 zeroext %b, void ()* nocapture %c) nounwind {
+; CHECK-LABEL: bool_ne:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xorl %esi, %edi
+; CHECK-NEXT:    cmpb $1, %dil
+; CHECK-NEXT:    jne .LBB1_1
+; CHECK-NEXT:  # %bb.2: # %if.then
+; CHECK-NEXT:    jmpq *%rdx # TAILCALL
+; CHECK-NEXT:  .LBB1_1: # %if.end
+; CHECK-NEXT:    retq
+entry:
+  %cmp = xor i1 %a, %b
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+  tail call void %c() #1
+  br label %if.end
+
+if.end:
+  ret void
+}