Index: llvm/test/TableGen/Common/GlobalISelEmitterCommon.td
===================================================================
--- /dev/null
+++ llvm/test/TableGen/Common/GlobalISelEmitterCommon.td
@@ -0,0 +1,18 @@
+// Common target boilerplate for GlobalISelEmitter tests.
+def MyTargetISA : InstrInfo;
+def MyTarget : Target { let InstructionSet = MyTargetISA; }
+
+def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
+def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
+def GPR32Op : RegisterOperand<GPR32>;
+def F0 : Register<"f0"> { let Namespace = "MyTarget"; }
+def FPR32 : RegisterClass<"MyTarget", [f32], 32, (add F0)>;
+def p0 : PtrValueType <i32, 0>;
+
+class I<dag OOps, dag IOps, list<dag> Pat>
+  : Instruction {
+  let Namespace = "MyTarget";
+  let OutOperandList = OOps;
+  let InOperandList = IOps;
+  let Pattern = Pat;
+}
Index: llvm/test/TableGen/GlobalISelEmitter-PR39045.td
===================================================================
--- llvm/test/TableGen/GlobalISelEmitter-PR39045.td
+++ llvm/test/TableGen/GlobalISelEmitter-PR39045.td
@@ -1,4 +1,4 @@
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include %s -o %t
+// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common  %s -o %t
 // RUN: FileCheck %s < %t
 
 // Both predicates should be tested
@@ -6,9 +6,7 @@
 // CHECK-DAG: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_pat_frag_a,
 
 include "llvm/Target/Target.td"
-
-def MyTargetISA : InstrInfo;
-def MyTarget : Target { let InstructionSet = MyTargetISA; }
+include "GlobalISelEmitterCommon.td"
 
 
 def pat_frag_a : PatFrag <(ops node:$ptr), (load node:$ptr), [{}]> {
@@ -21,9 +19,6 @@
    let GISelPredicateCode = [{ return isInstB(MI); }];
 }
 
-def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
-def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
-
 def inst_a : Instruction {
   let OutOperandList = (outs GPR32:$dst);
   let InOperandList = (ins GPR32:$src);
Index: llvm/test/TableGen/GlobalISelEmitter.td
===================================================================
--- llvm/test/TableGen/GlobalISelEmitter.td
+++ llvm/test/TableGen/GlobalISelEmitter.td
@@ -1,6 +1,6 @@
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -optimize-match-table=false %s -o %T/non-optimized.cpp
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -optimize-match-table=true  %s -o %T/optimized.cpp
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include %s -o %T/default.cpp
+// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/non-optimized.cpp
+// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=true  %s -o %T/optimized.cpp
+// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o %T/default.cpp
 
 // RUN: FileCheck %s --check-prefixes=CHECK,R19C,R19N -input-file=%T/non-optimized.cpp
 // RUN: FileCheck %s --check-prefixes=CHECK,R19C,R19O -input-file=%T/optimized.cpp
@@ -23,30 +23,14 @@
 // RUN: diff %T/default.cpp %T/optimized.cpp
 
 include "llvm/Target/Target.td"
+include "GlobalISelEmitterCommon.td"
 
 //===- Define the necessary boilerplate for our test target. --------------===//
 
-def MyTargetISA : InstrInfo;
-def MyTarget : Target { let InstructionSet = MyTargetISA; }
-
 let TargetPrefix = "mytarget" in {
 def int_mytarget_nop : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
 }
 
-def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
-def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
-def GPR32Op : RegisterOperand<GPR32>;
-def F0 : Register<"f0"> { let Namespace = "MyTarget"; }
-def FPR32 : RegisterClass<"MyTarget", [f32], 32, (add F0)>;
-
-class I<dag OOps, dag IOps, list<dag> Pat>
-  : Instruction {
-  let Namespace = "MyTarget";
-  let OutOperandList = OOps;
-  let InOperandList = IOps;
-  let Pattern = Pat;
-}
-
 def complex : Operand<i32>, ComplexPattern<i32, 2, "SelectComplexPattern", []> {
   let MIOperandInfo = (ops i32imm, i32imm);
 }
@@ -996,8 +980,6 @@
 // NOOPT-NEXT:    GIR_Done,
 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 
-def p0 : PtrValueType <i32, 0>;
-
 def : Pat<(load GPR32:$src),
           (p0 (LOAD GPR32:$src))>;
 
Index: llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td
===================================================================
--- llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td
+++ llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td
@@ -1,28 +1,11 @@
-// RUN: llvm-tblgen -gen-global-isel -I %p/../../include %s -o - | FileCheck %s
-
-// Boilerplate code.
+// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o - | FileCheck %s
 include "llvm/Target/Target.td"
-
-def MyTargetISA : InstrInfo;
-def MyTarget : Target { let InstructionSet = MyTargetISA; }
+include "GlobalISelEmitterCommon.td"
 
 let TargetPrefix = "mytarget" in {
     def int_mytarget_anyptr : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
 }
 
-def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
-def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
-def GPR32Op : RegisterOperand<GPR32>;
-def p0 : PtrValueType <i32, 0>;
-
-class I<dag OOps, dag IOps, list<dag> Pat>
-  : Instruction {
-  let Namespace = "MyTarget";
-  let OutOperandList = OOps;
-  let InOperandList = IOps;
-  let Pattern = Pat;
-}
-
 // Ensure that llvm_anyptr_ty on an intrinsic results in a
 // GIM_CheckPointerToAny rather than a GIM_CheckType.
 //
Index: llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td
===================================================================
--- llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td
+++ llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td
@@ -1,24 +1,8 @@
-// RUN: llvm-tblgen -warn-on-skipped-patterns -gen-global-isel -I %p/../../include %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: llvm-tblgen -warn-on-skipped-patterns -gen-global-isel -I %p/../../include %s -I %p/Common -o /dev/null 2>&1 | FileCheck %s
 include "llvm/Target/Target.td"
+include "GlobalISelEmitterCommon.td"
 
 //===- Boiler plate target code -===//
-def MyTargetISA : InstrInfo;
-def MyTarget : Target { let InstructionSet = MyTargetISA; }
-
-let TargetPrefix = "mytarget" in {
-def int_mytarget_nop : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
-}
-
-def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
-def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
-
-class I<dag OOps, dag IOps, list<dag> Pat>
-  : Instruction {
-  let Namespace = "MyTarget";
-  let OutOperandList = OOps;
-  let InOperandList = IOps;
-  let Pattern = Pat;
-}
 
 def complex : Operand<i32>, ComplexPattern<i32, 2, "SelectComplexPattern", []> {
   let MIOperandInfo = (ops i32imm, i32imm);