diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -456,6 +456,16 @@ VK == RISCVMCExpr::VK_RISCV_None; } + bool isUImm6() const { + if (!isImm()) + return false; + RISCVMCExpr::VariantKind VK; + int64_t Imm; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isUInt<6>(Imm) && + VK == RISCVMCExpr::VK_RISCV_None; + } + bool isSImm6() const { if (!isImm()) return false; @@ -487,6 +497,16 @@ VK == RISCVMCExpr::VK_RISCV_None; } + bool isUImm7() const { + if (!isImm()) + return false; + RISCVMCExpr::VariantKind VK; + int64_t Imm; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isUInt<7>(Imm) && + VK == RISCVMCExpr::VK_RISCV_None; + } + bool isUImm7Lsb00() const { if (!isImm()) return false; @@ -899,6 +919,8 @@ return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5) - 1); case Match_InvalidUImm5: return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1); + case Match_InvalidUImm6: + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 6) - 1); case Match_InvalidSImm6: return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 5), (1 << 5) - 1); @@ -910,6 +932,8 @@ return generateImmOutOfRangeError( Operands, ErrorInfo, 1, (1 << 5) - 1, "immediate must be in [0xfffe0, 0xfffff] or"); + case Match_InvalidUImm7: + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 7) - 1); case Match_InvalidUImm7Lsb00: return generateImmOutOfRangeError( Operands, ErrorInfo, 0, (1 << 7) - 4, diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -48,6 +48,80 @@ AssemblerPredicate<"FeatureStdExtC", "'C' (Compressed Instructions)">; +def FeatureExtZbb + : SubtargetFeature<"zbb", "HasStdExtZbb", "true", + "'Zbb' (Base Bit Manipulation Instructions)">; +def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">, + AssemblerPredicate<"FeatureExtZbb">; + +def FeatureExtZbc + : SubtargetFeature<"zbc", "HasStdExtZbc", "true", + "'Zbc' (Carry-Less Bit Manipulation Instructions)">; +def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">, + AssemblerPredicate<"FeatureExtZbc">; + +def FeatureExtZbe + : SubtargetFeature<"zbe", "HasStdExtZbe", "true", + "'Zbe' (Extract-Deposit Bit Manipulation Instructions)">; +def HasStdExtZbe : Predicate<"Subtarget->hasStdExtZbe()">, + AssemblerPredicate<"FeatureExtZbe">; + +def FeatureExtZbf + : SubtargetFeature<"zbf", "HasStdExtZbf", "true", + "'Zbf' (Bit-Field Bit Manipulation Instructions)">; +def HasStdExtZbf : Predicate<"Subtarget->hasStdExtZbf()">, + AssemblerPredicate<"FeatureExtZbf">; + +def FeatureExtZbm + : SubtargetFeature<"zbm", "HasStdExtZbm", "true", + "'Zbm' (Matrix Bit Manipulation Instructions)">; +def HasStdExtZbm : Predicate<"Subtarget->hasStdExtZbm()">, + AssemblerPredicate<"FeatureExtZbm">; + +def FeatureExtZbp + : SubtargetFeature<"zbp", "HasStdExtZbp", "true", + "'Zbp' (Permutation Bit Manipulation Instructions)">; +def HasStdExtZbp : Predicate<"Subtarget->hasStdExtZbp()">, + AssemblerPredicate<"FeatureExtZbp">; + +def FeatureExtZbr + : SubtargetFeature<"zbr", "HasStdExtZbr", "true", + "'Zbr' (Polynomial Reduction Bit Manipulation Instructions)">; +def HasStdExtZbr : Predicate<"Subtarget->hasStdExtZbr()">, + AssemblerPredicate<"FeatureExtZbr">; + +def FeatureExtZbs + : SubtargetFeature<"zbs", "HasStdExtZbs", "true", + "'Zbs' (Single-Bit Bit Manipulation Instructions)">; +def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">, + AssemblerPredicate<"FeatureExtZbs">; + +def FeatureExtZbt + : SubtargetFeature<"zbt", "HasStdExtZbt", "true", + "'Zbt' (Ternary Bit Manipulation Instructions)">; +def HasStdExtZbt : Predicate<"Subtarget->hasStdExtZbt()">, + AssemblerPredicate<"FeatureExtZbt">; + +// For instructions that belong to both the basic and the permutation subextensions. +// They should be added if any of the two subextension has been specified. +def HasStdExtZbbOrZbp + : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp()">; + +def FeatureStdExtB + : SubtargetFeature<"b", "HasStdExtB", "true", + "'B' (Bit Manipulation Instructions)", + [FeatureExtZbb, + FeatureExtZbc, + FeatureExtZbe, + FeatureExtZbf, + FeatureExtZbm, + FeatureExtZbp, + FeatureExtZbr, + FeatureExtZbs, + FeatureExtZbt]>; +def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">, + AssemblerPredicate<"FeatureStdExtB">; + def FeatureRVCHints : SubtargetFeature<"rvc-hints", "EnableRVCHintInstrs", "true", "Enable RVC Hint Instructions.">; diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -151,9 +151,12 @@ setOperationAction(ISD::ROTL, XLenVT, Expand); setOperationAction(ISD::ROTR, XLenVT, Expand); setOperationAction(ISD::BSWAP, XLenVT, Expand); - setOperationAction(ISD::CTTZ, XLenVT, Expand); - setOperationAction(ISD::CTLZ, XLenVT, Expand); - setOperationAction(ISD::CTPOP, XLenVT, Expand); + + if(!Subtarget.hasStdExtB()) { + setOperationAction(ISD::CTTZ, XLenVT, Expand); + setOperationAction(ISD::CTLZ, XLenVT, Expand); + setOperationAction(ISD::CTPOP, XLenVT, Expand); + } ISD::CondCode FPCCToExtend[] = { ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1144,3 +1144,4 @@ include "RISCVInstrInfoF.td" include "RISCVInstrInfoD.td" include "RISCVInstrInfoC.td" +include "RISCVInstrInfoB.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td new file mode 100644 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td @@ -0,0 +1,515 @@ +//===-- RISCVInstrFormatsB.td - RISCV B Instruction Formats --*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the RISC-V B extension instruction formats. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instruction class templates +//===----------------------------------------------------------------------===// + +def uimm6 : Operand, ImmLeaf(Imm);}]> { + let ParserMatchClass = UImmAsmOperand<6>; + let DecoderMethod = "decodeUImmOperand<6>"; +} + +def uimm7 : Operand, ImmLeaf(Imm);}]> { + let ParserMatchClass = UImmAsmOperand<7>; + let DecoderMethod = "decodeUImmOperand<7>"; +} + +//===----------------------------------------------------------------------===// +// Instruction class templates +//===----------------------------------------------------------------------===// + +// These templates should be moved to RISCVInstrFormats.td once the B extension has +// been ratified. + +class RVBInstShift funct5, bits<3> funct3, RISCVOpcode opcode, + string opcodestr> + : RVInst<(outs GPR:$rd), (ins GPR:$rs1, uimm6:$imm6), + opcodestr, "$rd, $rs1, $imm6", [], InstFormatI> { + bits<5> rs1; + bits<6> imm6; + bits<5> rd; + + let Inst{31-27} = funct5; + // NOTE: the shamt bit-field should be 7-bits long, but since that would cause + // decoding conflicts all the shift operations are encoded with op(26) = 0 + // apart from funnel shifts FSL, FSR and FSRI that have op(26) = 1 + let Inst{26} = 0; + let Inst{25-20} = imm6; + let Inst{19-15} = rs1; + let Inst{14-12} = funct3; + let Inst{11-7} = rd; + let Opcode = opcode.Value; +} + +class RVBInstImm7 funct5, bits<3> funct3, RISCVOpcode opcode, + string opcodestr> + : RVInst<(outs GPR:$rd), (ins GPR:$rs1, uimm7:$imm7), + opcodestr, "$rd, $rs1, $imm7", [], InstFormatI> { + bits<5> rs1; + bits<7> imm7; + bits<5> rd; + + let Inst{31-27} = funct5; + let Inst{26-20} = imm7; + let Inst{19-15} = rs1; + let Inst{14-12} = funct3; + let Inst{11-7} = rd; + let Opcode = opcode.Value; +} + +class RVBInstImm6 funct6, bits<3> funct3, RISCVOpcode opcode, + string opcodestr> + : RVInst<(outs GPR:$rd), (ins GPR:$rs1, uimm6:$imm6), + opcodestr, "$rd, $rs1, $imm6", [], InstFormatI> { + bits<5> rs1; + bits<6> imm6; + bits<5> rd; + + let Inst{31-26} = funct6; + let Inst{25-20} = imm6; + let Inst{19-15} = rs1; + let Inst{14-12} = funct3; + let Inst{11-7} = rd; + let Opcode = opcode.Value; +} + +class RVBInstImm5 funct7, bits<3> funct3, RISCVOpcode opcode, + string opcodestr> + : RVInst<(outs GPR:$rd), (ins GPR:$rs1, uimm5:$imm5), + opcodestr, "$rd, $rs1, $imm5", [], InstFormatI> { + bits<5> rs1; + bits<5> imm5; + bits<5> rd; + + let Inst{31-25} = funct7; + let Inst{24-20} = imm5; + let Inst{19-15} = rs1; + let Inst{14-12} = funct3; + let Inst{11-7} = rd; + let Opcode = opcode.Value; +} + +class RVBInstFunct12 funct12, bits<3> funct3, RISCVOpcode opcode, + string opcodestr> + : RVInst<(outs GPR:$rd), (ins GPR:$rs1), + opcodestr, "$rd, $rs1", [], InstFormatI> { + bits<5> rs1; + bits<5> rd; + + let Inst{31-20} = funct12; + let Inst{19-15} = rs1; + let Inst{14-12} = funct3; + let Inst{11-7} = rd; + let Opcode = opcode.Value; +} + +class RVBInstR funct7, bits<3> funct3, string opcodestr> + : RVInstR {} + +class RVBInstR4Reg funct2, bits<3> funct3, RISCVOpcode opcode, + string opcodestr, string argstr> + : RVInst<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, GPR:$rs3), opcodestr, + argstr, [], InstFormatR4> { + bits<5> rs3; + bits<5> rs2; + bits<5> rs1; + bits<5> rd; + + let Inst{31-27} = rs3; + let Inst{26-25} = funct2; + let Inst{24-20} = rs2; + let Inst{19-15} = rs1; + let Inst{14-12} = funct3; + let Inst{11-7} = rd; + let Opcode = opcode.Value; +} + +// Currently implemented only for one instruction FSRIW +class RVBInstR4Imm funct2, bits<3> funct3, RISCVOpcode opcode, + string opcodestr> + : RVInst<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs3, uimm5:$imm), + opcodestr, "$rd, $rs1, $rs3, $imm", [], InstFormatR4> { + bits<5> rs3; + bits<5> imm; + bits<5> rs1; + bits<5> rd; + + let Inst{31-27} = rs3; + let Inst{26-25} = funct2; + let Inst{24-20} = imm; + let Inst{19-15} = rs1; + let Inst{14-12} = funct3; + let Inst{11-7} = rd; + let Opcode = opcode.Value; +} + +// Currently implemented only for one instruction FSRI +class RVBInstR4Imm6 funct3, RISCVOpcode opcode, + string opcodestr> + : RVInst<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs3, uimm5:$imm), + opcodestr, "$rd, $rs1, $rs3, $imm", [], InstFormatR4> { + bits<5> rs3; + bits<6> imm; + bits<5> rs1; + bits<5> rd; + + let Inst{31-27} = rs3; + let Inst{26} = funct1; + let Inst{25-20} = imm; + let Inst{19-15} = rs1; + let Inst{14-12} = funct3; + let Inst{11-7} = rd; + let Opcode = opcode.Value; +} + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +// Base instructions + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +let Predicates = [HasStdExtZbb] in { + def CLZ : RVBInstFunct12<0b011000000000, 0b001, OPC_OP_IMM, "clz">, Sched<[]>; + def CTZ : RVBInstFunct12<0b011000000001, 0b001, OPC_OP_IMM, "ctz">, Sched<[]>; + def PCNT : RVBInstFunct12<0b011000000010, 0b001, OPC_OP_IMM, "pcnt">, Sched<[]>; + + def SLO : ALU_rr<0b0010000, 0b001, "slo">, Sched<[]>; + def SRO : ALU_rr<0b0010000, 0b101, "sro">, Sched<[]>; + def SLOI : RVBInstShift<0b00100, 0b001, OPC_OP_IMM, "sloi">, Sched<[]>; + def SROI : RVBInstShift<0b00100, 0b101, OPC_OP_IMM, "sroi">, Sched<[]>; + + def MIN : ALU_rr<0b0000101, 0b100, "min">, Sched<[]>; + def MAX : ALU_rr<0b0000101, 0b101, "max">, Sched<[]>; + def MINU : ALU_rr<0b0000101, 0b110, "minu">, Sched<[]>; + def MAXU : ALU_rr<0b0000101, 0b111, "maxu">, Sched<[]>; + + def SEXTB : RVBInstFunct12<0b011000000100, 0b001, OPC_OP_IMM, "sext.b">, Sched<[]>; + def SEXTH : RVBInstFunct12<0b011000000101, 0b001, OPC_OP_IMM, "sext.h">, Sched<[]>; +} + +let Predicates = [HasStdExtZbb, IsRV64] in { + def CLZW : RVBInstFunct12<0b011000000000, 0b001, OPC_OP_IMM_32, "clzw">, Sched<[]>; + def CTZW : RVBInstFunct12<0b011000000001, 0b001, OPC_OP_IMM_32, "ctzw">, Sched<[]>; + def PCNTW : RVBInstFunct12<0b011000000010, 0b001, OPC_OP_IMM_32, "pcntw">, Sched<[]>; + def SLOW : RVBInstR<0b0010000, 0b001, "slow">, Sched<[]>; + def SROW : RVBInstR<0b0010000, 0b101, "srow">, Sched<[]>; + def SLOIW : RVBInstImm5<0b0010000, 0b001, OPC_OP_IMM_32, "sloiw">, Sched<[]>; + def SROIW : RVBInstImm5<0b0010000, 0b101, OPC_OP_IMM_32, "sroiw">, Sched<[]>; + def ADDIWU : RVInstI<0b100, OPC_OP_IMM_32, (outs GPR:$rd), + (ins GPR:$rs1, simm12:$imm12), + "addiwu", "$rd, $rs1, $imm12">, Sched<[]>; + + def SLLIUW : RVBInstShift<0b00001, 0b001, OPC_OP_IMM_32, "slliu.w">, Sched<[]>; + + def ADDWU : RVBInstR<0b0000101, 0b000, "addwu">, Sched<[]>; + def SUBWU : RVBInstR<0b0100101, 0b000, "subwu">, Sched<[]>; + def ADDUW : RVBInstR<0b0000100, 0b000, "addu.w">, Sched<[]>; + def SUBUW : RVBInstR<0b0100100, 0b000, "subu.w">, Sched<[]>; +} + +// Carry-less instructions + +let Predicates = [HasStdExtZbc] in { + def CLMUL : ALU_rr<0b0000101, 0b001, "clmul">, Sched<[]>; + def CLMULR : ALU_rr<0b0000101, 0b010, "clmulr">, Sched<[]>; + def CLMULH : ALU_rr<0b0000101, 0b011, "clmulh">, Sched<[]>; +} + +let Predicates = [HasStdExtZbc, IsRV64] in { + def CLMULW : RVBInstR<0b0000101, 0b001, "clmulw">, Sched<[]>; + def CLMULRW : RVBInstR<0b0000101, 0b010, "clmulrw">, Sched<[]>; + def CLMULHW : RVBInstR<0b0000101, 0b011, "clmulhw">, Sched<[]>; +} + +// Extract-bit/Deposit-bit instructions + +let Predicates = [HasStdExtZbe] in { + def BDEP : ALU_rr<0b0100100, 0b110, "bdep">, Sched<[]>; + def BEXT : ALU_rr<0b0000100, 0b110, "bext">, Sched<[]>; +} + +let Predicates = [HasStdExtZbe, IsRV64] in { + def BDEPW : RVBInstR<0b0100100, 0b110, "bdepw">, Sched<[]>; + def BEXTW : RVBInstR<0b0000100, 0b110, "bextw">, Sched<[]>; +} + +// Bit-Field instructions + +let Predicates = [HasStdExtZbf] in { + def BFP : ALU_rr<0b0100100, 0b111, "bfp">, Sched<[]>; +} + +let Predicates = [HasStdExtZbf, IsRV64] in { + def BFPW : RVBInstR<0b0100100, 0b111, "bfpw">, Sched<[]>; +} + +// Matrix Instructions + +let Predicates = [HasStdExtZbm, IsRV64] in { + def BMATOR : ALU_rr<0b0000100, 0b011, "bmator">, Sched<[]>; + def BMATXOR : ALU_rr<0b0100100, 0b011, "bmatxor">, Sched<[]>; + def BMATFLIP : RVBInstFunct12<0b011000000011, 0b001, OPC_OP_IMM, "bmatflip">, Sched<[]>; +} + +// Bit Permutations Instructions + +let Predicates = [HasStdExtZbbOrZbp] in { + def ANDN : ALU_rr<0b0100000, 0b111, "andn">, Sched<[]>; + def ORN : ALU_rr<0b0100000, 0b110, "orn">, Sched<[]>; + def XNOR : ALU_rr<0b0100000, 0b100, "xnor">, Sched<[]>; + def PACK : ALU_rr<0b0000100, 0b100, "pack">, Sched<[]>; + def PACKU : ALU_rr<0b0100100, 0b100, "packu">, Sched<[]>; + def PACKH : ALU_rr<0b0000100, 0b111, "packh">, Sched<[]>; + def ROL : ALU_rr<0b0110000, 0b001, "rol">, Sched<[]>; + def ROR : ALU_rr<0b0110000, 0b101, "ror">, Sched<[]>; + def RORI : RVBInstImm7<0b01100, 0b101, OPC_OP_IMM, "rori">, Sched<[]>; +} + +let Predicates = [HasStdExtZbp] in { + def GREV : ALU_rr<0b0110100, 0b101, "grev">, Sched<[]>; + def GORC : ALU_rr<0b0010100, 0b101, "gorc">, Sched<[]>; + def SHFL : ALU_rr<0b0000100, 0b001, "shfl">, Sched<[]>; + def UNSHFL : ALU_rr<0b0000100, 0b101, "unshfl">, Sched<[]>; + + // RVBInstShift sets inst[26] to 0. We use it here to avoid a decoding conflict with FSRI + def GREVI : RVBInstShift<0b01101, 0b101, OPC_OP_IMM, "grevi">, Sched<[]>; + def GORCI : RVBInstShift<0b00101, 0b101, OPC_OP_IMM, "gorci">, Sched<[]>; + + def SHFLI : RVBInstImm6<0b000010, 0b001, OPC_OP_IMM, "shfli">, Sched<[]>; + def UNSHFLI : RVBInstImm6<0b000010, 0b101, OPC_OP_IMM, "unshfli">, Sched<[]>; +} + +let Predicates = [HasStdExtZbbOrZbp, IsRV64] in { + def ROLW : RVBInstR<0b0110000, 0b001, "rolw">, Sched<[]>; + def RORW : RVBInstR<0b0110000, 0b101, "rorw">, Sched<[]>; + def RORIW : RVBInstImm5<0b0110000, 0b101, OPC_OP_IMM_32, "roriw">, Sched<[]>; + + def PACKW : RVBInstR<0b0000100, 0b100, "packw">, Sched<[]>; + def PACKUW : RVBInstR<0b0100100, 0b100, "packuw">, Sched<[]>; +} + +let Predicates = [HasStdExtZbp, IsRV64] in { + def GREVW : RVBInstR<0b0110100, 0b101, "grevw">, Sched<[]>; + def GORCW : RVBInstR<0b0010100, 0b101, "gorcw">, Sched<[]>; + def GREVIW : RVBInstImm5<0b0110100, 0b101, OPC_OP_IMM_32, "greviw">, Sched<[]>; + def GORCIW : RVBInstImm5<0b0010100, 0b101, OPC_OP_IMM_32, "gorciw">, Sched<[]>; + + def SHFLW : RVBInstR<0b0000100, 0b001, "shflw">, Sched<[]>; + def UNSHFLW : RVBInstR<0b0000100, 0b101, "unshflw">, Sched<[]>; +} + +// Polynomial Reduction Instructions + +let Predicates = [HasStdExtZbr] in { + def CRC32B : RVBInstFunct12<0b011000010000, 0b001, OPC_OP_IMM, "crc32.b">, Sched<[]>; + def CRC32H : RVBInstFunct12<0b011000010001, 0b001, OPC_OP_IMM, "crc32.h">, Sched<[]>; + def CRC32W : RVBInstFunct12<0b011000010010, 0b001, OPC_OP_IMM, "crc32.w">, Sched<[]>; + + def CRC32CB : RVBInstFunct12<0b011000011000, 0b001, OPC_OP_IMM, "crc32c.b">, Sched<[]>; + def CRC32CH : RVBInstFunct12<0b011000011001, 0b001, OPC_OP_IMM, "crc32c.h">, Sched<[]>; + def CRC32CW : RVBInstFunct12<0b011000011010, 0b001, OPC_OP_IMM, "crc32c.w">, Sched<[]>; +} + +let Predicates = [HasStdExtZbr, IsRV64] in { + def CRC32D : RVBInstFunct12<0b011000010011, 0b001, OPC_OP_IMM, "crc32.d">, Sched<[]>; + def CRC32CD : RVBInstFunct12<0b011000011011, 0b001, OPC_OP_IMM, "crc32c.d">, Sched<[]>; +} + +// Single Bit Instructions + +let Predicates = [HasStdExtZbs] in { + def SBSET : ALU_rr<0b0010100, 0b001, "sbset">, Sched<[]>; + def SBCLR : ALU_rr<0b0100100, 0b001, "sbclr">, Sched<[]>; + def SBINV : ALU_rr<0b0110100, 0b001, "sbinv">, Sched<[]>; + def SBEXT : ALU_rr<0b0100100, 0b101, "sbext">, Sched<[]>; + + def SBSETI : RVBInstImm7<0b00101, 0b001, OPC_OP_IMM, "sbseti">, Sched<[]>; + def SBCLRI : RVBInstImm7<0b01001, 0b001, OPC_OP_IMM, "sbclri">, Sched<[]>; + def SBINVI : RVBInstImm7<0b01101, 0b001, OPC_OP_IMM, "sbinvi">, Sched<[]>; + def SBEXTI : RVBInstImm7<0b01001, 0b101, OPC_OP_IMM, "sbexti">, Sched<[]>; +} + +let Predicates = [HasStdExtZbs, IsRV64] in { + def SBSETW : RVBInstR<0b0010100, 0b001, "sbsetw">, Sched<[]>; + def SBCLRW : RVBInstR<0b0100100, 0b001, "sbclrw">, Sched<[]>; + def SBINVW : RVBInstR<0b0110100, 0b001, "sbinvw">, Sched<[]>; + def SBEXTW : RVBInstR<0b0100100, 0b101, "sbextw">, Sched<[]>; + + def SBSETIW : RVBInstImm5<0b0010100, 0b001, OPC_OP_IMM_32, "sbsetiw">, Sched<[]>; + def SBCLRIW : RVBInstImm5<0b0100100, 0b001, OPC_OP_IMM_32, "sbclriw">, Sched<[]>; + def SBINVIW : RVBInstImm5<0b0110100, 0b001, OPC_OP_IMM_32, "sbinviw">, Sched<[]>; +} + +// Ternary Instructions + +let Predicates = [HasStdExtZbt] in { + def CMIX : RVBInstR4Reg<0b11, 0b001, OPC_OP, "cmix", "$rd, $rs2, $rs1, $rs3">, Sched<[]>; + def CMOV : RVBInstR4Reg<0b11, 0b101, OPC_OP, "cmov", "$rd, $rs2, $rs1, $rs3">, Sched<[]>; + def FSL : RVBInstR4Reg<0b10, 0b001, OPC_OP, "fsl", "$rd, $rs1, $rs3, $rs2">, Sched<[]>; + def FSR : RVBInstR4Reg<0b10, 0b101, OPC_OP, "fsr", "$rd, $rs1, $rs3, $rs2">, Sched<[]>; + def FSRI : RVBInstR4Imm6<0b1, 0b101, OPC_OP_IMM, "fsri">, Sched<[]>; +} + +let Predicates = [HasStdExtZbt, IsRV64] in { + def FSLW : RVBInstR4Reg<0b10, 0b001, OPC_OP_32, "fslw", "$rd, $rs1, $rs3, $rs2">, Sched<[]>; + def FSRW : RVBInstR4Reg<0b10, 0b101, OPC_OP_32, "fsrw", "$rd, $rs1, $rs3, $rs2">, Sched<[]>; + def FSRIW : RVBInstR4Imm<0b10, 0b101, OPC_OP_IMM_32, "fsriw">, Sched<[]>; +} + +//===----------------------------------------------------------------------===// +// Future compressed instructions +//===----------------------------------------------------------------------===// + +class RVBInstC funct2, string opcodestr> + : RVInst16<(outs GPR:$rs_wb), (ins GPR:$rs), opcodestr, "$rs", [], + InstFormatCR> { + bits<3> rs; + let Constraints = "$rs = $rs_wb"; + + let Inst{12-15} = 0b0110; + let Inst{10-11} = funct2; + let Inst{7-9} = rs; + let Inst{0-6} = 0b0000001; +} + +let Predicates = [HasStdExtB, HasStdExtC] in { + def CNOT : RVBInstC<00, "c.not">, Sched<[]>; +} + +let Predicates = [HasStdExtB, HasStdExtC, IsRV64] in { + def CZESTW : RVBInstC<01, "c.zest.w">, Sched<[]>; +} +} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 + +//===----------------------------------------------------------------------===// +// Pseudo Instructions +//===----------------------------------------------------------------------===// + +let Predicates = [HasStdExtZbb, IsRV32] in { + def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF)>; + def : InstAlias<"zext.h $rd, $rs", (PACK GPR:$rd, GPR:$rs, X0)>; +} + +let Predicates = [HasStdExtZbb, IsRV64] in { + def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF)>; + def : InstAlias<"zext.h $rd, $rs", (PACKW GPR:$rd, GPR:$rs, X0)>; + def : InstAlias<"zext.w $rd, $rs", (PACK GPR:$rd, GPR:$rs, X0)>; + def : InstAlias<"sext.w $rd, $rs", (ADDIW GPR:$rd, GPR:$rs, 0x0)>; +} + +let Predicates = [HasStdExtZbbOrZbp, IsRV32] in { + def : InstAlias<"rev $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11111)>, Sched<[]>; + def : InstAlias<"rev2 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11110)>, Sched<[]>; + def : InstAlias<"rev4 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11100)>, Sched<[]>; + def : InstAlias<"rev8 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11000)>, Sched<[]>; + def : InstAlias<"rev16 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b10000)>, Sched<[]>; + + def : InstAlias<"orc $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11111)>, Sched<[]>; + def : InstAlias<"orc2 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11110)>, Sched<[]>; + def : InstAlias<"orc4 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11100)>, Sched<[]>; + def : InstAlias<"orc8 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11000)>, Sched<[]>; + def : InstAlias<"orc16 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b10000)>, Sched<[]>; + + def : InstAlias<"zip $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1111)>, Sched<[]>; + def : InstAlias<"zip2 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1110)>, Sched<[]>; + def : InstAlias<"zip4 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1100)>, Sched<[]>; + def : InstAlias<"zip8 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1000)>, Sched<[]>; + def : InstAlias<"unzip $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1111)>, Sched<[]>; + def : InstAlias<"unzip2 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1110)>, Sched<[]>; + def : InstAlias<"unzip4 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1100)>, Sched<[]>; + def : InstAlias<"unzip8 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1000)>, Sched<[]>; +} + +let Predicates = [HasStdExtZbbOrZbp, IsRV64] in { + def : InstAlias<"rev.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011111)>, Sched<[]>; + def : InstAlias<"rev2.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011110)>, Sched<[]>; + def : InstAlias<"rev4.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011100)>, Sched<[]>; + def : InstAlias<"rev8.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011000)>, Sched<[]>; + def : InstAlias<"rev16.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b010000)>, Sched<[]>; + def : InstAlias<"rev $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b111111)>, Sched<[]>; + def : InstAlias<"rev2 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b111110)>, Sched<[]>; + def : InstAlias<"rev4 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b111100)>, Sched<[]>; + def : InstAlias<"rev8 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b111000)>, Sched<[]>; + def : InstAlias<"rev16 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b110000)>, Sched<[]>; + def : InstAlias<"rev32 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b100000)>, Sched<[]>; + + def : InstAlias<"orc.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b011111)>, Sched<[]>; + def : InstAlias<"orc2.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b011110)>, Sched<[]>; + def : InstAlias<"orc4.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b011100)>, Sched<[]>; + def : InstAlias<"orc8.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b011000)>, Sched<[]>; + def : InstAlias<"orc16.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b010000)>, Sched<[]>; + def : InstAlias<"orc $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b111111)>, Sched<[]>; + def : InstAlias<"orc2 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b111110)>, Sched<[]>; + def : InstAlias<"orc4 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b111100)>, Sched<[]>; + def : InstAlias<"orc8 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b111000)>, Sched<[]>; + def : InstAlias<"orc16 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b110000)>, Sched<[]>; + def : InstAlias<"orc32 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b100000)>, Sched<[]>; + + def : InstAlias<"zip.w $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b01111)>, Sched<[]>; + def : InstAlias<"zip2.w $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b01110)>, Sched<[]>; + def : InstAlias<"zip4.w $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b01100)>, Sched<[]>; + def : InstAlias<"zip8.w $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b01000)>, Sched<[]>; + def : InstAlias<"unzip.w $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b01111)>, Sched<[]>; + def : InstAlias<"unzip2.w $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b01110)>, Sched<[]>; + def : InstAlias<"unzip4.w $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b01100)>, Sched<[]>; + def : InstAlias<"unzip8.w $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b01000)>, Sched<[]>; + def : InstAlias<"zip $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b11111)>, Sched<[]>; + def : InstAlias<"zip2 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b11110)>, Sched<[]>; + def : InstAlias<"zip4 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b11100)>, Sched<[]>; + def : InstAlias<"zip8 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b11000)>, Sched<[]>; + def : InstAlias<"zip16 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b10000)>, Sched<[]>; + def : InstAlias<"unzip $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b11111)>, Sched<[]>; + def : InstAlias<"unzip2 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b11110)>, Sched<[]>; + def : InstAlias<"unzip4 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b11100)>, Sched<[]>; + def : InstAlias<"unzip8 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b11000)>, Sched<[]>; + def : InstAlias<"unzip16 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b10000)>, Sched<[]>; +} + +let Predicates = [HasStdExtZbbOrZbp] in { + def : InstAlias<"rev.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01111)>, Sched<[]>; + def : InstAlias<"rev.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00111)>, Sched<[]>; + def : InstAlias<"rev.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00011)>, Sched<[]>; + def : InstAlias<"rev.p $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00001)>, Sched<[]>; + def : InstAlias<"rev2.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01110)>, Sched<[]>; + def : InstAlias<"rev2.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00110)>, Sched<[]>; + def : InstAlias<"rev2.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00010)>, Sched<[]>; + def : InstAlias<"rev4.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01100)>, Sched<[]>; + def : InstAlias<"rev4.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00100)>, Sched<[]>; + def : InstAlias<"rev8.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01000)>, Sched<[]>; + + def : InstAlias<"orc.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01111)>, Sched<[]>; + def : InstAlias<"orc.b $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00111)>, Sched<[]>; + def : InstAlias<"orc.n $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00011)>, Sched<[]>; + def : InstAlias<"orc.p $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00001)>, Sched<[]>; + def : InstAlias<"orc2.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01110)>, Sched<[]>; + def : InstAlias<"orc2.b $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00110)>, Sched<[]>; + def : InstAlias<"orc2.n $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00010)>, Sched<[]>; + def : InstAlias<"orc4.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01100)>, Sched<[]>; + def : InstAlias<"orc4.b $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00100)>, Sched<[]>; + def : InstAlias<"orc8.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01000)>, Sched<[]>; + + def : InstAlias<"zip.h $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0111)>, Sched<[]>; + def : InstAlias<"zip.b $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0011)>, Sched<[]>; + def : InstAlias<"zip.n $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0001)>, Sched<[]>; + def : InstAlias<"zip2.h $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0110)>, Sched<[]>; + def : InstAlias<"zip2.b $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0010)>, Sched<[]>; + def : InstAlias<"zip4.h $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0100)>, Sched<[]>; + def : InstAlias<"unzip.h $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0111)>, Sched<[]>; + def : InstAlias<"unzip.b $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0011)>, Sched<[]>; + def : InstAlias<"unzip.n $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0001)>, Sched<[]>; + def : InstAlias<"unzip2.h $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0110)>, Sched<[]>; + def : InstAlias<"unzip2.b $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0010)>, Sched<[]>; + def : InstAlias<"unzip4.h $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0100)>, Sched<[]>; +} diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -39,6 +39,16 @@ bool HasStdExtF = false; bool HasStdExtD = false; bool HasStdExtC = false; + bool HasStdExtB = false; + bool HasStdExtZbb = false; + bool HasStdExtZbc = false; + bool HasStdExtZbe = false; + bool HasStdExtZbf = false; + bool HasStdExtZbm = false; + bool HasStdExtZbp = false; + bool HasStdExtZbr = false; + bool HasStdExtZbs = false; + bool HasStdExtZbt = false; bool HasRV64 = false; bool IsRV32E = false; bool EnableLinkerRelax = false; @@ -87,6 +97,16 @@ bool hasStdExtF() const { return HasStdExtF; } bool hasStdExtD() const { return HasStdExtD; } bool hasStdExtC() const { return HasStdExtC; } + bool hasStdExtB() const { return HasStdExtB; } + bool hasStdExtZbb() const { return HasStdExtZbb; } + bool hasStdExtZbc() const { return HasStdExtZbc; } + bool hasStdExtZbe() const { return HasStdExtZbe; } + bool hasStdExtZbf() const { return HasStdExtZbf; } + bool hasStdExtZbm() const { return HasStdExtZbm; } + bool hasStdExtZbp() const { return HasStdExtZbp; } + bool hasStdExtZbr() const { return HasStdExtZbr; } + bool hasStdExtZbs() const { return HasStdExtZbs; } + bool hasStdExtZbt() const { return HasStdExtZbt; } bool is64Bit() const { return HasRV64; } bool isRV32E() const { return IsRV32E; } bool enableLinkerRelax() const { return EnableLinkerRelax; } diff --git a/llvm/test/MC/RISCV/rv32Zbb-invalid.s b/llvm/test/MC/RISCV/rv32Zbb-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32Zbb-invalid.s @@ -0,0 +1,28 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+b,zbb < %s 2>&1 | FileCheck %s + +# Too few operands +slo s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +sro s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +sloi s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +sroi s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too many operands +clz s0, s1, s2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction +# Too many operands +ctz s0, s1, s2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction +# Too many operands +pcnt s0, s1, s2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction +# Too few operands +min s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +max s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +minu s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +maxu s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too many operands +sext.b s0, s1, s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction +# Too many operands +sext.h s0, s1, s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv32Zbb-valid.s b/llvm/test/MC/RISCV/rv32Zbb-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32Zbb-valid.s @@ -0,0 +1,51 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+b -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+b < %s \ +# RUN: | llvm-objdump -mattr=+b -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zbb -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zbb < %s \ +# RUN: | llvm-objdump -mattr=+zbb -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: slo t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x20] +slo t0, t1, t2 +# CHECK-ASM-AND-OBJ: sro t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x20] +sro t0, t1, t2 +# CHECK-ASM-AND-OBJ: sloi t0, t1, 0 +# CHECK-ASM: encoding: [0x93,0x12,0x03,0x20] +sloi t0, t1, 0 +# CHECK-ASM-AND-OBJ: sroi t0, t1, 0 +# CHECK-ASM: encoding: [0x93,0x52,0x03,0x20] +sroi t0, t1, 0 +# CHECK-ASM-AND-OBJ: clz t0, t1 +# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60] +clz t0, t1 +# CHECK-ASM-AND-OBJ: ctz t0, t1 +# CHECK-ASM: encoding: [0x93,0x12,0x13,0x60] +ctz t0, t1 +# CHECK-ASM-AND-OBJ: pcnt t0, t1 +# CHECK-ASM: encoding: [0x93,0x12,0x23,0x60] +pcnt t0, t1 +# CHECK-ASM-AND-OBJ: min t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a] +min t0, t1, t2 +# CHECK-ASM-AND-OBJ: max t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x0a] +max t0, t1, t2 +# CHECK-ASM-AND-OBJ: minu t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a] +minu t0, t1, t2 +# CHECK-ASM-AND-OBJ: maxu t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x0a] +maxu t0, t1, t2 +# CHECK-ASM-AND-OBJ: sext.b t0, t1 +# CHECK-ASM: encoding: [0x93,0x12,0x43,0x60] +sext.b t0, t1 +# CHECK-ASM-AND-OBJ: sext.h t0, t1 +# CHECK-ASM: encoding: [0x93,0x12,0x53,0x60] +sext.h t0, t1 diff --git a/llvm/test/MC/RISCV/rv32Zbbp-invalid.s b/llvm/test/MC/RISCV/rv32Zbbp-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32Zbbp-invalid.s @@ -0,0 +1,20 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+b,zbb,zbp < %s 2>&1 | FileCheck %s + +# Too few operands +andn s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +orn s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +xnor s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +rol s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +ror s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +rori s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +pack s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +packu s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +packh s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/rv32Zbbp-valid.s b/llvm/test/MC/RISCV/rv32Zbbp-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32Zbbp-valid.s @@ -0,0 +1,51 @@ +# With B extension: +# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \ +# RUN: | llvm-objdump -mattr=+b -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# With Bitmanip base extension: +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zbb -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbb < %s \ +# RUN: | llvm-objdump -mattr=+zbb -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# With Bitmanip permutation extension: +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zbp -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbp < %s \ +# RUN: | llvm-objdump -mattr=+zbp -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: andn t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x40] +andn t0, t1, t2 +# CHECK-ASM-AND-OBJ: orn t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x40] +orn t0, t1, t2 +# CHECK-ASM-AND-OBJ: xnor t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x40] +xnor t0, t1, t2 +# CHECK-ASM-AND-OBJ: rol t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x60] +rol t0, t1, t2 +# CHECK-ASM-AND-OBJ: ror t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x60] +ror t0, t1, t2 +# CHECK-ASM-AND-OBJ: rori t0, t1, 31 +# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x61] +rori t0, t1, 31 +# CHECK-ASM-AND-OBJ: rori t0, t1, 0 +# CHECK-ASM: encoding: [0x93,0x52,0x03,0x60] +rori t0, t1, 0 +# CHECK-ASM-AND-OBJ: pack t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08] +pack t0, t1, t2 +# CHECK-ASM-AND-OBJ: packu t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x48] +packu t0, t1, t2 +# CHECK-ASM-AND-OBJ: packh t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x08] +packh t0, t1, t2 diff --git a/llvm/test/MC/RISCV/rv32Zbc-invalid.s b/llvm/test/MC/RISCV/rv32Zbc-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32Zbc-invalid.s @@ -0,0 +1,8 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+b,zbc < %s 2>&1 | FileCheck %s + +# Too few operands +clmul s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +clmulr s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +clmulh s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/rv32Zbc-valid.s b/llvm/test/MC/RISCV/rv32Zbc-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32Zbc-valid.s @@ -0,0 +1,23 @@ +# With B extension: +# RUN: llvm-mc %s -triple=riscv32 -mattr=+b -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+b < %s \ +# RUN: | llvm-objdump -mattr=+b -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# With Bitmanip carry-less multiply extension: +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zbc -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zbc < %s \ +# RUN: | llvm-objdump -mattr=+zbc -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: clmul t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x0a] +clmul t0, t1, t2 +# CHECK-ASM-AND-OBJ: clmulr t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x22,0x73,0x0a] +clmulr t0, t1, t2 +# CHECK-ASM-AND-OBJ: clmulh t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x32,0x73,0x0a] +clmulh t0, t1, t2 diff --git a/llvm/test/MC/RISCV/rv32Zbe-invalid.s b/llvm/test/MC/RISCV/rv32Zbe-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32Zbe-invalid.s @@ -0,0 +1,6 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+b,zbe < %s 2>&1 | FileCheck %s + +# Too few operands +bdep s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +bext s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/rv32Zbe-valid.s b/llvm/test/MC/RISCV/rv32Zbe-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32Zbe-valid.s @@ -0,0 +1,20 @@ +# With B extension: +# RUN: llvm-mc %s -triple=riscv32 -mattr=+b -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+b < %s \ +# RUN: | llvm-objdump -mattr=+b -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# With Bitmanip extract/deposit extension: +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zbe -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zbe < %s \ +# RUN: | llvm-objdump -mattr=+zbe -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: bdep t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x48] +bdep t0, t1, t2 +# CHECK-ASM-AND-OBJ: bext t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x08] +bext t0, t1, t2 diff --git a/llvm/test/MC/RISCV/rv32Zbf-invalid.s b/llvm/test/MC/RISCV/rv32Zbf-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32Zbf-invalid.s @@ -0,0 +1,4 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+b,zbf < %s 2>&1 | FileCheck %s + +# Too few operands +bfp s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/rv32Zbf-valid.s b/llvm/test/MC/RISCV/rv32Zbf-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32Zbf-valid.s @@ -0,0 +1,17 @@ +# With B extension: +# RUN: llvm-mc %s -triple=riscv32 -mattr=+b -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+b < %s \ +# RUN: | llvm-objdump -mattr=+b -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# With Bit-Field extension: +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zbf -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zbf < %s \ +# RUN: | llvm-objdump -mattr=+zbf -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: bfp t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x48] +bfp t0, t1, t2 diff --git a/llvm/test/MC/RISCV/rv32Zbp-invalid.s b/llvm/test/MC/RISCV/rv32Zbp-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32Zbp-invalid.s @@ -0,0 +1,14 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+b,zbp < %s 2>&1 | FileCheck %s + +# Too few operands +grev s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +grevi s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +shfl s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +unshfl s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +shfli t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +unshfli t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/rv32Zbp-valid.s b/llvm/test/MC/RISCV/rv32Zbp-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32Zbp-valid.s @@ -0,0 +1,31 @@ +# With Bitmanip permutation extension: +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zbp -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zbp < %s \ +# RUN: | llvm-objdump -mattr=+zbp -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: grev t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x68] +grev t0, t1, t2 +# CHECK-ASM-AND-OBJ: gorc t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x28] +gorc t0, t1, t2 +# CHECK-ASM-AND-OBJ: grevi t0, t1, 0 +# CHECK-ASM: encoding: [0x93,0x52,0x03,0x68] +grevi t0, t1, 0 +# CHECK-ASM-AND-OBJ: gorci t0, t1, 0 +# CHECK-ASM: encoding: [0x93,0x52,0x03,0x28] +gorci t0, t1, 0 +# CHECK-ASM-AND-OBJ: shfl t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x08] +shfl t0, t1, t2 +# CHECK-ASM-AND-OBJ: unshfl t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x08] +unshfl t0, t1, t2 +# CHECK-ASM-AND-OBJ: shfli t0, t1, 0 +# CHECK-ASM: encoding: [0x93,0x12,0x03,0x08] +shfli t0, t1, 0 +# CHECK-ASM-AND-OBJ: unshfli t0, t1, 0 +# CHECK-ASM: encoding: [0x93,0x52,0x03,0x08] +unshfli t0, t1, 0 diff --git a/llvm/test/MC/RISCV/rv32Zbr-invalid.s b/llvm/test/MC/RISCV/rv32Zbr-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32Zbr-invalid.s @@ -0,0 +1,14 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+b,zbr < %s 2>&1 | FileCheck %s + +# Too many operands +crc32.b s0, s1, s2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction +# Too many operands +crc32.h s0, s1, s2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction +# Too many operands +crc32.w s0, s1, s2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction +# Too many operands +crc32c.b s0, s1, s2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction +# Too many operands +crc32c.h s0, s1, s2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction +# Too many operands +crc32c.w s0, s1, s2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv32Zbr-valid.s b/llvm/test/MC/RISCV/rv32Zbr-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32Zbr-valid.s @@ -0,0 +1,32 @@ +# With B extension: +# RUN: llvm-mc %s -triple=riscv32 -mattr=+b -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+b < %s \ +# RUN: | llvm-objdump -mattr=+b -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# With Bitmanip CRC extension: +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zbr -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zbr < %s \ +# RUN: | llvm-objdump -mattr=+zbr -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: crc32.b t0, t1 +# CHECK-ASM: encoding: [0x93,0x12,0x03,0x61] +crc32.b t0, t1 +# CHECK-ASM-AND-OBJ: crc32.h t0, t1 +# CHECK-ASM: encoding: [0x93,0x12,0x13,0x61] +crc32.h t0, t1 +# CHECK-ASM-AND-OBJ: crc32.w t0, t1 +# CHECK-ASM: encoding: [0x93,0x12,0x23,0x61] +crc32.w t0, t1 +# CHECK-ASM-AND-OBJ: crc32c.b t0, t1 +# CHECK-ASM: encoding: [0x93,0x12,0x83,0x61] +crc32c.b t0, t1 +# CHECK-ASM-AND-OBJ: crc32c.h t0, t1 +# CHECK-ASM: encoding: [0x93,0x12,0x93,0x61] +crc32c.h t0, t1 +# CHECK-ASM-AND-OBJ: crc32c.w t0, t1 +# CHECK-ASM: encoding: [0x93,0x12,0xa3,0x61] +crc32c.w t0, t1 diff --git a/llvm/test/MC/RISCV/rv32Zbs-invalid.s b/llvm/test/MC/RISCV/rv32Zbs-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32Zbs-invalid.s @@ -0,0 +1,18 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+b,zbs < %s 2>&1 | FileCheck %s + +# Too few operands +sbset s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +sbclr s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +sbinv s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +sbext s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +sbseti s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +sbclri s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +sbinvi s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +sbexti s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/rv32Zbs-valid.s b/llvm/test/MC/RISCV/rv32Zbs-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32Zbs-valid.s @@ -0,0 +1,38 @@ +# With B extension: +# RUN: llvm-mc %s -triple=riscv32 -mattr=+b -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+b < %s \ +# RUN: | llvm-objdump -mattr=+b -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# With Bitmanip single bit extension: +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zbs -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zbs < %s \ +# RUN: | llvm-objdump -mattr=+zbs -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: sbset t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x28] +sbset t0, t1, t2 +# CHECK-ASM-AND-OBJ: sbclr t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x48] +sbclr t0, t1, t2 +# CHECK-ASM-AND-OBJ: sbinv t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x68] +sbinv t0, t1, t2 +# CHECK-ASM-AND-OBJ: sbext t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x48] +sbext t0, t1, t2 +# CHECK-ASM-AND-OBJ: sbseti t0, t1, 1 +# CHECK-ASM: encoding: [0x93,0x12,0x13,0x28] +sbseti t0, t1, 1 +# CHECK-ASM-AND-OBJ: sbclri t0, t1, 1 +# CHECK-ASM: encoding: [0x93,0x12,0x13,0x48] +sbclri t0, t1, 1 +# CHECK-ASM-AND-OBJ: sbinvi t0, t1, 1 +# CHECK-ASM: encoding: [0x93,0x12,0x13,0x68] +sbinvi t0, t1, 1 +# CHECK-ASM-AND-OBJ: sbexti t0, t1, 1 +# CHECK-ASM: encoding: [0x93,0x52,0x13,0x48] +sbexti t0, t1, 1 diff --git a/llvm/test/MC/RISCV/rv32Zbt-invalid.s b/llvm/test/MC/RISCV/rv32Zbt-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32Zbt-invalid.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+b,zbt < %s 2>&1 | FileCheck %s + +# Too few operands +cmix s0, s1, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +cmov s0, s1, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +fsl s0, s1, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +fsr s0, s1, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/rv32Zbt-valid.s b/llvm/test/MC/RISCV/rv32Zbt-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32Zbt-valid.s @@ -0,0 +1,26 @@ +# With B extension: +# RUN: llvm-mc %s -triple=riscv32 -mattr=+b -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+b < %s \ +# RUN: | llvm-objdump -mattr=+b -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# With Bitmanip ternary extension: +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zbt -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zbt < %s \ +# RUN: | llvm-objdump -mattr=+zbt -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3 +# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6] +cmix t0, t1, t2, t3 +# CHECK-ASM-AND-OBJ: cmov t0, t1, t2, t3 +# CHECK-ASM: encoding: [0xb3,0xd2,0x63,0xe6] +cmov t0, t1, t2, t3 +# CHECK-ASM-AND-OBJ: fsl t0, t1, t2, t3 +# CHECK-ASM: encoding: [0xb3,0x12,0xc3,0x3d] +fsl t0, t1, t2, t3 +# CHECK-ASM-AND-OBJ: fsr t0, t1, t2, t3 +# CHECK-ASM: encoding: [0xb3,0x52,0xc3,0x3d] +fsr t0, t1, t2, t3 diff --git a/llvm/test/MC/RISCV/rv32b-aliases-valid.s b/llvm/test/MC/RISCV/rv32b-aliases-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32b-aliases-valid.s @@ -0,0 +1,224 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+b -riscv-no-aliases \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s +# RUN: llvm-mc %s -triple=riscv32 -mattr=+b \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+b < %s \ +# RUN: | llvm-objdump -d -r -riscv-no-aliases -mattr=+b - \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+b < %s \ +# RUN: | llvm-objdump -d -r -mattr=+b - \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s + +# The following check prefixes are used in this test: +# CHECK-S-OBJ Match both the .s and objdumped object output with +# aliases enabled +# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with +# aliases disabled + +# CHECK-S-OBJ-NOALIAS: andi t0, t1, 255 +# CHECK-S-OBJ: zext.b t0, t1 +zext.b x5, x6 + +# CHECK-S-OBJ-NOALIAS: pack t0, t1, zero +# CHECK-S-OBJ: zext.h t0, t1 +zext.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 31 +# CHECK-S-OBJ: rev t0, t1 +rev x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 15 +# CHECK-S-OBJ: rev.h t0, t1 +rev.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 7 +# CHECK-S-OBJ: rev.b t0, t1 +rev.b x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 3 +# CHECK-S-OBJ: rev.n t0, t1 +rev.n x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 1 +# CHECK-S-OBJ: rev.p t0, t1 +rev.p x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 30 +# CHECK-S-OBJ: rev2 t0, t1 +rev2 x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 14 +# CHECK-S-OBJ: rev2.h t0, t1 +rev2.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 6 +# CHECK-S-OBJ: rev2.b t0, t1 +rev2.b x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 2 +# CHECK-S-OBJ: rev2.n t0, t1 +rev2.n x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 28 +# CHECK-S-OBJ: rev4 t0, t1 +rev4 x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 12 +# CHECK-S-OBJ: rev4.h t0, t1 +rev4.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 4 +# CHECK-S-OBJ: rev4.b t0, t1 +rev4.b x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 24 +# CHECK-S-OBJ: rev8 t0, t1 +rev8 x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8 +# CHECK-S-OBJ: rev8.h t0, t1 +rev8.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 16 +# CHECK-S-OBJ: rev16 t0, t1 +rev16 x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 31 +# CHECK-S-OBJ: orc t0, t1 +orc x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 15 +# CHECK-S-OBJ: orc.h t0, t1 +orc.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 7 +# CHECK-S-OBJ: orc.b t0, t1 +orc.b x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 3 +# CHECK-S-OBJ: orc.n t0, t1 +orc.n x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 1 +# CHECK-S-OBJ: orc.p t0, t1 +orc.p x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 30 +# CHECK-S-OBJ: orc2 t0, t1 +orc2 x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 14 +# CHECK-S-OBJ: orc2.h t0, t1 +orc2.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 6 +# CHECK-S-OBJ: orc2.b t0, t1 +orc2.b x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 2 +# CHECK-S-OBJ: orc2.n t0, t1 +orc2.n x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 28 +# CHECK-S-OBJ: orc4 t0, t1 +orc4 x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 12 +# CHECK-S-OBJ: orc4.h t0, t1 +orc4.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 4 +# CHECK-S-OBJ: orc4.b t0, t1 +orc4.b x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 24 +# CHECK-S-OBJ: orc8 t0, t1 +orc8 x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 8 +# CHECK-S-OBJ: orc8.h t0, t1 +orc8.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 16 +# CHECK-S-OBJ: orc16 t0, t1 +orc16 x5, x6 + +# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 15 +# CHECK-S-OBJ: zip t0, t1 +zip x5, x6 + +# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 7 +# CHECK-S-OBJ: zip.h t0, t1 +zip.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 3 +# CHECK-S-OBJ: zip.b t0, t1 +zip.b x5, x6 + +# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 1 +# CHECK-S-OBJ: zip.n t0, t1 +zip.n x5, x6 + +# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 14 +# CHECK-S-OBJ: zip2 t0, t1 +zip2 x5, x6 + +# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 6 +# CHECK-S-OBJ: zip2.h t0, t1 +zip2.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 2 +# CHECK-S-OBJ: zip2.b t0, t1 +zip2.b x5, x6 + +# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 12 +# CHECK-S-OBJ: zip4 t0, t1 +zip4 x5, x6 + +# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 4 +# CHECK-S-OBJ: zip4.h t0, t1 +zip4.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 8 +# CHECK-S-OBJ: zip8 t0, t1 +zip8 x5, x6 + +# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 15 +# CHECK-S-OBJ: unzip t0, t1 +unzip x5, x6 + +# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 7 +# CHECK-S-OBJ: unzip.h t0, t1 +unzip.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 3 +# CHECK-S-OBJ: unzip.b t0, t1 +unzip.b x5, x6 + +# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 1 +# CHECK-S-OBJ: unzip.n t0, t1 +unzip.n x5, x6 + +# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 14 +# CHECK-S-OBJ: unzip2 t0, t1 +unzip2 x5, x6 + +# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 6 +# CHECK-S-OBJ: unzip2.h t0, t1 +unzip2.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 2 +# CHECK-S-OBJ: unzip2.b t0, t1 +unzip2.b x5, x6 + +# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 12 +# CHECK-S-OBJ: unzip4 t0, t1 +unzip4 x5, x6 + +# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 4 +# CHECK-S-OBJ: unzip4.h t0, t1 +unzip4.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 8 +# CHECK-S-OBJ: unzip8 t0, t1 +unzip8 x5, x6 diff --git a/llvm/test/MC/RISCV/rv32bc-invalid.s b/llvm/test/MC/RISCV/rv32bc-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32bc-invalid.s @@ -0,0 +1,4 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+b,c < %s 2>&1 | FileCheck %s + +# Too many operands +c.not s0, s1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv32bc-valid.s b/llvm/test/MC/RISCV/rv32bc-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32bc-valid.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+b,c -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+b,c < %s \ +# RUN: | llvm-objdump -mattr=+b,c -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: c.not t0 +# CHECK-ASM: encoding: [0xc0,0x62] +c.not t0 diff --git a/llvm/test/MC/RISCV/rv64Zbb-invalid.s b/llvm/test/MC/RISCV/rv64Zbb-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64Zbb-invalid.s @@ -0,0 +1,28 @@ +# RUN: not llvm-mc -triple riscv64 -mattr=+b,zbb < %s 2>&1 | FileCheck %s + +# Too many operands +clzw s0, s1, s2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction +# Too many operands +ctzw s0, s1, s2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction +# Too many operands +pcntw s0, s1, s2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction +# Too few operands +slow t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +srow t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +sloiw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +sroiw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +addiwu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +slliu.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +addwu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +subwu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +addu.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +subu.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/rv64Zbb-valid.s b/llvm/test/MC/RISCV/rv64Zbb-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64Zbb-valid.s @@ -0,0 +1,53 @@ +# With B extension: +# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \ +# RUN: | llvm-objdump -mattr=+b -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# With Bitmanip base extension: +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zbb -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbb < %s \ +# RUN: | llvm-objdump -mattr=+zbb -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: clzw t0, t1 +# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x60] +clzw t0, t1 +# CHECK-ASM-AND-OBJ: ctzw t0, t1 +# CHECK-ASM: encoding: [0x9b,0x12,0x13,0x60] +ctzw t0, t1 +# CHECK-ASM-AND-OBJ: pcntw t0, t1 +# CHECK-ASM: encoding: [0x9b,0x12,0x23,0x60] +pcntw t0, t1 +# CHECK-ASM-AND-OBJ: slow t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x20] +slow t0, t1, t2 +# CHECK-ASM-AND-OBJ: srow t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x20] +srow t0, t1, t2 +# CHECK-ASM-AND-OBJ: sloiw t0, t1, 0 +# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x20] +sloiw t0, t1, 0 +# CHECK-ASM-AND-OBJ: sroiw t0, t1, 0 +# CHECK-ASM: encoding: [0x9b,0x52,0x03,0x20] +sroiw t0, t1, 0 +# CHECK-ASM-AND-OBJ: addiwu t0, t1, 0 +# CHECK-ASM: encoding: [0x9b,0x42,0x03,0x00] +addiwu t0, t1, 0 +# CHECK-ASM-AND-OBJ: slliu.w t0, t1, 0 +# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x08] +slliu.w t0, t1, 0 +# CHECK-ASM-AND-OBJ: addwu t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x0a] +addwu t0, t1, t2 +# CHECK-ASM-AND-OBJ: subwu t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x4a] +subwu t0, t1, t2 +# CHECK-ASM-AND-OBJ: addu.w t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x08] +addu.w t0, t1, t2 +# CHECK-ASM-AND-OBJ: subu.w t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x48] +subu.w t0, t1, t2 diff --git a/llvm/test/MC/RISCV/rv64Zbbp-invalid.s b/llvm/test/MC/RISCV/rv64Zbbp-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64Zbbp-invalid.s @@ -0,0 +1,12 @@ +# RUN: not llvm-mc -triple riscv64 -mattr=+b,zbb,zbp < %s 2>&1 | FileCheck %s + +# Too few operands +rolw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +rorw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +roriw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +packw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +packuw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/rv64Zbbp-valid.s b/llvm/test/MC/RISCV/rv64Zbbp-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64Zbbp-valid.s @@ -0,0 +1,39 @@ +# With B extension: +# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \ +# RUN: | llvm-objdump -mattr=+b -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# With Bitmanip base extension: +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zbb -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbb < %s \ +# RUN: | llvm-objdump -mattr=+zbb -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# With Bitmanip permutation extension: +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zbp -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbp < %s \ +# RUN: | llvm-objdump -mattr=+zbp -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: rolw t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x60] +rolw t0, t1, t2 +# CHECK-ASM-AND-OBJ: rorw t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x60] +rorw t0, t1, t2 +# CHECK-ASM-AND-OBJ: roriw t0, t1, 31 +# CHECK-ASM: encoding: [0x9b,0x52,0xf3,0x61] +roriw t0, t1, 31 +# CHECK-ASM-AND-OBJ: roriw t0, t1, 0 +# CHECK-ASM: encoding: [0x9b,0x52,0x03,0x60] +roriw t0, t1, 0 +# CHECK-ASM-AND-OBJ: packw t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x42,0x73,0x08] +packw t0, t1, t2 +# CHECK-ASM-AND-OBJ: packuw t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x42,0x73,0x48] +packuw t0, t1, t2 diff --git a/llvm/test/MC/RISCV/rv64Zbc-invalid.s b/llvm/test/MC/RISCV/rv64Zbc-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64Zbc-invalid.s @@ -0,0 +1,8 @@ +# RUN: not llvm-mc -triple riscv64 -mattr=+b,zbc < %s 2>&1 | FileCheck %s + +# Too few operands +clmulw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +clmulrw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +clmulhw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/rv64Zbc-valid.s b/llvm/test/MC/RISCV/rv64Zbc-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64Zbc-valid.s @@ -0,0 +1,23 @@ +# With B extension: +# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \ +# RUN: | llvm-objdump -mattr=+b -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# With Bitmanip carry-less multiply extension: +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zbc -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbc < %s \ +# RUN: | llvm-objdump -mattr=+zbc -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: clmulw t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x0a] +clmulw t0, t1, t2 +# CHECK-ASM-AND-OBJ: clmulrw t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x22,0x73,0x0a] +clmulrw t0, t1, t2 +# CHECK-ASM-AND-OBJ: clmulhw t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x32,0x73,0x0a] +clmulhw t0, t1, t2 diff --git a/llvm/test/MC/RISCV/rv64Zbe-invalid.s b/llvm/test/MC/RISCV/rv64Zbe-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64Zbe-invalid.s @@ -0,0 +1,6 @@ +# RUN: not llvm-mc -triple riscv64 -mattr=+b,zbe < %s 2>&1 | FileCheck %s + +# Too few operands +bdepw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +bextw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/rv64Zbe-valid.s b/llvm/test/MC/RISCV/rv64Zbe-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64Zbe-valid.s @@ -0,0 +1,20 @@ +# With B extension: +# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \ +# RUN: | llvm-objdump -mattr=+b -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# With Bitmanip extract/deposit extension: +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zbe -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbe < %s \ +# RUN: | llvm-objdump -mattr=+zbe -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: bdepw t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x62,0x73,0x48] +bdepw t0, t1, t2 +# CHECK-ASM-AND-OBJ: bextw t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x62,0x73,0x08] +bextw t0, t1, t2 diff --git a/llvm/test/MC/RISCV/rv64Zbf-invalid.s b/llvm/test/MC/RISCV/rv64Zbf-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64Zbf-invalid.s @@ -0,0 +1,4 @@ +# RUN: not llvm-mc -triple riscv64 -mattr=+b,zbf < %s 2>&1 | FileCheck %s + +# Too few operands +bfpw s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/rv64Zbf-valid.s b/llvm/test/MC/RISCV/rv64Zbf-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64Zbf-valid.s @@ -0,0 +1,17 @@ +# With B extension: +# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \ +# RUN: | llvm-objdump -mattr=+b -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# With Bit-Field extension: +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zbf -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbf < %s \ +# RUN: | llvm-objdump -mattr=+zbf -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: bfpw t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x72,0x73,0x48] +bfpw t0, t1, t2 diff --git a/llvm/test/MC/RISCV/rv64Zbm-invalid.s b/llvm/test/MC/RISCV/rv64Zbm-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64Zbm-invalid.s @@ -0,0 +1,8 @@ +# RUN: not llvm-mc -triple riscv64 -mattr=+b,zbm < %s 2>&1 | FileCheck %s + +# Too few operands +bmator s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +bmatxor s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too many operands +bmatflip s0, s1, s2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv64Zbm-valid.s b/llvm/test/MC/RISCV/rv64Zbm-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64Zbm-valid.s @@ -0,0 +1,23 @@ +# With B extension: +# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \ +# RUN: | llvm-objdump -mattr=+b -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# With Bitmanip matix extension: +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zbm -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbm < %s \ +# RUN: | llvm-objdump -mattr=+zbm -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: bmator t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x32,0x73,0x08] +bmator t0, t1, t2 +# CHECK-ASM-AND-OBJ: bmatxor t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x32,0x73,0x48] +bmatxor t0, t1, t2 +# CHECK-ASM-AND-OBJ: bmatflip t0, t1 +# CHECK-ASM: encoding: [0x93,0x12,0x33,0x60] +bmatflip t0, t1 diff --git a/llvm/test/MC/RISCV/rv64Zbp-invalid.s b/llvm/test/MC/RISCV/rv64Zbp-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64Zbp-invalid.s @@ -0,0 +1,14 @@ +# RUN: not llvm-mc -triple riscv64 -mattr=+b,zbp < %s 2>&1 | FileCheck %s + +# Too few operands +grevw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +gorcw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +greviw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +gorciw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +shflw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +unshflw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/rv64Zbp-valid.s b/llvm/test/MC/RISCV/rv64Zbp-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64Zbp-valid.s @@ -0,0 +1,25 @@ +# With Bitmanip permutation extension: +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zbp -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbp < %s \ +# RUN: | llvm-objdump -mattr=+zbp -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: grevw t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x68] +grevw t0, t1, t2 +# CHECK-ASM-AND-OBJ: gorcw t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x28] +gorcw t0, t1, t2 +# CHECK-ASM-AND-OBJ: greviw t0, t1, 0 +# CHECK-ASM: encoding: [0x9b,0x52,0x03,0x68] +greviw t0, t1, 0 +# CHECK-ASM-AND-OBJ: gorciw t0, t1, 0 +# CHECK-ASM: encoding: [0x9b,0x52,0x03,0x28] +gorciw t0, t1, 0 +# CHECK-ASM-AND-OBJ: shflw t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x08] +shflw t0, t1, t2 +# CHECK-ASM-AND-OBJ: unshflw t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x08] +unshflw t0, t1, t2 diff --git a/llvm/test/MC/RISCV/rv64Zbr-invalid.s b/llvm/test/MC/RISCV/rv64Zbr-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64Zbr-invalid.s @@ -0,0 +1,6 @@ +# RUN: not llvm-mc -triple riscv64 -mattr=+b,zbr < %s 2>&1 | FileCheck %s + +# Too many operands +crc32.d s0, s1, s2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction +# Too many operands +crc32c.d s0, s1, s2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv64Zbr-valid.s b/llvm/test/MC/RISCV/rv64Zbr-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64Zbr-valid.s @@ -0,0 +1,20 @@ +# With B extension: +# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \ +# RUN: | llvm-objdump -mattr=+b -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# With Bitmanip CRC extension: +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zbr -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbr < %s \ +# RUN: | llvm-objdump -mattr=+zbr -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: crc32.d t0, t1 +# CHECK-ASM: encoding: [0x93,0x12,0x33,0x61] +crc32.d t0, t1 +# CHECK-ASM-AND-OBJ: crc32c.d t0, t1 +# CHECK-ASM: encoding: [0x93,0x12,0xb3,0x61] +crc32c.d t0, t1 diff --git a/llvm/test/MC/RISCV/rv64Zbs-invalid.s b/llvm/test/MC/RISCV/rv64Zbs-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64Zbs-invalid.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple riscv64 -mattr=+b,zbs < %s 2>&1 | FileCheck %s + +# Too few operands +sbsetw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +sbclrw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +sbinvw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +sbextw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +sbsetiw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +sbclriw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +sbinviw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/rv64Zbs-valid.s b/llvm/test/MC/RISCV/rv64Zbs-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64Zbs-valid.s @@ -0,0 +1,35 @@ +# With B extension: +# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \ +# RUN: | llvm-objdump -mattr=+b -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# With Bitmanip single bit extension: +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zbs -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbs < %s \ +# RUN: | llvm-objdump -mattr=+zbs -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: sbsetw t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x28] +sbsetw t0, t1, t2 +# CHECK-ASM-AND-OBJ: sbclrw t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x48] +sbclrw t0, t1, t2 +# CHECK-ASM-AND-OBJ: sbinvw t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x68] +sbinvw t0, t1, t2 +# CHECK-ASM-AND-OBJ: sbextw t0, t1, t2 +# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x48] +sbextw t0, t1, t2 +# CHECK-ASM-AND-OBJ: sbsetiw t0, t1, 0 +# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x28] +sbsetiw t0, t1, 0 +# CHECK-ASM-AND-OBJ: sbclriw t0, t1, 0 +# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x48] +sbclriw t0, t1, 0 +# CHECK-ASM-AND-OBJ: sbinviw t0, t1, 0 +# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x68] +sbinviw t0, t1, 0 diff --git a/llvm/test/MC/RISCV/rv64Zbt-invalid.s b/llvm/test/MC/RISCV/rv64Zbt-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64Zbt-invalid.s @@ -0,0 +1,6 @@ +# RUN: not llvm-mc -triple riscv64 -mattr=+b,zbt < %s 2>&1 | FileCheck %s + +# Too few operands +fslw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# Too few operands +fsrw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/rv64Zbt-valid.s b/llvm/test/MC/RISCV/rv64Zbt-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64Zbt-valid.s @@ -0,0 +1,20 @@ +# With B extension: +# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \ +# RUN: | llvm-objdump -mattr=+b -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# With Bitmanip ternary extension: +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zbt -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zbt < %s \ +# RUN: | llvm-objdump -mattr=+zbt -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: fslw t0, t1, t2, t3 +# CHECK-ASM: encoding: [0xbb,0x12,0xc3,0x3d] +fslw t0, t1, t2, t3 +# CHECK-ASM-AND-OBJ: fsrw t0, t1, t2, t3 +# CHECK-ASM: encoding: [0xbb,0x52,0xc3,0x3d] +fsrw t0, t1, t2, t3 diff --git a/llvm/test/MC/RISCV/rv64b-aliases-valid.s b/llvm/test/MC/RISCV/rv64b-aliases-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64b-aliases-valid.s @@ -0,0 +1,320 @@ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -riscv-no-aliases \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+b \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+b < %s \ +# RUN: | llvm-objdump -d -r -riscv-no-aliases -mattr=+b - \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+b < %s \ +# RUN: | llvm-objdump -d -r -mattr=+b - \ +# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s + +# The following check prefixes are used in this test: +# CHECK-S-OBJ Match both the .s and objdumped object output with +# aliases enabled +# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with +# aliases disabled + +# CHECK-S-OBJ-NOALIAS: andi t0, t1, 255 +# CHECK-S-OBJ: zext.b t0, t1 +zext.b x5, x6 + +# CHECK-S-OBJ-NOALIAS: packw t0, t1, zero +# CHECK-S-OBJ: zext.h t0, t1 +zext.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: pack t0, t1, zero +# CHECK-S-OBJ: zext.w t0, t1 +zext.w x5, x6 + +# CHECK-S-OBJ-NOALIAS: addiw t0, t1, 0 +# CHECK-S-OBJ: sext.w t0, t1 +sext.w x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 63 +# CHECK-S-OBJ: rev t0, t1 +rev x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 31 +# CHECK-S-OBJ: rev.w t0, t1 +rev.w x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 15 +# CHECK-S-OBJ: rev.h t0, t1 +rev.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 7 +# CHECK-S-OBJ: rev.b t0, t1 +rev.b x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 3 +# CHECK-S-OBJ: rev.n t0, t1 +rev.n x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 1 +# CHECK-S-OBJ: rev.p t0, t1 +rev.p x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 62 +# CHECK-S-OBJ: rev2 t0, t1 +rev2 x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 30 +# CHECK-S-OBJ: rev2.w t0, t1 +rev2.w x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 14 +# CHECK-S-OBJ: rev2.h t0, t1 +rev2.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 6 +# CHECK-S-OBJ: rev2.b t0, t1 +rev2.b x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 2 +# CHECK-S-OBJ: rev2.n t0, t1 +rev2.n x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 60 +# CHECK-S-OBJ: rev4 t0, t1 +rev4 x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 28 +# CHECK-S-OBJ: rev4.w t0, t1 +rev4.w x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 12 +# CHECK-S-OBJ: rev4.h t0, t1 +rev4.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 4 +# CHECK-S-OBJ: rev4.b t0, t1 +rev4.b x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 56 +# CHECK-S-OBJ: rev8 t0, t1 +rev8 x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 24 +# CHECK-S-OBJ: rev8.w t0, t1 +rev8.w x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8 +# CHECK-S-OBJ: rev8.h t0, t1 +rev8.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 48 +# CHECK-S-OBJ: rev16 t0, t1 +rev16 x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 16 +# CHECK-S-OBJ: rev16.w t0, t1 +rev16.w x5, x6 + +# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 32 +# CHECK-S-OBJ: rev32 t0, t1 +rev32 x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 63 +# CHECK-S-OBJ: orc t0, t1 +orc x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 31 +# CHECK-S-OBJ: orc.w t0, t1 +orc.w x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 15 +# CHECK-S-OBJ: orc.h t0, t1 +orc.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 7 +# CHECK-S-OBJ: orc.b t0, t1 +orc.b x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 3 +# CHECK-S-OBJ: orc.n t0, t1 +orc.n x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 1 +# CHECK-S-OBJ: orc.p t0, t1 +orc.p x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 62 +# CHECK-S-OBJ: orc2 t0, t1 +orc2 x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 30 +# CHECK-S-OBJ: orc2.w t0, t1 +orc2.w x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 14 +# CHECK-S-OBJ: orc2.h t0, t1 +orc2.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 6 +# CHECK-S-OBJ: orc2.b t0, t1 +orc2.b x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 2 +# CHECK-S-OBJ: orc2.n t0, t1 +orc2.n x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 60 +# CHECK-S-OBJ: orc4 t0, t1 +orc4 x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 28 +# CHECK-S-OBJ: orc4.w t0, t1 +orc4.w x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 12 +# CHECK-S-OBJ: orc4.h t0, t1 +orc4.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 4 +# CHECK-S-OBJ: orc4.b t0, t1 +orc4.b x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 56 +# CHECK-S-OBJ: orc8 t0, t1 +orc8 x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 24 +# CHECK-S-OBJ: orc8.w t0, t1 +orc8.w x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 8 +# CHECK-S-OBJ: orc8.h t0, t1 +orc8.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 48 +# CHECK-S-OBJ: orc16 t0, t1 +orc16 x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 16 +# CHECK-S-OBJ: orc16.w t0, t1 +orc16.w x5, x6 + +# CHECK-S-OBJ-NOALIAS: gorci t0, t1, 32 +# CHECK-S-OBJ: orc32 t0, t1 +orc32 x5, x6 + +# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 31 +# CHECK-S-OBJ: zip t0, t1 +zip x5, x6 + +# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 15 +# CHECK-S-OBJ: zip.w t0, t1 +zip.w x5, x6 + +# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 7 +# CHECK-S-OBJ: zip.h t0, t1 +zip.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 3 +# CHECK-S-OBJ: zip.b t0, t1 +zip.b x5, x6 + +# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 1 +# CHECK-S-OBJ: zip.n t0, t1 +zip.n x5, x6 + +# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 30 +# CHECK-S-OBJ: zip2 t0, t1 +zip2 x5, x6 + +# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 14 +# CHECK-S-OBJ: zip2.w t0, t1 +zip2.w x5, x6 + +# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 6 +# CHECK-S-OBJ: zip2.h t0, t1 +zip2.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 2 +# CHECK-S-OBJ: zip2.b t0, t1 +zip2.b x5, x6 + +# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 28 +# CHECK-S-OBJ: zip4 t0, t1 +zip4 x5, x6 + +# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 12 +# CHECK-S-OBJ: zip4.w t0, t1 +zip4.w x5, x6 + +# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 4 +# CHECK-S-OBJ: zip4.h t0, t1 +zip4.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 24 +# CHECK-S-OBJ: zip8 t0, t1 +zip8 x5, x6 + +# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 8 +# CHECK-S-OBJ: zip8.w t0, t1 +zip8.w x5, x6 + +# CHECK-S-OBJ-NOALIAS: shfli t0, t1, 16 +# CHECK-S-OBJ: zip16 t0, t1 +zip16 x5, x6 + +# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 31 +# CHECK-S-OBJ: unzip t0, t1 +unzip x5, x6 + +# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 15 +# CHECK-S-OBJ: unzip.w t0, t1 +unzip.w x5, x6 + +# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 7 +# CHECK-S-OBJ: unzip.h t0, t1 +unzip.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 3 +# CHECK-S-OBJ: unzip.b t0, t1 +unzip.b x5, x6 + +# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 1 +# CHECK-S-OBJ: unzip.n t0, t1 +unzip.n x5, x6 + +# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 30 +# CHECK-S-OBJ: unzip2 t0, t1 +unzip2 x5, x6 + +# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 14 +# CHECK-S-OBJ: unzip2.w t0, t1 +unzip2.w x5, x6 + +# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 6 +# CHECK-S-OBJ: unzip2.h t0, t1 +unzip2.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 2 +# CHECK-S-OBJ: unzip2.b t0, t1 +unzip2.b x5, x6 + +# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 28 +# CHECK-S-OBJ: unzip4 t0, t1 +unzip4 x5, x6 + +# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 12 +# CHECK-S-OBJ: unzip4.w t0, t1 +unzip4.w x5, x6 + +# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 4 +# CHECK-S-OBJ: unzip4.h t0, t1 +unzip4.h x5, x6 + +# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 24 +# CHECK-S-OBJ: unzip8 t0, t1 +unzip8 x5, x6 + +# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 8 +# CHECK-S-OBJ: unzip8.w t0, t1 +unzip8.w x5, x6 + +# CHECK-S-OBJ-NOALIAS: unshfli t0, t1, 16 +# CHECK-S-OBJ: unzip16 t0, t1 +unzip16 x5, x6 diff --git a/llvm/test/MC/RISCV/rv64bc-invalid.s b/llvm/test/MC/RISCV/rv64bc-invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64bc-invalid.s @@ -0,0 +1,6 @@ +# RUN: not llvm-mc -triple riscv64 -mattr=+b,c < %s 2>&1 | FileCheck %s + +# Too many operands +c.not t0, t1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction +# Too many operands +c.zest.w t0, t1 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv64bc-valid.s b/llvm/test/MC/RISCV/rv64bc-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64bc-valid.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+b,c -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b,c < %s \ +# RUN: | llvm-objdump -mattr=+b,c -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: c.not t0 +# CHECK-ASM: encoding: [0xc0,0x62] +c.not t0 + +# CHECK-ASM-AND-OBJ: c.zest.w t0 +# CHECK-ASM: encoding: [0xc0,0x6a] +c.zest.w t0