diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -43,6 +43,70 @@
 def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
                            AssemblerPredicate<"FeatureStdExtC">;
 
+def FeatureExtZbb
+    : SubtargetFeature<"bb", "HasStdExtZbb", "true",
+                       "'Zbb' (Base bit Manipulation Instructions)">;
+def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
+                             AssemblerPredicate<"FeatureExtZbb">;
+
+def FeatureExtZbc
+    : SubtargetFeature<"bc", "HasStdExtZbc", "true",
+                       "'Zbc' (Carry-less bit Manipulation Instructions)">;
+def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
+                             AssemblerPredicate<"FeatureExtZbc">;
+
+def FeatureExtZbe
+    : SubtargetFeature<"be", "HasStdExtZbe", "true",
+                       "'Zbe' (Extract-deposit bit Manipulation Instructions)">;
+def HasStdExtZbe : Predicate<"Subtarget->hasStdExtZbe()">,
+                             AssemblerPredicate<"FeatureExtZbe">;
+
+def FeatureExtZbm
+    : SubtargetFeature<"bm", "HasStdExtZbm", "true",
+                       "'Zbm' (Matrix bit Manipulation Instructions)">;
+def HasStdExtZbm : Predicate<"Subtarget->hasStdExtZbm()">,
+                             AssemblerPredicate<"FeatureExtZbm">;
+
+def FeatureExtZbp
+    : SubtargetFeature<"bp", "HasStdExtZbp", "true",
+                       "'Zbp' (Permutation bit Manipulation Instructions)">;
+def HasStdExtZbp : Predicate<"Subtarget->hasStdExtZbp()">,
+                             AssemblerPredicate<"FeatureExtZbp">;
+
+def FeatureExtZbr
+    : SubtargetFeature<"br", "HasStdExtZbr", "true",
+                       "'Zbr' (Polynomial Reduction bit Manipulation Instructions)">;
+def HasStdExtZbr : Predicate<"Subtarget->hasStdExtZbr()">,
+                             AssemblerPredicate<"FeatureExtZbr">;
+
+def FeatureExtZbs
+    : SubtargetFeature<"bs", "HasStdExtZbs", "true",
+                       "'Zbs' (Single-bit bit Manipulation Instructions)">;
+def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
+                             AssemblerPredicate<"FeatureExtZbs">;
+
+def FeatureExtZbt
+    : SubtargetFeature<"bt", "HasStdExtZbt", "true",
+                       "'Zbt' (Ternary bit Manipulation Instructions)">;
+def HasStdExtZbt : Predicate<"Subtarget->hasStdExtZbt()">,
+                             AssemblerPredicate<"FeatureExtZbt">;
+
+def HasStdExtZbbOrZbp
+    : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp()">;
+
+def FeatureStdExtB
+    : SubtargetFeature<"b", "HasStdExtB", "true",
+                       "'B' (Bit Manipulation Instructions)",
+                                [FeatureExtZbb,
+                                 FeatureExtZbc,
+                                 FeatureExtZbe,
+                                 FeatureExtZbm,
+                                 FeatureExtZbp,
+                                 FeatureExtZbr,
+                                 FeatureExtZbs,
+                                 FeatureExtZbt]>;
+def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">,
+                           AssemblerPredicate<"FeatureStdExtB">;
 
 def Feature64Bit
     : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1084,3 +1084,4 @@
 include "RISCVInstrInfoF.td"
 include "RISCVInstrInfoD.td"
 include "RISCVInstrInfoC.td"
+include "RISCVInstrInfoB.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
new file mode 100644
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -0,0 +1,357 @@
+//===-- RISCVInstrFormatsB.td - RISCV B Instruction Formats --*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+//  This file describes the RISC-V B extension instruction formats.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+class RVBInstShift<bits<5> funct5, bits<3> funct3, RISCVOpcode opcode,
+                   string opcodestr>
+    : RVInstI<funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
+              opcodestr, "$rd, $rs1, $imm12"> {
+  // NOTE: the shamt bit-field should be 7-bits long, but since that would cause
+  // decoding conflicts all the shift operations are encoded with op(26) = 0
+  // apart from funnel shifts FSL, FSR and FSRI that have op(26) = 1
+  let imm12{11-7} = funct5;
+  let imm12{6} = 0;
+}
+
+class RVBInstFunct5<bits<5> funct5, bits<3> funct3, RISCVOpcode opcode,
+                    string opcodestr>
+    : RVInstI<funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
+              opcodestr, "$rd, $rs1, $imm12"> {
+  let imm12{11-7} = funct5;
+}
+
+class RVBInstFunct6<bits<6> funct6, bits<3> funct3, RISCVOpcode opcode,
+                    string opcodestr>
+    : RVInstI<funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
+              opcodestr, "$rd, $rs1, $imm12"> {
+  let imm12{11-6} = funct6;
+}
+
+class RVBInstFunct7<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode,
+                    string opcodestr>
+    : RVInstI<funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
+              opcodestr, "$rd, $rs1, $imm12"> {
+  let imm12{11-5} = funct7;
+}
+
+class RVBInstFunct12<bits<12> funct12, bits<3> funct3, RISCVOpcode opcode,
+                     string opcodestr>
+    : RVInst<(outs GPR:$rd), (ins GPR:$rs1),
+             opcodestr, "$rd, $rs1", [], InstFormatI> {
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-20} = funct12;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = opcode.Value;
+}
+
+class RVBInstR<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_32, (outs GPR:$rd),
+              (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2"> {}
+
+class RVBInstR4Reg<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode,
+                   string opcodestr, string argstr>
+    : RVInst<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, GPR:$rs3), opcodestr,
+             argstr, [], InstFormatR4> {
+  bits<5> rs3;
+  bits<5> rs2;
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-27} = rs3;
+  let Inst{26-25} = funct2;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = opcode.Value;
+}
+
+class RVBInstR4Imm<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode,
+                   string opcodestr>
+    : RVInst<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs3, uimm5:$imm),
+             "fsriw", "$rd, $rs1, $rs3, $imm", [], InstFormatR4> {
+  bits<5> rs3;
+  bits<5> imm;
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-27} = rs3;
+  let Inst{26-25} = funct2;
+  let Inst{24-20} = imm;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = opcode.Value;
+}
+
+// Currently implemented only for one instruction FSRI
+class RVBInstR4Imm6<bit funct1, bits<3> funct3, RISCVOpcode opcode,
+                    string opcodestr>
+    : RVInst<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs3, uimm5:$imm),
+             "fsriw", "$rd, $rs1, $rs3, $imm", [], InstFormatR4> {
+  bits<5> rs3;
+  bits<6> imm;
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-27} = rs3;
+  let Inst{26} = funct1;
+  let Inst{25-20} = imm;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = opcode.Value;
+}
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+// Base instructions
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+let Predicates = [HasStdExtZbb] in {
+  def CLZ  : RVBInstFunct12<0b011000000000, 0b001, OPC_OP_IMM, "clz">;
+  def CTZ  : RVBInstFunct12<0b011000000001, 0b001, OPC_OP_IMM, "ctz">;
+  def PCNT : RVBInstFunct12<0b011000000010, 0b001, OPC_OP_IMM, "pcnt">;
+
+  def SLO  : ALU_rr<0b0010000, 0b001, "slo">;
+  def SRO  : ALU_rr<0b0010000, 0b101, "sro">;
+  def SLOI : RVBInstShift<0b00100, 0b001, OPC_OP_IMM, "sloi">;
+  def SROI : RVBInstShift<0b00100, 0b101, OPC_OP_IMM, "sroi">;
+
+  def MIN  : ALU_rr<0b0000101, 0b100, "min">;
+  def MAX  : ALU_rr<0b0000101, 0b101, "max">;
+  def MINU : ALU_rr<0b0000101, 0b110, "minu">;
+  def MAXU : ALU_rr<0b0000101, 0b111, "maxu">;
+}
+
+let Predicates = [HasStdExtZbb, IsRV64] in {
+  def CLZW   : RVBInstFunct12<0b011000000000, 0b001, OPC_OP_IMM_32, "clzw">;
+  def CTZW   : RVBInstFunct12<0b011000000001, 0b001, OPC_OP_IMM_32, "ctzw">;
+  def PCNTW  : RVBInstFunct12<0b011000000010, 0b001, OPC_OP_IMM_32, "pcntw">;
+  def SLOW   : RVBInstR<0b0010000, 0b001, "slow">;
+  def SROW   : RVBInstR<0b0010000, 0b101, "srow">;
+  def SLOIW  : RVBInstFunct7<0b0010000, 0b001, OPC_OP_IMM_32, "sloiw">;
+  def SROIW  : RVBInstFunct7<0b0010000, 0b101, OPC_OP_IMM_32, "sroiw">;
+  def ADDIWU : RVInstI<0b100, OPC_OP_IMM_32, (outs GPR:$rd),
+                       (ins GPR:$rs1, simm12:$imm12),
+                       "addiwu", "$rd, $rs1, $imm12">;
+
+  def SLLIUW : RVBInstShift<0b00001, 0b001, OPC_OP_IMM_32, "slliu.w">;
+
+  def ADDWU : RVBInstR<0b0000101, 0b000, "addwu">;
+  def SUBWU : RVBInstR<0b0100101, 0b000, "subwu">;
+  def ADDUW : RVBInstR<0b0000100, 0b000, "addu.w">;
+  def SUBUW : RVBInstR<0b0100100, 0b000, "subu.w">;
+}
+
+// Carry-less instructions
+
+let Predicates = [HasStdExtZbc] in {
+  def CLMUL  : ALU_rr<0b0000101, 0b001, "clmul">;
+  def CLMULR : ALU_rr<0b0000101, 0b010, "clmulr">;
+  def CLMULH : ALU_rr<0b0000101, 0b011, "clmulh">;
+}
+
+let Predicates = [HasStdExtZbc, IsRV64] in {
+  def CLMULW  : RVBInstR<0b0000101, 0b001, "clmulw">;
+  def CLMULRW : RVBInstR<0b0000101, 0b010, "clmulrw">;
+  def CLMULHW : RVBInstR<0b0000101, 0b011, "clmulhw">;
+}
+
+// Extract-bit/Deposit-bit instructions
+
+let Predicates = [HasStdExtZbe] in {
+  def BDEP : ALU_rr<0b0000100, 0b011, "bdep">;
+  def BEXT : ALU_rr<0b0000100, 0b100, "bext">;
+}
+
+let Predicates = [HasStdExtZbe, IsRV64] in {
+  def BDEPW : RVBInstR<0b0000100, 0b010, "bdepw">;
+  def BEXTW : RVBInstR<0b0000100, 0b110, "bextw">;
+}
+
+// Matrix Instructions
+
+let Predicates = [HasStdExtZbm, IsRV64] in {
+  def BMATOR   : ALU_rr<0b0000100, 0b110, "bmator">;
+  def BMATXOR  : ALU_rr<0b0000100, 0b111, "bmatxor">;
+  def BMATFLIP : RVBInstFunct12<0b011000000011, 0b001, OPC_OP_IMM, "bmatflip">;
+}
+
+// Bit Permutations Instructions
+
+let Predicates = [HasStdExtZbbOrZbp] in {
+  def ANDN : ALU_rr<0b0100000, 0b111, "andn">;
+  def ORN  : ALU_rr<0b0100000, 0b110, "orn">;
+  def XNOR : ALU_rr<0b0100000, 0b100, "xnor">;
+  def PACK : ALU_rr<0b0000100, 0b101, "pack">;
+  def ROL  : ALU_rr<0b0110000, 0b001, "rol">;
+  def ROR  : ALU_rr<0b0110000, 0b101, "ror">;
+  def RORI : RVBInstFunct5<0b01100, 0b101, OPC_OP_IMM, "rori">;
+}
+
+let Predicates = [HasStdExtZbp] in {
+  def GREV   : ALU_rr<0b0100000, 0b001, "grev">;
+  def SHFL   : ALU_rr<0b0000100, 0b001, "shfl">;
+  def UNSHFL : ALU_rr<0b0000100, 0b010, "unshfl">;
+
+  def GREVI   : RVBInstFunct5<0b01000, 0b001, OPC_OP_IMM, "grevi">;
+  def SHFLI   : RVBInstFunct6<0b000010, 0b001, OPC_OP_IMM, "shfli">;
+  def UNSHFLI : RVBInstFunct6<0b000010, 0b101, OPC_OP_IMM, "unshfli">;
+}
+
+let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
+  def ROLW  : RVBInstR<0b0110000, 0b001, "rolw">;
+  def RORW  : RVBInstR<0b0110000, 0b101, "rorw">;
+  def RORIW : RVBInstFunct7<0b0110000, 0b101, OPC_OP_IMM_32, "roriw">;
+
+  def PACKW : RVBInstR<0b0000100, 0b100, "packw">;
+}
+
+let Predicates = [HasStdExtZbp, IsRV64] in {
+  def GREVW  : RVBInstR<0b0100000, 0b001, "grevw">;
+  def GREVIW : RVBInstFunct7<0b0100000, 0b001, OPC_OP_IMM_32, "greviw">;
+
+  def SHFLW   : RVBInstR<0b0000100, 0b001, "shflw">;
+  def UNSHFLW : RVBInstR<0b0000100, 0b101, "unshflw">;
+}
+
+// Polynomial Reduction Instructions
+
+let Predicates = [HasStdExtZbr] in {
+  def CRC32B : RVBInstFunct12<0b011000010000, 0b001, OPC_OP_IMM, "crc32.b">;
+  def CRC32H : RVBInstFunct12<0b011000010001, 0b001, OPC_OP_IMM, "crc32.h">;
+  def CRC32W : RVBInstFunct12<0b011000010010, 0b001, OPC_OP_IMM, "crc32.w">;
+
+  def CRC32CB : RVBInstFunct12<0b011000011000, 0b001, OPC_OP_IMM, "crc32c.b">;
+  def CRC32CH : RVBInstFunct12<0b011000011001, 0b001, OPC_OP_IMM, "crc32c.h">;
+  def CRC32CW : RVBInstFunct12<0b011000011010, 0b001, OPC_OP_IMM, "crc32c.w">;
+}
+
+let Predicates = [HasStdExtZbr, IsRV64] in {
+  def CRC32D  : RVBInstFunct12<0b011000010011, 0b001, OPC_OP_IMM, "crc32.d">;
+  def CRC32CD : RVBInstFunct12<0b011000011011, 0b001, OPC_OP_IMM, "crc32c.d">;
+}
+
+// Single Bit Instructions
+
+let Predicates = [HasStdExtZbs] in {
+  def SBSET : ALU_rr<0b0010100, 0b001, "sbset">;
+  def SBCLR : ALU_rr<0b0100100, 0b001, "sbclr">;
+  def SBINV : ALU_rr<0b0110100, 0b001, "sbinv">;
+  def SBEXT : ALU_rr<0b0100100, 0b101, "sbext">;
+
+  def SBSETI : RVBInstFunct5<0b00101, 0b001, OPC_OP_IMM, "sbseti">;
+  def SBCLRI : RVBInstFunct5<0b01001, 0b001, OPC_OP_IMM, "sbclri">;
+  def SBINVI : RVBInstFunct5<0b01101, 0b001, OPC_OP_IMM, "sbinvi">;
+  def SBEXTI : RVBInstFunct5<0b01001, 0b101, OPC_OP_IMM, "sbexti">;
+}
+
+let Predicates = [HasStdExtZbs, IsRV64] in {
+  def SBSETW : RVBInstR<0b0010100, 0b001, "sbsetw">;
+  def SBCLRW : RVBInstR<0b0100100, 0b001, "sbclrw">;
+  def SBINVW : RVBInstR<0b0110100, 0b001, "sbinvw">;
+  def SBEXTW : RVBInstR<0b0100100, 0b101, "sbextw">;
+
+  def SBSETIW : RVBInstFunct7<0b0010100, 0b001, OPC_OP_IMM_32, "sbsetiw">;
+  def SBCLRIW : RVBInstFunct7<0b0100100, 0b001, OPC_OP_IMM_32, "sbclriw">;
+  def SBINVIW : RVBInstFunct7<0b0110100, 0b001, OPC_OP_IMM_32, "sbinviw">;
+}
+
+// Ternary Instructions
+
+let Predicates = [HasStdExtZbt] in {
+  def CMIX : RVBInstR4Reg<0b11, 0b001, OPC_OP, "cmix", "$rd, $rs2, $rs1, $rs3">;
+  def CMOV : RVBInstR4Reg<0b11, 0b101, OPC_OP, "cmov", "$rd, $rs2, $rs1, $rs3">;
+  def FSL  : RVBInstR4Reg<0b10, 0b001, OPC_OP, "fsl", "$rd, $rs1, $rs3, $rs2">;
+  def FSR  : RVBInstR4Reg<0b10, 0b101, OPC_OP, "fsr", "$rd, $rs1, $rs3, $rs2">;
+  def FSRI : RVBInstR4Imm6<0b1, 0b101, OPC_OP_IMM, "fsri">;
+}
+
+let Predicates = [HasStdExtZbt, IsRV64] in {
+  def FSLW  : RVBInstR4Reg<0b10, 0b001, OPC_OP_32, "fslw", "$rd, $rs1, $rs3, $rs2">;
+  def FSRW  : RVBInstR4Reg<0b10, 0b101, OPC_OP_32, "fsrw", "$rd, $rs1, $rs3, $rs2">;
+  def FSRIW : RVBInstR4Imm<0b10, 0b101, OPC_OP_IMM_32, "fsriw">;
+}
+
+//===----------------------------------------------------------------------===//
+// Future compressed instructions
+//===----------------------------------------------------------------------===//
+
+class RVBInstC<bits<2> funct2, string opcodestr>
+    : RVInst16<(outs GPR:$rs_wb), (ins GPR:$rs), opcodestr, "$rs", [],
+               InstFormatCR> {
+  bits<3> rs;
+  let Constraints = "$rs = $rs_wb";
+
+  let Inst{12-15} = 0b0110;
+  let Inst{10-11} = funct2;
+  let Inst{7-9} = rs;
+  let Inst{0-6} = 0b0000001;
+}
+
+let Predicates = [HasStdExtB, HasStdExtC] in {
+  def CNOT : RVBInstC<00, "c.not">;
+}
+
+let Predicates = [HasStdExtB, HasStdExtC, IsRV64] in {
+  def CZESTW : RVBInstC<01, "c.zest.w">;
+}
+}  // hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+//===----------------------------------------------------------------------===//
+// Pseudo Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZbbOrZbp, IsRV32] in {
+  def : InstAlias<"rev $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11111)>;
+  def : InstAlias<"rev2 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11110)>;
+  def : InstAlias<"rev4 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11100)>;
+  def : InstAlias<"rev8 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11000)>;
+  def : InstAlias<"rev16 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b10000)>;
+}
+
+let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
+  def : InstAlias<"rev.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011111)>;
+  def : InstAlias<"rev2.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011110)>;
+  def : InstAlias<"rev4.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011100)>;
+  def : InstAlias<"rev8.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011000)>;
+  def : InstAlias<"rev16.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b010000)>;
+}
+
+let Predicates = [HasStdExtZbp] in {
+  def : InstAlias<"rev.p $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00001)>;
+}
+
+let Predicates = [HasStdExtZbbOrZbp] in {
+  def : InstAlias<"rev.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01111)>;
+  def : InstAlias<"rev.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00111)>;
+  def : InstAlias<"rev.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00011)>;
+
+  def : InstAlias<"rev2.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01110)>;
+  def : InstAlias<"rev2.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00110)>;
+  def : InstAlias<"rev2.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00010)>;
+
+  def : InstAlias<"rev4.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01100)>;
+  def : InstAlias<"rev4.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00100)>;
+
+  def : InstAlias<"rev8.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01000)>;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -35,6 +35,15 @@
   bool HasStdExtF = false;
   bool HasStdExtD = false;
   bool HasStdExtC = false;
+  bool HasStdExtB = false;
+  bool HasStdExtZbb = false;
+  bool HasStdExtZbc = false;
+  bool HasStdExtZbe = false;
+  bool HasStdExtZbm = false;
+  bool HasStdExtZbp = false;
+  bool HasStdExtZbr = false;
+  bool HasStdExtZbs = false;
+  bool HasStdExtZbt = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
   bool EnableLinkerRelax = false;
@@ -80,6 +89,15 @@
   bool hasStdExtF() const { return HasStdExtF; }
   bool hasStdExtD() const { return HasStdExtD; }
   bool hasStdExtC() const { return HasStdExtC; }
+  bool hasStdExtB() const { return HasStdExtB; }
+  bool hasStdExtZbb() const { return HasStdExtZbb; }
+  bool hasStdExtZbc() const { return HasStdExtZbc; }
+  bool hasStdExtZbe() const { return HasStdExtZbe; }
+  bool hasStdExtZbm() const { return HasStdExtZbm; }
+  bool hasStdExtZbp() const { return HasStdExtZbp; }
+  bool hasStdExtZbr() const { return HasStdExtZbr; }
+  bool hasStdExtZbs() const { return HasStdExtZbs; }
+  bool hasStdExtZbt() const { return HasStdExtZbt; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
diff --git a/llvm/test/MC/RISCV/rv32Zbb-invalid.s b/llvm/test/MC/RISCV/rv32Zbb-invalid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32Zbb-invalid.s
@@ -0,0 +1,24 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+b,bb < %s 2>&1 | FileCheck %s
+
+# Too few operands
+slo s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sro s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sloi s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sroi s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too many operands
+clz s0, s1, s2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+# Too many operands
+ctz s0, s1, s2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+# Too many operands
+pcnt s0, s1, s2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+# Too few operands
+min	s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+max	s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+minu	s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+maxu	s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv32Zbb-valid.s b/llvm/test/MC/RISCV/rv32Zbb-valid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32Zbb-valid.s
@@ -0,0 +1,51 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+bb -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+bb < %s \
+# RUN:     | llvm-objdump -mattr=+bb -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: slo t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x20]
+slo t0, t1, t2
+# CHECK-ASM-AND-OBJ: sro t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x20]
+sro t0, t1, t2
+# CHECK-ASM-AND-OBJ: sloi t0, t1, 31
+# CHECK-ASM: encoding: [0x93,0x12,0xf3,0x21]
+sloi t0, t1, 31
+# CHECK-ASM-AND-OBJ: sroi t0, t1, 31
+# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x21]
+sroi t0, t1, 31
+# CHECK-ASM-AND-OBJ: sloi t0, t1, 0
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x20]
+sloi t0, t1, 0
+# CHECK-ASM-AND-OBJ: sroi t0, t1, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x20]
+sroi t0, t1, 0
+# CHECK-ASM-AND-OBJ: clz t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x60]
+clz t0, t1
+# CHECK-ASM-AND-OBJ: ctz t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x13,0x60]
+ctz t0, t1
+# CHECK-ASM-AND-OBJ: pcnt t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x23,0x60]
+pcnt t0, t1
+# CHECK-ASM-AND-OBJ: min t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
+min t0, t1, t2
+# CHECK-ASM-AND-OBJ: max t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x0a]
+max t0, t1, t2
+# CHECK-ASM-AND-OBJ: minu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
+minu t0, t1, t2
+# CHECK-ASM-AND-OBJ: maxu t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x0a]
+maxu t0, t1, t2
diff --git a/llvm/test/MC/RISCV/rv32Zbbp-invalid.s b/llvm/test/MC/RISCV/rv32Zbbp-invalid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32Zbbp-invalid.s
@@ -0,0 +1,16 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+b,bb,bp < %s 2>&1 | FileCheck %s
+
+# Too few operands
+andn s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+orn s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+xnor s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+rol s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+ror s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+rori s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+pack	s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv32Zbbp-valid.s b/llvm/test/MC/RISCV/rv32Zbbp-valid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32Zbbp-valid.s
@@ -0,0 +1,45 @@
+# With B extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip base extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+bb -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+bb < %s \
+# RUN:     | llvm-objdump -mattr=+bb -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip permutation extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+bp -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+bp < %s \
+# RUN:     | llvm-objdump -mattr=+bp -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: andn t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x40]
+andn t0, t1, t2
+# CHECK-ASM-AND-OBJ: orn t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x40]
+orn t0, t1, t2
+# CHECK-ASM-AND-OBJ: xnor t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x40]
+xnor t0, t1, t2
+# CHECK-ASM-AND-OBJ: rol t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x60]
+rol t0, t1, t2
+# CHECK-ASM-AND-OBJ: ror t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x60]
+ror t0, t1, t2
+# CHECK-ASM-AND-OBJ: rori t0, t1, 31
+# CHECK-ASM: encoding: [0x93,0x52,0xf3,0x61]
+rori t0, t1, 31
+# CHECK-ASM-AND-OBJ: rori t0, t1, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x60]
+rori t0, t1, 0
+# CHECK-ASM-AND-OBJ: pack t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x08]
+pack t0, t1, t2
diff --git a/llvm/test/MC/RISCV/rv32Zbc-invalid.s b/llvm/test/MC/RISCV/rv32Zbc-invalid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32Zbc-invalid.s
@@ -0,0 +1,8 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+b,bc < %s 2>&1 | FileCheck %s
+
+# Too few operands
+clmul	s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+clmulr	s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+clmulh	s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv32Zbc-valid.s b/llvm/test/MC/RISCV/rv32Zbc-valid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32Zbc-valid.s
@@ -0,0 +1,23 @@
+# With B extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip carry-less multiply extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+bc -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+bc < %s \
+# RUN:     | llvm-objdump -mattr=+bc -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: clmul t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x0a]
+clmul t0, t1, t2
+# CHECK-ASM-AND-OBJ: clmulr t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x22,0x73,0x0a]
+clmulr t0, t1, t2
+# CHECK-ASM-AND-OBJ: clmulh t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x32,0x73,0x0a]
+clmulh t0, t1, t2
diff --git a/llvm/test/MC/RISCV/rv32Zbe-invalid.s b/llvm/test/MC/RISCV/rv32Zbe-invalid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32Zbe-invalid.s
@@ -0,0 +1,6 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+b,be < %s 2>&1 | FileCheck %s
+
+# Too few operands
+bdep	s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+bext	s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv32Zbe-valid.s b/llvm/test/MC/RISCV/rv32Zbe-valid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32Zbe-valid.s
@@ -0,0 +1,20 @@
+# With B extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip extract/deposit extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+be -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+be < %s \
+# RUN:     | llvm-objdump -mattr=+be -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: bdep t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x32,0x73,0x08]
+bdep t0, t1, t2
+# CHECK-ASM-AND-OBJ: bext t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x08]
+bext t0, t1, t2
diff --git a/llvm/test/MC/RISCV/rv32Zbp-invalid.s b/llvm/test/MC/RISCV/rv32Zbp-invalid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32Zbp-invalid.s
@@ -0,0 +1,14 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+b,bp < %s 2>&1 | FileCheck %s
+
+# Too few operands
+grev s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+grevi s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+shfl	s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+unshfl	s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+shfli t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+unshfli	t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv32Zbp-valid.s b/llvm/test/MC/RISCV/rv32Zbp-valid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32Zbp-valid.s
@@ -0,0 +1,25 @@
+# With Bitmanip permutation extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+bp -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+bp < %s \
+# RUN:     | llvm-objdump -mattr=+bp -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: grev t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x40]
+grev t0, t1, t2
+# CHECK-ASM-AND-OBJ: grevi t0, t1, 0
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x40]
+grevi t0, t1, 0
+# CHECK-ASM-AND-OBJ: shfl t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x08]
+shfl t0, t1, t2
+# CHECK-ASM-AND-OBJ: unshfl t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x22,0x73,0x08]
+unshfl t0, t1, t2
+# CHECK-ASM-AND-OBJ: shfli t0, t1, 0
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x08]
+shfli	t0, t1, 0
+# CHECK-ASM-AND-OBJ: unshfli t0, t1, 0
+# CHECK-ASM: encoding: [0x93,0x52,0x03,0x08]
+unshfli t0, t1, 0
diff --git a/llvm/test/MC/RISCV/rv32Zbr-invalid.s b/llvm/test/MC/RISCV/rv32Zbr-invalid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32Zbr-invalid.s
@@ -0,0 +1,14 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+b,br < %s 2>&1 | FileCheck %s
+
+# Too many operands
+crc32.b	s0, s1, s2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+# Too many operands
+crc32.h	s0, s1, s2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+# Too many operands
+crc32.w	s0, s1, s2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+# Too many operands
+crc32c.b s0, s1, s2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
+# Too many operands
+crc32c.h s0, s1, s2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
+# Too many operands
+crc32c.w s0, s1, s2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv32Zbr-valid.s b/llvm/test/MC/RISCV/rv32Zbr-valid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32Zbr-valid.s
@@ -0,0 +1,32 @@
+# With B extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip CRC extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+br -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+br < %s \
+# RUN:     | llvm-objdump -mattr=+br -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: crc32.b	t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x03,0x61]
+crc32.b	t0, t1
+# CHECK-ASM-AND-OBJ: crc32.h	t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x13,0x61]
+crc32.h	t0, t1
+# CHECK-ASM-AND-OBJ: crc32.w	t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x23,0x61]
+crc32.w	t0, t1
+# CHECK-ASM-AND-OBJ: crc32c.b	t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x83,0x61]
+crc32c.b	t0, t1
+# CHECK-ASM-AND-OBJ: crc32c.h	t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x93,0x61]
+crc32c.h	t0, t1
+# CHECK-ASM-AND-OBJ: crc32c.w	t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0xa3,0x61]
+crc32c.w	t0, t1
diff --git a/llvm/test/MC/RISCV/rv32Zbs-invalid.s b/llvm/test/MC/RISCV/rv32Zbs-invalid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32Zbs-invalid.s
@@ -0,0 +1,18 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+b,bs < %s 2>&1 | FileCheck %s
+
+# Too few operands
+sbset s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbclr s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbinv s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbext s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbseti s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbclri s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbinvi s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbexti s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv32Zbs-valid.s b/llvm/test/MC/RISCV/rv32Zbs-valid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32Zbs-valid.s
@@ -0,0 +1,38 @@
+# With B extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip single bit extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+bs -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+bs < %s \
+# RUN:     | llvm-objdump -mattr=+bs -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: sbset t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x28]
+sbset t0, t1, t2
+# CHECK-ASM-AND-OBJ: sbclr t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x48]
+sbclr t0, t1, t2
+# CHECK-ASM-AND-OBJ: sbinv t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x12,0x73,0x68]
+sbinv t0, t1, t2
+# CHECK-ASM-AND-OBJ: sbext t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x48]
+sbext t0, t1, t2
+# CHECK-ASM-AND-OBJ: sbseti t0, t1, 1
+# CHECK-ASM: encoding: [0x93,0x12,0x13,0x28]
+sbseti t0, t1, 1
+# CHECK-ASM-AND-OBJ: sbclri t0, t1, 1
+# CHECK-ASM: encoding: [0x93,0x12,0x13,0x48]
+sbclri t0, t1, 1
+# CHECK-ASM-AND-OBJ: sbinvi t0, t1, 1
+# CHECK-ASM: encoding: [0x93,0x12,0x13,0x68]
+sbinvi t0, t1, 1
+# CHECK-ASM-AND-OBJ: sbexti t0, t1, 1
+# CHECK-ASM: encoding: [0x93,0x52,0x13,0x48]
+sbexti t0, t1, 1
diff --git a/llvm/test/MC/RISCV/rv32Zbt-invalid.s b/llvm/test/MC/RISCV/rv32Zbt-invalid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32Zbt-invalid.s
@@ -0,0 +1,10 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+b,bt < %s 2>&1 | FileCheck %s
+
+# Too few operands
+cmix s0, s1, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+cmov s0, s1, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+fsl s0, s1, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+fsr s0, s1, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv32Zbt-valid.s b/llvm/test/MC/RISCV/rv32Zbt-valid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32Zbt-valid.s
@@ -0,0 +1,26 @@
+# With B extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip ternary extension:
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+bt -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+bt < %s \
+# RUN:     | llvm-objdump -mattr=+bt -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: cmix t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x92,0x63,0xe6]
+cmix t0, t1, t2, t3
+# CHECK-ASM-AND-OBJ: cmov t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0xd2,0x63,0xe6]
+cmov t0, t1, t2, t3
+# CHECK-ASM-AND-OBJ: fsl t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x12,0xc3,0x3d]
+fsl t0, t1, t2, t3
+# CHECK-ASM-AND-OBJ: fsr t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xb3,0x52,0xc3,0x3d]
+fsr t0, t1, t2, t3
diff --git a/llvm/test/MC/RISCV/rv32b-aliases-valid.s b/llvm/test/MC/RISCV/rv32b-aliases-valid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32b-aliases-valid.s
@@ -0,0 +1,76 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+b -riscv-no-aliases \
+# RUN:     | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+b \
+# RUN:     | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+b < %s \
+# RUN:     | llvm-objdump -d -r -riscv-no-aliases -mattr=+b - \
+# RUN:     | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+b < %s \
+# RUN:     | llvm-objdump -d -r -mattr=+b - \
+# RUN:     | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# The following check prefixes are used in this test:
+# CHECK-S-OBJ            Match both the .s and objdumped object output with
+#                        aliases enabled
+# CHECK-S-OBJ-NOALIAS    Match both the .s and objdumped object output with
+#                        aliases disabled
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 31
+# CHECK-S-OBJ: rev t0, t1
+rev x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 15
+# CHECK-S-OBJ: rev.h t0, t1
+rev.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 7
+# CHECK-S-OBJ: rev.b t0, t1
+rev.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 3
+# CHECK-S-OBJ: rev.n t0, t1
+rev.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 1
+# CHECK-S-OBJ: rev.p t0, t1
+rev.p x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 30
+# CHECK-S-OBJ: rev2 t0, t1
+rev2 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 14
+# CHECK-S-OBJ: rev2.h t0, t1
+rev2.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 6
+# CHECK-S-OBJ: rev2.b t0, t1
+rev2.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 2
+# CHECK-S-OBJ: rev2.n t0, t1
+rev2.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 28
+# CHECK-S-OBJ: rev4 t0, t1
+rev4 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 12
+# CHECK-S-OBJ: rev4.h t0, t1
+rev4.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 4
+# CHECK-S-OBJ: rev4.b t0, t1
+rev4.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 24
+# CHECK-S-OBJ: rev8 t0, t1
+rev8 x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 16
+# CHECK-S-OBJ: rev16 t0, t1
+rev16 x5, x6
diff --git a/llvm/test/MC/RISCV/rv32bc-valid.s b/llvm/test/MC/RISCV/rv32bc-valid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32bc-valid.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+b,c -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+b,c < %s \
+# RUN:     | llvm-objdump -mattr=+b,c -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: c.not t0
+# CHECK-ASM: encoding: [0xc0,0x62]
+c.not t0
diff --git a/llvm/test/MC/RISCV/rv64Zbb-invalid.s b/llvm/test/MC/RISCV/rv64Zbb-invalid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64Zbb-invalid.s
@@ -0,0 +1,28 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+b,bb < %s 2>&1 | FileCheck %s
+
+# Too many operands
+clzw s0, s1, s2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+# Too many operands
+ctzw s0, s1, s2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+# Too many operands
+pcntw s0, s1, s2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+# Too few operands
+slow t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+srow t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sloiw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sroiw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+addiwu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+slliu.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+addwu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+subwu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+addu.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+subu.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv64Zbb-valid.s b/llvm/test/MC/RISCV/rv64Zbb-valid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64Zbb-valid.s
@@ -0,0 +1,53 @@
+# With B extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip base extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+bb -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+bb < %s \
+# RUN:     | llvm-objdump -mattr=+bb -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: clzw t0, t1
+# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x60]
+clzw	t0, t1
+# CHECK-ASM-AND-OBJ: ctzw t0, t1
+# CHECK-ASM: encoding: [0x9b,0x12,0x13,0x60]
+ctzw	t0, t1
+# CHECK-ASM-AND-OBJ: pcntw t0, t1
+# CHECK-ASM: encoding: [0x9b,0x12,0x23,0x60]
+pcntw	t0, t1
+# CHECK-ASM-AND-OBJ: slow t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x20]
+slow t0, t1, t2
+# CHECK-ASM-AND-OBJ: srow t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x20]
+srow t0, t1, t2
+# CHECK-ASM-AND-OBJ: sloiw  t0, t1, 0
+# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x20]
+sloiw	t0, t1, 0
+# CHECK-ASM-AND-OBJ: sroiw  t0, t1, 0
+# CHECK-ASM: encoding: [0x9b,0x52,0x03,0x20]
+sroiw	t0, t1, 0
+# CHECK-ASM-AND-OBJ: addiwu t0, t1, 0
+# CHECK-ASM: encoding: [0x9b,0x42,0x03,0x00]
+addiwu t0, t1, 0
+# CHECK-ASM-AND-OBJ: slliu.w t0, t1, 0
+# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x08]
+slliu.w t0, t1, 0
+# CHECK-ASM-AND-OBJ: addwu t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x0a]
+addwu t0, t1, t2
+# CHECK-ASM-AND-OBJ: subwu t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x4a]
+subwu t0, t1, t2
+# CHECK-ASM-AND-OBJ: addu.w t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x08]
+addu.w t0, t1, t2
+# CHECK-ASM-AND-OBJ: subu.w t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x02,0x73,0x48]
+subu.w t0, t1, t2
diff --git a/llvm/test/MC/RISCV/rv64Zbbp-invalid.s b/llvm/test/MC/RISCV/rv64Zbbp-invalid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64Zbbp-invalid.s
@@ -0,0 +1,10 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+b,bb,bp < %s 2>&1 | FileCheck %s
+
+# Too few operands
+rolw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+rorw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+roriw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+packw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv64Zbbp-valid.s b/llvm/test/MC/RISCV/rv64Zbbp-valid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64Zbbp-valid.s
@@ -0,0 +1,36 @@
+# With B extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip base extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+bb -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+bb < %s \
+# RUN:     | llvm-objdump -mattr=+bb -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip permutation extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+bp -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+bp < %s \
+# RUN:     | llvm-objdump -mattr=+bp -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: rolw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x60]
+rolw t0, t1, t2
+# CHECK-ASM-AND-OBJ: rorw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x60]
+rorw t0, t1, t2
+# CHECK-ASM-AND-OBJ: roriw  t0, t1, 31
+# CHECK-ASM: encoding: [0x9b,0x52,0xf3,0x61]
+roriw	t0, t1, 31
+# CHECK-ASM-AND-OBJ: roriw  t0, t1, 0
+# CHECK-ASM: encoding: [0x9b,0x52,0x03,0x60]
+roriw	t0, t1, 0
+# CHECK-ASM-AND-OBJ: packw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x42,0x73,0x08]
+packw	t0, t1, t2
diff --git a/llvm/test/MC/RISCV/rv64Zbc-invalid.s b/llvm/test/MC/RISCV/rv64Zbc-invalid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64Zbc-invalid.s
@@ -0,0 +1,8 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+b,bc < %s 2>&1 | FileCheck %s
+
+# Too few operands
+clmulw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+clmulrw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+clmulhw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv64Zbc-valid.s b/llvm/test/MC/RISCV/rv64Zbc-valid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64Zbc-valid.s
@@ -0,0 +1,23 @@
+# With B extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip carry-less multiply extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+bc -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+bc < %s \
+# RUN:     | llvm-objdump -mattr=+bc -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: clmulw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x0a]
+clmulw	t0, t1, t2
+# CHECK-ASM-AND-OBJ: clmulrw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x22,0x73,0x0a]
+clmulrw	t0, t1, t2
+# CHECK-ASM-AND-OBJ: clmulhw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x32,0x73,0x0a]
+clmulhw	t0, t1, t2
diff --git a/llvm/test/MC/RISCV/rv64Zbe-invalid.s b/llvm/test/MC/RISCV/rv64Zbe-invalid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64Zbe-invalid.s
@@ -0,0 +1,6 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+b,be < %s 2>&1 | FileCheck %s
+
+# Too few operands
+bdepw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+bextw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv64Zbe-valid.s b/llvm/test/MC/RISCV/rv64Zbe-valid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64Zbe-valid.s
@@ -0,0 +1,20 @@
+# With B extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip extract/deposit extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+be -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+be < %s \
+# RUN:     | llvm-objdump -mattr=+be -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: bdepw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x22,0x73,0x08]
+bdepw	t0, t1, t2
+# CHECK-ASM-AND-OBJ: bextw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x62,0x73,0x08]
+bextw	t0, t1, t2
diff --git a/llvm/test/MC/RISCV/rv64Zbm-invalid.s b/llvm/test/MC/RISCV/rv64Zbm-invalid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64Zbm-invalid.s
@@ -0,0 +1,8 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+b,bm < %s 2>&1 | FileCheck %s
+
+# Too few operands
+bmator	s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+bmatxor	s0, s1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too many operands
+bmatflip s0, s1, s2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv64Zbm-valid.s b/llvm/test/MC/RISCV/rv64Zbm-valid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64Zbm-valid.s
@@ -0,0 +1,23 @@
+# With B extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip matix extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+bm -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+bm < %s \
+# RUN:     | llvm-objdump -mattr=+bm -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: bmator t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x08]
+bmator t0, t1, t2
+# CHECK-ASM-AND-OBJ: bmatxor t0, t1, t2
+# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x08]
+bmatxor t0, t1, t2
+# CHECK-ASM-AND-OBJ: bmatflip t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x33,0x60]
+bmatflip t0, t1
diff --git a/llvm/test/MC/RISCV/rv64Zbp-invalid.s b/llvm/test/MC/RISCV/rv64Zbp-invalid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64Zbp-invalid.s
@@ -0,0 +1,10 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+b,bp < %s 2>&1 | FileCheck %s
+
+# Too few operands
+grevw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+greviw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+shflw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+unshflw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv64Zbp-valid.s b/llvm/test/MC/RISCV/rv64Zbp-valid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64Zbp-valid.s
@@ -0,0 +1,22 @@
+# With Bitmanip permutation extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+bp -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+bp < %s \
+# RUN:     | llvm-objdump -mattr=+bp -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: grevw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x40]
+grevw t0, t1, t2
+# CHECK-ASM-AND-OBJ: greviw  t0, t1, 31
+# CHECK-ASM: encoding: [0x9b,0x12,0xf3,0x41]
+greviw	t0, t1, 31
+# CHECK-ASM-AND-OBJ: greviw  t0, t1, 0
+# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x40]
+greviw	t0, t1, 0
+# CHECK-ASM-AND-OBJ: shflw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x08]
+shflw	t0, t1, t2
+# CHECK-ASM-AND-OBJ: unshflw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x08]
+unshflw	t0, t1, t2
diff --git a/llvm/test/MC/RISCV/rv64Zbr-invalid.s b/llvm/test/MC/RISCV/rv64Zbr-invalid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64Zbr-invalid.s
@@ -0,0 +1,6 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+b,br < %s 2>&1 | FileCheck %s
+
+# Too many operands
+crc32.d s0, s1, s2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+# Too many operands
+crc32c.d s0, s1, s2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv64Zbr-valid.s b/llvm/test/MC/RISCV/rv64Zbr-valid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64Zbr-valid.s
@@ -0,0 +1,20 @@
+# With B extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip CRC extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+br -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+br < %s \
+# RUN:     | llvm-objdump -mattr=+br -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: crc32.d t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0x33,0x61]
+crc32.d t0, t1
+# CHECK-ASM-AND-OBJ: crc32c.d t0, t1
+# CHECK-ASM: encoding: [0x93,0x12,0xb3,0x61]
+crc32c.d t0, t1
diff --git a/llvm/test/MC/RISCV/rv64Zbs-invalid.s b/llvm/test/MC/RISCV/rv64Zbs-invalid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64Zbs-invalid.s
@@ -0,0 +1,16 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+b,bs < %s 2>&1 | FileCheck %s
+
+# Too few operands
+sbsetw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbclrw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbinvw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbextw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbsetiw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbclriw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+sbinviw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv64Zbs-valid.s b/llvm/test/MC/RISCV/rv64Zbs-valid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64Zbs-valid.s
@@ -0,0 +1,44 @@
+# With B extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip single bit extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+bs -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+bs < %s \
+# RUN:     | llvm-objdump -mattr=+bs -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: sbsetw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x28]
+sbsetw t0, t1, t2
+# CHECK-ASM-AND-OBJ: sbclrw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x48]
+sbclrw t0, t1, t2
+# CHECK-ASM-AND-OBJ: sbinvw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x12,0x73,0x68]
+sbinvw t0, t1, t2
+# CHECK-ASM-AND-OBJ: sbextw t0, t1, t2
+# CHECK-ASM: encoding: [0xbb,0x52,0x73,0x48]
+sbextw t0, t1, t2
+# CHECK-ASM-AND-OBJ: sbsetiw  t0, t1, 31
+# CHECK-ASM: encoding: [0x9b,0x12,0xf3,0x29]
+sbsetiw	t0, t1, 31
+# CHECK-ASM-AND-OBJ: sbsetiw  t0, t1, 0
+# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x28]
+sbsetiw	t0, t1, 0
+# CHECK-ASM-AND-OBJ: sbclriw  t0, t1, 31
+# CHECK-ASM: encoding: [0x9b,0x12,0xf3,0x49]
+sbclriw	t0, t1, 31
+# CHECK-ASM-AND-OBJ: sbclriw  t0, t1, 0
+# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x48]
+sbclriw	t0, t1, 0
+# CHECK-ASM-AND-OBJ: sbinviw  t0, t1, 31
+# CHECK-ASM: encoding: [0x9b,0x12,0xf3,0x69]
+sbinviw	t0, t1, 31
+# CHECK-ASM-AND-OBJ: sbinviw  t0, t1, 0
+# CHECK-ASM: encoding: [0x9b,0x12,0x03,0x68]
+sbinviw	t0, t1, 0
diff --git a/llvm/test/MC/RISCV/rv64Zbt-invalid.s b/llvm/test/MC/RISCV/rv64Zbt-invalid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64Zbt-invalid.s
@@ -0,0 +1,6 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+b,bt < %s 2>&1 | FileCheck %s
+
+# Too few operands
+fslw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+fsrw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/rv64Zbt-valid.s b/llvm/test/MC/RISCV/rv64Zbt-valid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64Zbt-valid.s
@@ -0,0 +1,20 @@
+# With B extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b < %s \
+# RUN:     | llvm-objdump -mattr=+b -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# With Bitmanip ternary extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+bt -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+bt < %s \
+# RUN:     | llvm-objdump -mattr=+bt -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: fslw  t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xbb,0x12,0xc3,0x3d]
+fslw t0, t1, t2, t3
+# CHECK-ASM-AND-OBJ: fsrw  t0, t1, t2, t3
+# CHECK-ASM: encoding: [0xbb,0x52,0xc3,0x3d]
+fsrw t0, t1, t2, t3
diff --git a/llvm/test/MC/RISCV/rv64b-aliases-valid.s b/llvm/test/MC/RISCV/rv64b-aliases-valid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64b-aliases-valid.s
@@ -0,0 +1,76 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+b -riscv-no-aliases \
+# RUN:     | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc %s  -triple=riscv64 -mattr=+b \
+# RUN:     | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+b < %s \
+# RUN:     | llvm-objdump -d -r -riscv-no-aliases -mattr=+b - \
+# RUN:     | FileCheck -check-prefixes=CHECK-S-OBJ-NOALIAS %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+b < %s \
+# RUN:     | llvm-objdump -d -r -mattr=+b - \
+# RUN:     | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# The following check prefixes are used in this test:
+# CHECK-S-OBJ            Match both the .s and objdumped object output with
+#                        aliases enabled
+# CHECK-S-OBJ-NOALIAS    Match both the .s and objdumped object output with
+#                        aliases disabled
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 31
+# CHECK-S-OBJ: rev.w t0, t1
+rev.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 15
+# CHECK-S-OBJ: rev.h t0, t1
+rev.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 7
+# CHECK-S-OBJ: rev.b t0, t1
+rev.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 3
+# CHECK-S-OBJ: rev.n t0, t1
+rev.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 1
+# CHECK-S-OBJ: rev.p t0, t1
+rev.p x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 30
+# CHECK-S-OBJ: rev2.w t0, t1
+rev2.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 14
+# CHECK-S-OBJ: rev2.h t0, t1
+rev2.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 6
+# CHECK-S-OBJ: rev2.b t0, t1
+rev2.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 2
+# CHECK-S-OBJ: rev2.n t0, t1
+rev2.n x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 28
+# CHECK-S-OBJ: rev4.w t0, t1
+rev4.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 12
+# CHECK-S-OBJ: rev4.h t0, t1
+rev4.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 4
+# CHECK-S-OBJ: rev4.b t0, t1
+rev4.b x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 24
+# CHECK-S-OBJ: rev8.w t0, t1
+rev8.w x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 8
+# CHECK-S-OBJ: rev8.h t0, t1
+rev8.h x5, x6
+
+# CHECK-S-OBJ-NOALIAS: grevi t0, t1, 16
+# CHECK-S-OBJ: rev16.w t0, t1
+rev16.w x5, x6
diff --git a/llvm/test/MC/RISCV/rv64bc-valid.s b/llvm/test/MC/RISCV/rv64bc-valid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64bc-valid.s
@@ -0,0 +1,13 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+b,c -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+b,c < %s \
+# RUN:     | llvm-objdump -mattr=+b,c -d -r - \
+# RUN:     | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: c.not t0
+# CHECK-ASM: encoding: [0xc0,0x62]
+c.not t0
+
+# CHECK-ASM-AND-OBJ: c.zest.w t0
+# CHECK-ASM: encoding: [0xc0,0x6a]
+c.zest.w t0