Index: llvm/trunk/docs/CommandGuide/llvm-mca.rst
===================================================================
--- llvm/trunk/docs/CommandGuide/llvm-mca.rst
+++ llvm/trunk/docs/CommandGuide/llvm-mca.rst
@@ -92,6 +92,11 @@
  the AT&T (vic. Intel) assembly format for the code printed out by the tool in
  the analysis report.
 
+.. option:: -print-imm-hex
+
+ Prefer hex format for numeric literals in the output assembly printed as part
+ of the report.
+
 .. option:: -dispatch=<width>
 
  Specify a different dispatch width for the processor. The dispatch width
Index: llvm/trunk/test/tools/llvm-mca/X86/print-imm-hex-1.s
===================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/print-imm-hex-1.s
+++ llvm/trunk/test/tools/llvm-mca/X86/print-imm-hex-1.s
@@ -0,0 +1,30 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=false -instruction-info < %s | FileCheck %s --check-prefixes=ALL,DEFAULT
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=false -instruction-info -print-imm-hex=false < %s | FileCheck %s --check-prefixes=ALL,DEFAULT
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=false -instruction-info -print-imm-hex < %s | FileCheck %s --check-prefixes=ALL,HEX
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=false -instruction-info -print-imm-hex=true < %s | FileCheck %s --check-prefixes=ALL,HEX
+
+  shl $5,    %eax
+  shl $0x5,  %eax
+  shl $5h,   %eax
+  shl $101b, %eax
+
+# ALL:          Instruction Info:
+# ALL-NEXT:     [1]: #uOps
+# ALL-NEXT:     [2]: Latency
+# ALL-NEXT:     [3]: RThroughput
+# ALL-NEXT:     [4]: MayLoad
+# ALL-NEXT:     [5]: MayStore
+# ALL-NEXT:     [6]: HasSideEffects (U)
+
+# ALL:          [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+
+# DEFAULT-NEXT:  1      1     0.50                        shll	$5, %eax
+# DEFAULT-NEXT:  1      1     0.50                        shll	$5, %eax
+# DEFAULT-NEXT:  1      1     0.50                        shll	$5, %eax
+# DEFAULT-NEXT:  1      1     0.50                        shll	$5, %eax
+
+# HEX-NEXT:      1      1     0.50                        shll	$0x5, %eax
+# HEX-NEXT:      1      1     0.50                        shll	$0x5, %eax
+# HEX-NEXT:      1      1     0.50                        shll	$0x5, %eax
+# HEX-NEXT:      1      1     0.50                        shll	$0x5, %eax
Index: llvm/trunk/test/tools/llvm-mca/X86/print-imm-hex-2.s
===================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/print-imm-hex-2.s
+++ llvm/trunk/test/tools/llvm-mca/X86/print-imm-hex-2.s
@@ -0,0 +1,39 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=false -instruction-info < %s | FileCheck %s --check-prefix=DEFAULT
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=false -instruction-info -print-imm-hex=false < %s | FileCheck %s --check-prefix=DEFAULT
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=false -instruction-info -print-imm-hex < %s | FileCheck %s --check-prefix=HEX
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-views=false -instruction-info -print-imm-hex=true < %s | FileCheck %s --check-prefix=HEX
+
+  .intel_syntax noprefix
+  shl eax, 8
+  shl eax, 0x8
+  shl eax, 8h
+  shl eax, 1000b
+
+# DEFAULT:      Instruction Info:
+# DEFAULT-NEXT: [1]: #uOps
+# DEFAULT-NEXT: [2]: Latency
+# DEFAULT-NEXT: [3]: RThroughput
+# DEFAULT-NEXT: [4]: MayLoad
+# DEFAULT-NEXT: [5]: MayStore
+# DEFAULT-NEXT: [6]: HasSideEffects (U)
+
+# HEX:          Instruction Info:
+# HEX-NEXT:     [1]: #uOps
+# HEX-NEXT:     [2]: Latency
+# HEX-NEXT:     [3]: RThroughput
+# HEX-NEXT:     [4]: MayLoad
+# HEX-NEXT:     [5]: MayStore
+# HEX-NEXT:     [6]: HasSideEffects (U)
+
+# DEFAULT:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# DEFAULT-NEXT:  1      1     0.50                        shl	eax, 8
+# DEFAULT-NEXT:  1      1     0.50                        shl	eax, 8
+# DEFAULT-NEXT:  1      1     0.50                        shl	eax, 8
+# DEFAULT-NEXT:  1      1     0.50                        shl	eax, 8
+
+# HEX:          [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# HEX-NEXT:      1      1     0.50                        shl	eax, 0x8
+# HEX-NEXT:      1      1     0.50                        shl	eax, 0x8
+# HEX-NEXT:      1      1     0.50                        shl	eax, 0x8
+# HEX-NEXT:      1      1     0.50                        shl	eax, 0x8
Index: llvm/trunk/tools/llvm-mca/CodeRegionGenerator.cpp
===================================================================
--- llvm/trunk/tools/llvm-mca/CodeRegionGenerator.cpp
+++ llvm/trunk/tools/llvm-mca/CodeRegionGenerator.cpp
@@ -118,6 +118,8 @@
   MCAsmLexer &Lexer = Parser->getLexer();
   MCACommentConsumer CC(Regions);
   Lexer.setCommentConsumer(&CC);
+  // Enable support for MASM literal numbers (example: 05h, 101b).
+  Lexer.setLexMasmIntegers(true);
 
   std::unique_ptr<MCTargetAsmParser> TAP(
       TheTarget.createMCAsmParser(STI, *Parser, MCII, Opts));
Index: llvm/trunk/tools/llvm-mca/llvm-mca.cpp
===================================================================
--- llvm/trunk/tools/llvm-mca/llvm-mca.cpp
+++ llvm/trunk/tools/llvm-mca/llvm-mca.cpp
@@ -88,6 +88,10 @@
                      cl::desc("Syntax variant to use for output printing"),
                      cl::cat(ToolOptions), cl::init(-1));
 
+static cl::opt<bool>
+    PrintImmHex("print-imm-hex", cl::cat(ToolOptions), cl::init(false),
+                cl::desc("Prefer hex format when printing immediate values"));
+
 static cl::opt<unsigned> Iterations("iterations",
                                     cl::desc("Number of iterations to run"),
                                     cl::cat(ToolOptions), cl::init(0));
@@ -396,6 +400,9 @@
     return 1;
   }
 
+  // Set the display preference for hex vs. decimal immediates.
+  IP->setPrintImmHex(PrintImmHex);
+
   std::unique_ptr<ToolOutputFile> TOF = std::move(*OF);
 
   const MCSchedModel &SM = STI->getSchedModel();