Index: llvm/trunk/lib/Target/PowerPC/PPCMIPeephole.cpp
===================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ llvm/trunk/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -1426,6 +1426,12 @@
   if (!MRI->hasOneNonDBGUse(SrcReg))
     return false;
 
+  assert(SrcMI->getNumOperands() == 2 && "EXTSW should have 2 operands");
+  assert(SrcMI->getOperand(1).isReg() &&
+         "EXTSW's second operand should be a register");
+  if (!Register::isVirtualRegister(SrcMI->getOperand(1).getReg()))
+    return false;
+
   LLVM_DEBUG(dbgs() << "Combining pair: ");
   LLVM_DEBUG(SrcMI->dump());
   LLVM_DEBUG(MI.dump());
Index: llvm/trunk/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir
===================================================================
--- llvm/trunk/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir
+++ llvm/trunk/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir
@@ -20,10 +20,11 @@
   ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   liveins: $x3
+  ; CHECK:   [[EXTSW:%[0-9]+]]:g8rc = EXTSW $x3
   ; CHECK:   [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDIo8_]], 2, 61
   ; CHECK:   $x3 = COPY [[RLDICR]]
-  ; CHECK:   [[EXTSWSLI:%[0-9]+]]:g8rc = EXTSWSLI $x3, 2, implicit-def $carry
-  ; CHECK:   [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY3]], [[EXTSWSLI]]
+  ; CHECK:   [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
+  ; CHECK:   [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY3]], [[RLDICR1]]
   ; CHECK:   $x3 = COPY [[ADD8_]]
   ; CHECK:   BLR8 implicit $lr8, implicit $rm, implicit $x3
   ; CHECK: bb.2: