Index: lib/Target/ARM/ARMInstrThumb2.td =================================================================== --- lib/Target/ARM/ARMInstrThumb2.td +++ lib/Target/ARM/ARMInstrThumb2.td @@ -5221,7 +5221,7 @@ def t2WhileLoopStart : t2PseudoInst<(outs), (ins rGPR:$elts, brtarget:$target), - 4, IIC_Br, []>, + 8, IIC_Br, []>, Sched<[WriteBr]>; def t2LoopEnd : Index: lib/Target/ARM/ARMLowOverheadLoops.cpp =================================================================== --- lib/Target/ARM/ARMLowOverheadLoops.cpp +++ lib/Target/ARM/ARMLowOverheadLoops.cpp @@ -207,9 +207,13 @@ return false; } - if (!End->getOperand(1).isMBB() || - End->getOperand(1).getMBB() != ML->getHeader()) - report_fatal_error("Expected LoopEnd to target Loop Header"); + if (!End->getOperand(1).isMBB()) + report_fatal_error("Expected LoopEnd to target basic block"); + + // TODO Maybe there's cases where the target doesn't have to be the header, + // but for now be safe and revert. + if (End->getOperand(1).getMBB() != ML->getHeader()) + Revert = true; // The WLS and LE instructions have 12-bits for the label offset. WLS // requires a positive offset, while LE uses negative. Index: test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir =================================================================== --- /dev/null +++ test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir @@ -0,0 +1,395 @@ +# RUN: llc -mtriple=thumbv8.1m.main -mattr=+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s +# CHECK-NOT: t2DLS +# CHECK: bb.5.for.inc16: +# CHECK: t2CMPri $lr, 0, 14 +# CHECK: t2Bcc %bb.6, 1 +# CHECK: tB %bb.2 +--- | + define void @header_not_target_unrolled_loop(i32* nocapture %v, i32 %n) { + entry: + %cmp56 = icmp sgt i32 %n, 1 + br i1 %cmp56, label %for.cond1.preheader.preheader, label %for.end20 + + for.cond1.preheader.preheader: ; preds = %entry + br label %for.cond1.preheader + + for.cond.loopexit: ; preds = %for.inc16, %for.cond1.preheader + %cmp = icmp sgt i32 %gap.057.in, 3 + br i1 %cmp, label %for.cond1.preheader, label %for.end20 + + for.cond1.preheader: ; preds = %for.cond1.preheader.preheader, %for.cond.loopexit + %gap.057.in = phi i32 [ %gap.057, %for.cond.loopexit ], [ %n, %for.cond1.preheader.preheader ] + %gap.057 = sdiv i32 %gap.057.in, 2 + %cmp252 = icmp slt i32 %gap.057, %n + %tmp = sub i32 %n, %gap.057 + br i1 %cmp252, label %for.cond4.preheader.preheader, label %for.cond.loopexit + + for.cond4.preheader.preheader: ; preds = %for.cond1.preheader + %tmp1 = mul i32 %gap.057, -16 + %tmp2 = mul i32 %gap.057, -4 + %tmp3 = mul i32 %gap.057, -8 + %tmp4 = mul i32 %gap.057, -12 + %tmp5 = mul i32 %gap.057, -3 + %tmp6 = mul i32 %gap.057, -2 + %tmp7 = mul nsw i32 %gap.057, -1 + call void @llvm.set.loop.iterations.i32(i32 %tmp) + br label %for.cond4.preheader + + for.cond4.preheader: ; preds = %for.inc16, %for.cond4.preheader.preheader + %lsr.iv = phi i32* [ %v, %for.cond4.preheader.preheader ], [ %scevgep, %for.inc16 ] + %i.053 = phi i32 [ %inc, %for.inc16 ], [ %gap.057, %for.cond4.preheader.preheader ] + %tmp8 = phi i32 [ %tmp, %for.cond4.preheader.preheader ], [ %tmp16, %for.inc16 ] + %j.048 = sub nsw i32 %i.053, %gap.057 + %cmp549 = icmp sgt i32 %j.048, -1 + br i1 %cmp549, label %land.rhs.preheader, label %for.inc16 + + land.rhs.preheader: ; preds = %for.cond4.preheader + br label %land.rhs + + land.rhs: ; preds = %land.rhs.preheader, %for.body8.3 + %lsr.iv58 = phi i32* [ %tmp40, %for.body8.3 ], [ %lsr.iv, %land.rhs.preheader ] + %j.051 = phi i32 [ %j.0.3, %for.body8.3 ], [ %j.048, %land.rhs.preheader ] + %tmp9 = load i32, i32* %lsr.iv58, align 4 + %sunkaddr = mul i32 %gap.057, 4 + %0 = bitcast i32* %lsr.iv58 to i8* + %sunkaddr23 = getelementptr i8, i8* %0, i32 %sunkaddr + %1 = bitcast i8* %sunkaddr23 to i32* + %tmp12 = load i32, i32* %1, align 4 + %cmp7 = icmp sgt i32 %tmp9, %tmp12 + br i1 %cmp7, label %for.body8, label %for.inc16 + + for.body8: ; preds = %land.rhs + store i32 %tmp12, i32* %lsr.iv58, align 4 + %sunkaddr24 = mul i32 %gap.057, 4 + %2 = bitcast i32* %lsr.iv58 to i8* + %sunkaddr25 = getelementptr i8, i8* %2, i32 %sunkaddr24 + %3 = bitcast i8* %sunkaddr25 to i32* + store i32 %tmp9, i32* %3, align 4 + %j.0 = sub nsw i32 %j.051, %gap.057 + %tmp15 = add i32 %tmp7, %j.051 + %cmp5 = icmp sgt i32 %tmp15, -1 + br i1 %cmp5, label %land.rhs.1, label %for.inc16 + + for.inc16: ; preds = %for.body8.3, %land.rhs.3, %for.body8.2, %land.rhs.2, %for.body8.1, %land.rhs.1, %for.body8, %land.rhs, %for.cond4.preheader + %inc = add nsw i32 %i.053, 1 + %scevgep = getelementptr i32, i32* %lsr.iv, i32 1 + %tmp16 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp8, i32 1) + %tmp17 = icmp ne i32 %tmp16, 0 + br i1 %tmp17, label %for.cond4.preheader, label %for.cond.loopexit + + for.end20: ; preds = %for.cond.loopexit, %entry + ret void + + land.rhs.1: ; preds = %for.body8 + %4 = bitcast i32* %lsr.iv58 to i8* + %uglygep17 = getelementptr i8, i8* %4, i32 %tmp2 + %uglygep1718 = bitcast i8* %uglygep17 to i32* + %tmp19 = load i32, i32* %uglygep1718, align 4 + %tmp20 = load i32, i32* %lsr.iv58, align 4 + %cmp7.1 = icmp sgt i32 %tmp19, %tmp20 + br i1 %cmp7.1, label %for.body8.1, label %for.inc16 + + for.body8.1: ; preds = %land.rhs.1 + %5 = bitcast i32* %lsr.iv58 to i8* + %uglygep15 = getelementptr i8, i8* %5, i32 %tmp2 + %uglygep1516 = bitcast i8* %uglygep15 to i32* + store i32 %tmp20, i32* %uglygep1516, align 4 + store i32 %tmp19, i32* %lsr.iv58, align 4 + %j.0.1 = sub nsw i32 %j.0, %gap.057 + %tmp23 = add i32 %tmp6, %j.051 + %cmp5.1 = icmp sgt i32 %tmp23, -1 + br i1 %cmp5.1, label %land.rhs.2, label %for.inc16 + + land.rhs.2: ; preds = %for.body8.1 + %6 = bitcast i32* %lsr.iv58 to i8* + %uglygep5 = getelementptr i8, i8* %6, i32 %tmp3 + %uglygep56 = bitcast i8* %uglygep5 to i32* + %tmp25 = load i32, i32* %uglygep56, align 4 + %uglygep13 = getelementptr i8, i8* %6, i32 %tmp2 + %uglygep1314 = bitcast i8* %uglygep13 to i32* + %tmp26 = load i32, i32* %uglygep1314, align 4 + %cmp7.2 = icmp sgt i32 %tmp25, %tmp26 + br i1 %cmp7.2, label %for.body8.2, label %for.inc16 + + for.body8.2: ; preds = %land.rhs.2 + %7 = bitcast i32* %lsr.iv58 to i8* + %uglygep3 = getelementptr i8, i8* %7, i32 %tmp3 + %uglygep34 = bitcast i8* %uglygep3 to i32* + store i32 %tmp26, i32* %uglygep34, align 4 + %uglygep11 = getelementptr i8, i8* %7, i32 %tmp2 + %uglygep1112 = bitcast i8* %uglygep11 to i32* + store i32 %tmp25, i32* %uglygep1112, align 4 + %j.0.2 = sub nsw i32 %j.0.1, %gap.057 + %tmp31 = add i32 %tmp5, %j.051 + %cmp5.2 = icmp sgt i32 %tmp31, -1 + br i1 %cmp5.2, label %land.rhs.3, label %for.inc16 + + land.rhs.3: ; preds = %for.body8.2 + %8 = bitcast i32* %lsr.iv58 to i8* + %uglygep9 = getelementptr i8, i8* %8, i32 %tmp4 + %uglygep910 = bitcast i8* %uglygep9 to i32* + %tmp33 = load i32, i32* %uglygep910, align 4 + %uglygep1 = getelementptr i8, i8* %8, i32 %tmp3 + %uglygep12 = bitcast i8* %uglygep1 to i32* + %tmp34 = load i32, i32* %uglygep12, align 4 + %cmp7.3 = icmp sgt i32 %tmp33, %tmp34 + br i1 %cmp7.3, label %for.body8.3, label %for.inc16 + + for.body8.3: ; preds = %land.rhs.3 + %9 = bitcast i32* %lsr.iv58 to i8* + %tmp35 = bitcast i32* %lsr.iv58 to i1* + %uglygep7 = getelementptr i8, i8* %9, i32 %tmp4 + %uglygep78 = bitcast i8* %uglygep7 to i32* + store i32 %tmp34, i32* %uglygep78, align 4 + %sunkaddr80 = getelementptr i8, i8* %9, i32 %tmp3 + %tmp39 = bitcast i8* %sunkaddr80 to i32* + store i32 %tmp33, i32* %tmp39, align 4 + %j.0.3 = sub nsw i32 %j.0.2, %gap.057 + %scevgep60 = getelementptr i1, i1* %tmp35, i32 %tmp1 + %tmp40 = bitcast i1* %scevgep60 to i32* + %cmp5.3 = icmp sgt i32 %j.0.3, -1 + br i1 %cmp5.3, label %land.rhs, label %for.inc16 + } + + declare void @llvm.set.loop.iterations.i32(i32) #0 + declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0 + + attributes #0 = { noduplicate nounwind } + attributes #1 = { nounwind } + +... +--- +name: header_not_target_unrolled_loop +alignment: 1 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: false +hasWinCFI: false +registers: [] +liveins: + - { reg: '$r0', virtual-reg: '' } + - { reg: '$r1', virtual-reg: '' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 56 + offsetAdjustment: 0 + maxAlignment: 4 + adjustsStack: false + hasCalls: false + stackProtector: '' + maxCallFrameSize: 0 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: spill-slot, offset: -40, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: spill-slot, offset: -44, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: '', type: spill-slot, offset: -48, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 3, name: '', type: spill-slot, offset: -52, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 4, name: '', type: spill-slot, offset: -56, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 5, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 6, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$r11', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 7, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$r10', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 8, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$r9', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 9, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 10, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 11, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 12, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 13, name: '', type: spill-slot, offset: -36, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +callSites: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.entry: + successors: %bb.1(0x40000000), %bb.14(0x40000000) + + $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr + frame-setup CFI_INSTRUCTION def_cfa_offset 36 + frame-setup CFI_INSTRUCTION offset $lr, -4 + frame-setup CFI_INSTRUCTION offset $r11, -8 + frame-setup CFI_INSTRUCTION offset $r10, -12 + frame-setup CFI_INSTRUCTION offset $r9, -16 + frame-setup CFI_INSTRUCTION offset $r8, -20 + frame-setup CFI_INSTRUCTION offset $r7, -24 + frame-setup CFI_INSTRUCTION offset $r6, -28 + frame-setup CFI_INSTRUCTION offset $r5, -32 + frame-setup CFI_INSTRUCTION offset $r4, -36 + $sp = frame-setup tSUBspi $sp, 5, 14, $noreg + frame-setup CFI_INSTRUCTION def_cfa_offset 56 + tCMPi8 renamable $r1, 2, 14, $noreg, implicit-def $cpsr + t2STRDi8 killed $r0, killed $r1, $sp, 0, 14, $noreg :: (store 4 into %stack.4), (store 4 into %stack.3) + tBcc %bb.14, 11, killed $cpsr + + bb.1: + successors: %bb.3(0x80000000) + + renamable $r3 = tLDRspi $sp, 1, 14, $noreg :: (load 4 from %stack.3) + tB %bb.3, 14, $noreg + + bb.2.for.cond.loopexit: + successors: %bb.3(0x7c000000), %bb.14(0x04000000) + + renamable $r0 = tLDRspi $sp, 2, 14, $noreg :: (load 4 from %stack.2) + tCMPi8 killed renamable $r0, 4, 14, $noreg, implicit-def $cpsr + tBcc %bb.14, 11, killed $cpsr + + bb.3.for.cond1.preheader: + successors: %bb.4(0x40000000), %bb.2(0x40000000) + + renamable $r0 = t2ADDrs renamable $r3, renamable $r3, 251, 14, $noreg, $noreg + renamable $r1 = tLDRspi $sp, 1, 14, $noreg :: (load 4 from %stack.3) + tSTRspi killed renamable $r3, $sp, 2, 14, $noreg :: (store 4 into %stack.2) + renamable $r3, dead $cpsr = tASRri renamable $r0, 1, 14, $noreg + t2CMPrs killed renamable $r1, renamable $r0, 9, 14, $noreg, implicit-def $cpsr + tBcc %bb.2, 13, killed $cpsr + + bb.4.for.cond4.preheader.preheader: + successors: %bb.7(0x50000000), %bb.5(0x30000000) + + renamable $r1 = tLDRspi $sp, 1, 14, $noreg :: (load 4 from %stack.3) + renamable $r10 = t2RSBri renamable $r3, 0, 14, $noreg, $noreg + $r12 = tMOVr $r3, 14, $noreg + renamable $lr = t2SUBrs killed renamable $r1, killed renamable $r0, 9, 14, $noreg, $noreg + renamable $r0, dead $cpsr = tMOVi8 0, 14, $noreg + renamable $r11 = t2SUBrs renamable $r0, renamable $r3, 10, 14, $noreg, $noreg + renamable $r5 = t2SUBrs renamable $r0, renamable $r3, 26, 14, $noreg, $noreg + renamable $r6 = t2SUBrs renamable $r0, renamable $r3, 18, 14, $noreg, $noreg + renamable $r0 = t2SUBrs killed renamable $r0, renamable $r3, 34, 14, $noreg, $noreg + t2DoLoopStart renamable $lr + tSTRspi killed renamable $r0, $sp, 3, 14, $noreg :: (store 4 into %stack.1) + renamable $r0 = t2SUBrs renamable $r3, renamable $r3, 18, 14, $noreg, $noreg + tSTRspi renamable $r0, $sp, 4, 14, $noreg :: (store 4 into %stack.0) + renamable $r7, dead $cpsr = tLSLri killed renamable $r0, 2, 14, $noreg + renamable $r0 = tLDRspi $sp, 0, 14, $noreg :: (load 4 from %stack.4) + renamable $r8 = nsw t2SUBrr renamable $r12, renamable $r3, 14, $noreg, def $cpsr + tBcc %bb.7, 5, killed $cpsr + + bb.5.for.inc16: + successors: %bb.6(0x7c000000), %bb.2(0x04000000) + + renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14, $noreg + renamable $r12 = nsw t2ADDri killed renamable $r12, 1, 14, $noreg, $noreg + renamable $lr = t2LoopDec killed renamable $lr, 1 + t2LoopEnd renamable $lr, %bb.6 + tB %bb.2, 14, $noreg + + bb.6.for.cond4.preheader: + successors: %bb.7(0x50000000), %bb.5(0x30000000) + + renamable $r8 = nsw t2SUBrr renamable $r12, renamable $r3, 14, $noreg, def $cpsr + tBcc %bb.5, 4, killed $cpsr + + bb.7.land.rhs.preheader: + successors: %bb.8(0x80000000) + + $r4 = tMOVr $r0, 14, $noreg + + bb.8.land.rhs: + successors: %bb.5(0x0ba10000), %bb.9(0x745f0000) + + renamable $r2 = t2LDRs renamable $r4, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.1) + renamable $r1 = tLDRi renamable $r4, 0, 14, $noreg :: (load 4 from %ir.lsr.iv58) + tCMPr renamable $r1, renamable $r2, 14, $noreg, implicit-def $cpsr + t2IT 12, 1, implicit-def $itstate + tSTRi killed renamable $r2, renamable $r4, 0, 12, $cpsr, implicit $itstate :: (store 4 into %ir.lsr.iv58) + t2STRs killed renamable $r1, renamable $r4, renamable $r3, 2, 12, $cpsr, implicit $itstate :: (store 4 into %ir.3) + renamable $r1 = t2ADDrr renamable $r10, renamable $r8, 12, $cpsr, $noreg, implicit $itstate + t2CMPri killed renamable $r1, -1, 12, killed $cpsr, implicit-def $cpsr, implicit killed $itstate + t2IT 12, 2, implicit-def $itstate + renamable $r1 = tLDRr renamable $r4, $r6, 12, $cpsr, implicit $itstate :: (load 4 from %ir.uglygep1718) + renamable $r2 = tLDRi renamable $r4, 0, 12, $cpsr, implicit $itstate :: (load 4 from %ir.lsr.iv58) + tCMPr renamable $r1, renamable $r2, 12, killed $cpsr, implicit-def $cpsr, implicit killed $itstate + tBcc %bb.5, 13, killed $cpsr + + bb.9.for.body8.1: + successors: %bb.10(0x7c000000), %bb.5(0x04000000) + + tSTRr killed renamable $r2, renamable $r4, $r6, 14, $noreg :: (store 4 into %ir.uglygep1516) + tSTRi killed renamable $r1, renamable $r4, 0, 14, $noreg :: (store 4 into %ir.lsr.iv58) + dead renamable $r1 = t2ADDrr renamable $r11, renamable $r8, 14, $noreg, def $cpsr + tBcc %bb.5, 4, killed $cpsr + + bb.10.land.rhs.2: + successors: %bb.11(0x7c000000), %bb.5(0x04000000) + + renamable $r2 = tLDRr renamable $r4, $r6, 14, $noreg :: (load 4 from %ir.uglygep1314) + renamable $r1 = tLDRr renamable $r4, $r5, 14, $noreg :: (load 4 from %ir.uglygep56) + tCMPr renamable $r1, renamable $r2, 14, $noreg, implicit-def $cpsr + tBcc %bb.5, 13, killed $cpsr + + bb.11.for.body8.2: + successors: %bb.12(0x7c000000), %bb.5(0x04000000) + + tSTRr killed renamable $r2, renamable $r4, $r5, 14, $noreg :: (store 4 into %ir.uglygep34) + tSTRr killed renamable $r1, renamable $r4, $r6, 14, $noreg :: (store 4 into %ir.uglygep1112) + renamable $r1 = tLDRspi $sp, 4, 14, $noreg :: (load 4 from %stack.0) + dead renamable $r1 = t2ADDrr killed renamable $r1, renamable $r8, 14, $noreg, def $cpsr + tBcc %bb.5, 4, killed $cpsr + + bb.12.land.rhs.3: + successors: %bb.13(0x7c000000), %bb.5(0x04000000) + + renamable $r9 = t2LDRs renamable $r4, renamable $r5, 0, 14, $noreg :: (load 4 from %ir.uglygep12) + renamable $r1 = tLDRr renamable $r4, $r7, 14, $noreg :: (load 4 from %ir.uglygep910) + tCMPhir renamable $r1, renamable $r9, 14, $noreg, implicit-def $cpsr + tBcc %bb.5, 13, killed $cpsr + + bb.13.for.body8.3: + successors: %bb.8(0x7c000000), %bb.5(0x04000000) + + renamable $r2 = nsw t2SUBrr killed renamable $r8, renamable $r3, 14, $noreg, $noreg + t2STRs killed renamable $r9, renamable $r4, renamable $r7, 0, 14, $noreg :: (store 4 into %ir.uglygep78) + renamable $r2, dead $cpsr = nsw tSUBrr killed renamable $r2, renamable $r3, 14, $noreg + tSTRr killed renamable $r1, renamable $r4, $r5, 14, $noreg :: (store 4 into %ir.tmp39) + renamable $r2, dead $cpsr = nsw tSUBrr killed renamable $r2, renamable $r3, 14, $noreg + renamable $r8 = nsw t2SUBrr killed renamable $r2, renamable $r3, 14, $noreg, $noreg + renamable $r1 = tLDRspi $sp, 3, 14, $noreg :: (load 4 from %stack.1) + t2CMPri renamable $r8, -1, 14, $noreg, implicit-def $cpsr + renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r1, 14, $noreg + tBcc %bb.8, 12, killed $cpsr + tB %bb.5, 14, $noreg + + bb.14.for.end20: + $sp = tADDspi $sp, 5, 14, $noreg + $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc + +...