Index: llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -747,6 +747,42 @@
     Observer.changedInstr(MI);
     return Legalized;
   }
+  case TargetOpcode::G_ICMP: {
+    uint64_t SrcSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
+    if (NarrowSize * 2 != SrcSize)
+      return UnableToLegalize;
+
+    Observer.changingInstr(MI);
+    Register LHSL = MRI.createGenericVirtualRegister(NarrowTy);
+    Register LHSH = MRI.createGenericVirtualRegister(NarrowTy);
+    MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2).getReg());
+
+    Register RHSL = MRI.createGenericVirtualRegister(NarrowTy);
+    Register RHSH = MRI.createGenericVirtualRegister(NarrowTy);
+    MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3).getReg());
+
+    CmpInst::Predicate Pred =
+        static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
+
+    if (Pred == CmpInst::ICMP_EQ || Pred == CmpInst::ICMP_NE) {
+      MachineInstrBuilder XorL = MIRBuilder.buildXor(NarrowTy, LHSL, RHSL);
+      MachineInstrBuilder XorH = MIRBuilder.buildXor(NarrowTy, LHSH, RHSH);
+      MachineInstrBuilder Or = MIRBuilder.buildOr(NarrowTy, XorL, XorH);
+      MachineInstrBuilder Zero = MIRBuilder.buildConstant(NarrowTy, 0);
+      MIRBuilder.buildICmp(Pred, MI.getOperand(0).getReg(), Or, Zero);
+    } else {
+      const LLT s1 = LLT::scalar(1);
+      MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, s1, LHSH, RHSH);
+      MachineInstrBuilder CmpHEQ =
+          MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, s1, LHSH, RHSH);
+      MachineInstrBuilder CmpLU = MIRBuilder.buildICmp(
+          ICmpInst::getUnsignedPredicate(Pred), s1, LHSL, RHSL);
+      MIRBuilder.buildSelect(MI.getOperand(0).getReg(), CmpHEQ, CmpLU, CmpH);
+    }
+    Observer.changedInstr(MI);
+    MI.eraseFromParent();
+    return Legalized;
+  }
   }
 }
 
Index: llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp
+++ llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp
@@ -81,7 +81,8 @@
     .minScalar(1, s32);
 
   getActionDefinitionsBuilder(G_ICMP)
-      .legalFor({{s32, s32}})
+      .legalForCartesianProduct({s32}, {s32, p0})
+      .clampScalar(1, s32, s32)
       .minScalar(0, s32);
 
   getActionDefinitionsBuilder(G_CONSTANT)
Index: llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir
===================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir
@@ -2,20 +2,22 @@
 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
 --- |
 
-  define void @eq() {entry: ret void}
-  define void @ne() {entry: ret void}
-  define void @sgt() {entry: ret void}
-  define void @sge() {entry: ret void}
-  define void @slt() {entry: ret void}
-  define void @sle() {entry: ret void}
-  define void @ugt() {entry: ret void}
-  define void @uge() {entry: ret void}
-  define void @ult() {entry: ret void}
-  define void @ule() {entry: ret void}
+  define void @eq_i32() {entry: ret void}
+  define void @ne_i32() {entry: ret void}
+  define void @sgt_i32() {entry: ret void}
+  define void @sge_i32() {entry: ret void}
+  define void @slt_i32() {entry: ret void}
+  define void @sle_i32() {entry: ret void}
+  define void @ugt_i32() {entry: ret void}
+  define void @uge_i32() {entry: ret void}
+  define void @ult_i32() {entry: ret void}
+  define void @ule_i32() {entry: ret void}
+  define void @eq_ptr() {entry: ret void}
+
 
 ...
 ---
-name:            eq
+name:            eq_i32
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -24,28 +26,24 @@
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: eq
+    ; MIPS32-LABEL: name: eq_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY]], [[COPY1]]
     ; MIPS32: [[SLTiu:%[0-9]+]]:gpr32 = SLTiu [[XOR]], 1
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTiu]], [[ORi]]
-    ; MIPS32: $v0 = COPY [[AND]]
+    ; MIPS32: $v0 = COPY [[SLTiu]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(eq), %0(s32), %1
-    %5:gprb(s32) = G_CONSTANT i32 1
-    %6:gprb(s32) = COPY %4(s32)
-    %3:gprb(s32) = G_AND %6, %5
+    %3:gprb(s32) = COPY %4(s32)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            ne
+name:            ne_i32
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -54,28 +52,24 @@
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: ne
+    ; MIPS32-LABEL: name: ne_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY]], [[COPY1]]
     ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu $zero, [[XOR]]
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi]]
-    ; MIPS32: $v0 = COPY [[AND]]
+    ; MIPS32: $v0 = COPY [[SLTu]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(ne), %0(s32), %1
-    %5:gprb(s32) = G_CONSTANT i32 1
-    %6:gprb(s32) = COPY %4(s32)
-    %3:gprb(s32) = G_AND %6, %5
+    %3:gprb(s32) = COPY %4(s32)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            sgt
+name:            sgt_i32
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -84,27 +78,23 @@
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: sgt
+    ; MIPS32-LABEL: name: sgt_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY1]], [[COPY]]
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLT]], [[ORi]]
-    ; MIPS32: $v0 = COPY [[AND]]
+    ; MIPS32: $v0 = COPY [[SLT]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(sgt), %0(s32), %1
-    %5:gprb(s32) = G_CONSTANT i32 1
-    %6:gprb(s32) = COPY %4(s32)
-    %3:gprb(s32) = G_AND %6, %5
+    %3:gprb(s32) = COPY %4(s32)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            sge
+name:            sge_i32
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -113,28 +103,24 @@
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: sge
+    ; MIPS32-LABEL: name: sge_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY]], [[COPY1]]
     ; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLT]], 1
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[XORi]], [[ORi]]
-    ; MIPS32: $v0 = COPY [[AND]]
+    ; MIPS32: $v0 = COPY [[XORi]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(sge), %0(s32), %1
-    %5:gprb(s32) = G_CONSTANT i32 1
-    %6:gprb(s32) = COPY %4(s32)
-    %3:gprb(s32) = G_AND %6, %5
+    %3:gprb(s32) = COPY %4(s32)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            slt
+name:            slt_i32
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -143,27 +129,23 @@
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: slt
+    ; MIPS32-LABEL: name: slt_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY]], [[COPY1]]
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLT]], [[ORi]]
-    ; MIPS32: $v0 = COPY [[AND]]
+    ; MIPS32: $v0 = COPY [[SLT]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(slt), %0(s32), %1
-    %5:gprb(s32) = G_CONSTANT i32 1
-    %6:gprb(s32) = COPY %4(s32)
-    %3:gprb(s32) = G_AND %6, %5
+    %3:gprb(s32) = COPY %4(s32)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            sle
+name:            sle_i32
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -172,28 +154,24 @@
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: sle
+    ; MIPS32-LABEL: name: sle_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY1]], [[COPY]]
     ; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLT]], 1
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[XORi]], [[ORi]]
-    ; MIPS32: $v0 = COPY [[AND]]
+    ; MIPS32: $v0 = COPY [[XORi]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(sle), %0(s32), %1
-    %5:gprb(s32) = G_CONSTANT i32 1
-    %6:gprb(s32) = COPY %4(s32)
-    %3:gprb(s32) = G_AND %6, %5
+    %3:gprb(s32) = COPY %4(s32)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            ugt
+name:            ugt_i32
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -202,27 +180,23 @@
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: ugt
+    ; MIPS32-LABEL: name: ugt_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY1]], [[COPY]]
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi]]
-    ; MIPS32: $v0 = COPY [[AND]]
+    ; MIPS32: $v0 = COPY [[SLTu]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(ugt), %0(s32), %1
-    %5:gprb(s32) = G_CONSTANT i32 1
-    %6:gprb(s32) = COPY %4(s32)
-    %3:gprb(s32) = G_AND %6, %5
+    %3:gprb(s32) = COPY %4(s32)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            uge
+name:            uge_i32
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -231,28 +205,24 @@
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: uge
+    ; MIPS32-LABEL: name: uge_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY]], [[COPY1]]
     ; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLTu]], 1
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[XORi]], [[ORi]]
-    ; MIPS32: $v0 = COPY [[AND]]
+    ; MIPS32: $v0 = COPY [[XORi]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(uge), %0(s32), %1
-    %5:gprb(s32) = G_CONSTANT i32 1
-    %6:gprb(s32) = COPY %4(s32)
-    %3:gprb(s32) = G_AND %6, %5
+    %3:gprb(s32) = COPY %4(s32)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            ult
+name:            ult_i32
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -261,27 +231,23 @@
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: ult
+    ; MIPS32-LABEL: name: ult_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY]], [[COPY1]]
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi]]
-    ; MIPS32: $v0 = COPY [[AND]]
+    ; MIPS32: $v0 = COPY [[SLTu]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(ult), %0(s32), %1
-    %5:gprb(s32) = G_CONSTANT i32 1
-    %6:gprb(s32) = COPY %4(s32)
-    %3:gprb(s32) = G_AND %6, %5
+    %3:gprb(s32) = COPY %4(s32)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            ule
+name:            ule_i32
 alignment:       2
 legalized:       true
 regBankSelected: true
@@ -290,22 +256,44 @@
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: ule
+    ; MIPS32-LABEL: name: ule_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
     ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY1]], [[COPY]]
     ; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLTu]], 1
-    ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-    ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[XORi]], [[ORi]]
-    ; MIPS32: $v0 = COPY [[AND]]
+    ; MIPS32: $v0 = COPY [[XORi]]
     ; MIPS32: RetRA implicit $v0
     %0:gprb(s32) = COPY $a0
     %1:gprb(s32) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(ule), %0(s32), %1
-    %5:gprb(s32) = G_CONSTANT i32 1
-    %6:gprb(s32) = COPY %4(s32)
-    %3:gprb(s32) = G_AND %6, %5
+    %3:gprb(s32) = COPY %4(s32)
+    $v0 = COPY %3(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            eq_ptr
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: eq_ptr
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY]], [[COPY1]]
+    ; MIPS32: [[SLTiu:%[0-9]+]]:gpr32 = SLTiu [[XOR]], 1
+    ; MIPS32: $v0 = COPY [[SLTiu]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %4:gprb(s32) = G_ICMP intpred(eq), %0(p0), %1
+    %3:gprb(s32) = COPY %4(s32)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
Index: llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir
===================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir
@@ -2,276 +2,503 @@
 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
 --- |
 
-  define void @eq() {entry: ret void}
-  define void @ne() {entry: ret void}
-  define void @sgt() {entry: ret void}
-  define void @sge() {entry: ret void}
-  define void @slt() {entry: ret void}
-  define void @sle() {entry: ret void}
-  define void @ugt() {entry: ret void}
-  define void @uge() {entry: ret void}
-  define void @ult() {entry: ret void}
-  define void @ule() {entry: ret void}
+  define void @ne_i32() {entry: ret void}
+  define void @eq_ptr() {entry: ret void}
+  define void @ult_i8() {entry: ret void}
+  define void @slt_i16() {entry: ret void}
+  define void @eq_i64() {entry: ret void}
+  define void @ne_i64() {entry: ret void}
+  define void @sgt_i64() {entry: ret void}
+  define void @sge_i64() {entry: ret void}
+  define void @slt_i64() {entry: ret void}
+  define void @sle_i64() {entry: ret void}
+  define void @ugt_i64() {entry: ret void}
+  define void @uge_i64() {entry: ret void}
+  define void @ult_i64() {entry: ret void}
+  define void @ule_i64() {entry: ret void}
 
 ...
 ---
-name:            eq
+name:            ne_i32
 alignment:       2
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: eq
+    ; MIPS32-LABEL: name: ne_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
     ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: $v0 = COPY [[COPY2]](s32)
     ; MIPS32: RetRA implicit $v0
     %0:_(s32) = COPY $a0
     %1:_(s32) = COPY $a1
-    %2:_(s1) = G_ICMP intpred(eq), %0(s32), %1
-    %3:_(s32) = G_ZEXT %2(s1)
+    %2:_(s1) = G_ICMP intpred(ne), %0(s32), %1
+    %3:_(s32) = G_ANYEXT %2(s1)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            ne
+name:            eq_ptr
 alignment:       2
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: ne
+    ; MIPS32-LABEL: name: eq_ptr
     ; MIPS32: liveins: $a0, $a1
-    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
-    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](p0), [[COPY1]]
     ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: $v0 = COPY [[COPY2]](s32)
     ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %2:_(s1) = G_ICMP intpred(ne), %0(s32), %1
-    %3:_(s32) = G_ZEXT %2(s1)
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %2:_(s1) = G_ICMP intpred(eq), %0(p0), %1
+    %3:_(s32) = G_ANYEXT %2(s1)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            sgt
+name:            ult_i8
 alignment:       2
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: sgt
+    ; MIPS32-LABEL: name: ult_i8
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
     ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+    ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+    ; MIPS32: $v0 = COPY [[COPY4]](s32)
     ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %2:_(s1) = G_ICMP intpred(sgt), %0(s32), %1
-    %3:_(s32) = G_ZEXT %2(s1)
-    $v0 = COPY %3(s32)
+    %2:_(s32) = COPY $a0
+    %0:_(s8) = G_TRUNC %2(s32)
+    %3:_(s32) = COPY $a1
+    %1:_(s8) = G_TRUNC %3(s32)
+    %4:_(s1) = G_ICMP intpred(ult), %0(s8), %1
+    %5:_(s32) = G_ANYEXT %4(s1)
+    $v0 = COPY %5(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            sge
+name:            slt_i16
 alignment:       2
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: sge
+    ; MIPS32-LABEL: name: slt_i16
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY]](s32), [[COPY1]]
+    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
+    ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+    ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+    ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+    ; MIPS32: $v0 = COPY [[COPY4]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %2:_(s32) = COPY $a0
+    %0:_(s16) = G_TRUNC %2(s32)
+    %3:_(s32) = COPY $a1
+    %1:_(s16) = G_TRUNC %3(s32)
+    %4:_(s1) = G_ICMP intpred(slt), %0(s16), %1
+    %5:_(s32) = G_ANYEXT %4(s1)
+    $v0 = COPY %5(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            eq_i64
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1, $a2, $a3
+
+    ; MIPS32-LABEL: name: eq_i64
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+    ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY2]]
+    ; MIPS32: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY3]]
+    ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR]], [[XOR1]]
+    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s32), [[C]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+    ; MIPS32: $v0 = COPY [[COPY4]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %2:_(s32) = COPY $a0
+    %3:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+    %4:_(s32) = COPY $a2
+    %5:_(s32) = COPY $a3
+    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
+    %6:_(s1) = G_ICMP intpred(eq), %0(s64), %1
+    %7:_(s32) = G_ANYEXT %6(s1)
+    $v0 = COPY %7(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            ne_i64
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1, $a2, $a3
+
+    ; MIPS32-LABEL: name: ne_i64
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+    ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY2]]
+    ; MIPS32: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY3]]
+    ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR]], [[XOR1]]
+    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[OR]](s32), [[C]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+    ; MIPS32: $v0 = COPY [[COPY4]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %2:_(s32) = COPY $a0
+    %3:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+    %4:_(s32) = COPY $a2
+    %5:_(s32) = COPY $a3
+    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
+    %6:_(s1) = G_ICMP intpred(ne), %0(s64), %1
+    %7:_(s32) = G_ANYEXT %6(s1)
+    $v0 = COPY %7(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            sgt_i64
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1, $a2, $a3
+
+    ; MIPS32-LABEL: name: sgt_i64
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
+    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
+    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+    ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]]
+    ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
+    ; MIPS32: $v0 = COPY [[COPY7]](s32)
     ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %2:_(s1) = G_ICMP intpred(sge), %0(s32), %1
-    %3:_(s32) = G_ZEXT %2(s1)
-    $v0 = COPY %3(s32)
+    %2:_(s32) = COPY $a0
+    %3:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+    %4:_(s32) = COPY $a2
+    %5:_(s32) = COPY $a3
+    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
+    %6:_(s1) = G_ICMP intpred(sgt), %0(s64), %1
+    %7:_(s32) = G_ANYEXT %6(s1)
+    $v0 = COPY %7(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            slt
+name:            sge_i64
 alignment:       2
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
-    liveins: $a0, $a1
+    liveins: $a0, $a1, $a2, $a3
 
-    ; MIPS32-LABEL: name: slt
-    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32-LABEL: name: sge_i64
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY2]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
+    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
+    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+    ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]]
+    ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
+    ; MIPS32: $v0 = COPY [[COPY7]](s32)
     ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %2:_(s1) = G_ICMP intpred(slt), %0(s32), %1
-    %3:_(s32) = G_ZEXT %2(s1)
-    $v0 = COPY %3(s32)
+    %2:_(s32) = COPY $a0
+    %3:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+    %4:_(s32) = COPY $a2
+    %5:_(s32) = COPY $a3
+    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
+    %6:_(s1) = G_ICMP intpred(sge), %0(s64), %1
+    %7:_(s32) = G_ANYEXT %6(s1)
+    $v0 = COPY %7(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            sle
+name:            slt_i64
 alignment:       2
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
-    liveins: $a0, $a1
+    liveins: $a0, $a1, $a2, $a3
 
-    ; MIPS32-LABEL: name: sle
-    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32-LABEL: name: slt_i64
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), [[COPY]](s32), [[COPY1]]
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
+    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
+    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+    ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]]
+    ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
+    ; MIPS32: $v0 = COPY [[COPY7]](s32)
     ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %2:_(s1) = G_ICMP intpred(sle), %0(s32), %1
-    %3:_(s32) = G_ZEXT %2(s1)
-    $v0 = COPY %3(s32)
+    %2:_(s32) = COPY $a0
+    %3:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+    %4:_(s32) = COPY $a2
+    %5:_(s32) = COPY $a3
+    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
+    %6:_(s1) = G_ICMP intpred(slt), %0(s64), %1
+    %7:_(s32) = G_ANYEXT %6(s1)
+    $v0 = COPY %7(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            ugt
+name:            sle_i64
 alignment:       2
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
-    liveins: $a0, $a1
+    liveins: $a0, $a1, $a2, $a3
 
-    ; MIPS32-LABEL: name: ugt
-    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32-LABEL: name: sle_i64
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY]](s32), [[COPY2]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
+    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
+    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+    ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]]
+    ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
+    ; MIPS32: $v0 = COPY [[COPY7]](s32)
     ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %2:_(s1) = G_ICMP intpred(ugt), %0(s32), %1
-    %3:_(s32) = G_ZEXT %2(s1)
-    $v0 = COPY %3(s32)
+    %2:_(s32) = COPY $a0
+    %3:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+    %4:_(s32) = COPY $a2
+    %5:_(s32) = COPY $a3
+    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
+    %6:_(s1) = G_ICMP intpred(sle), %0(s64), %1
+    %7:_(s32) = G_ANYEXT %6(s1)
+    $v0 = COPY %7(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            uge
+name:            ugt_i64
 alignment:       2
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
-    liveins: $a0, $a1
+    liveins: $a0, $a1, $a2, $a3
 
-    ; MIPS32-LABEL: name: uge
-    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32-LABEL: name: ugt_i64
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY1]]
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
+    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
+    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+    ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]]
+    ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
+    ; MIPS32: $v0 = COPY [[COPY7]](s32)
     ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %2:_(s1) = G_ICMP intpred(uge), %0(s32), %1
-    %3:_(s32) = G_ZEXT %2(s1)
-    $v0 = COPY %3(s32)
+    %2:_(s32) = COPY $a0
+    %3:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+    %4:_(s32) = COPY $a2
+    %5:_(s32) = COPY $a3
+    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
+    %6:_(s1) = G_ICMP intpred(ugt), %0(s64), %1
+    %7:_(s32) = G_ANYEXT %6(s1)
+    $v0 = COPY %7(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            ult
+name:            uge_i64
 alignment:       2
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
-    liveins: $a0, $a1
+    liveins: $a0, $a1, $a2, $a3
 
-    ; MIPS32-LABEL: name: ult
-    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32-LABEL: name: uge_i64
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY2]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
+    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
+    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+    ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]]
+    ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
+    ; MIPS32: $v0 = COPY [[COPY7]](s32)
     ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %2:_(s1) = G_ICMP intpred(ult), %0(s32), %1
-    %3:_(s32) = G_ZEXT %2(s1)
-    $v0 = COPY %3(s32)
+    %2:_(s32) = COPY $a0
+    %3:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+    %4:_(s32) = COPY $a2
+    %5:_(s32) = COPY $a3
+    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
+    %6:_(s1) = G_ICMP intpred(uge), %0(s64), %1
+    %7:_(s32) = G_ANYEXT %6(s1)
+    $v0 = COPY %7(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            ule
+name:            ult_i64
 alignment:       2
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
-    liveins: $a0, $a1
+    liveins: $a0, $a1, $a2, $a3
 
-    ; MIPS32-LABEL: name: ule
-    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32-LABEL: name: ult_i64
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
     ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY]](s32), [[COPY1]]
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
+    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
     ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
+    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+    ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]]
+    ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
+    ; MIPS32: $v0 = COPY [[COPY7]](s32)
     ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %2:_(s1) = G_ICMP intpred(ule), %0(s32), %1
-    %3:_(s32) = G_ZEXT %2(s1)
-    $v0 = COPY %3(s32)
+    %2:_(s32) = COPY $a0
+    %3:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+    %4:_(s32) = COPY $a2
+    %5:_(s32) = COPY $a3
+    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
+    %6:_(s1) = G_ICMP intpred(ult), %0(s64), %1
+    %7:_(s32) = G_ANYEXT %6(s1)
+    $v0 = COPY %7(s32)
     RetRA implicit $v0
 
 ...
+---
+name:            ule_i64
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1, $a2, $a3
 
+    ; MIPS32-LABEL: name: ule_i64
+    ; MIPS32: liveins: $a0, $a1, $a2, $a3
+    ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
+    ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
+    ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
+    ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
+    ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY]](s32), [[COPY2]]
+    ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
+    ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+    ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
+    ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+    ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]]
+    ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
+    ; MIPS32: $v0 = COPY [[COPY7]](s32)
+    ; MIPS32: RetRA implicit $v0
+    %2:_(s32) = COPY $a0
+    %3:_(s32) = COPY $a1
+    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+    %4:_(s32) = COPY $a2
+    %5:_(s32) = COPY $a3
+    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
+    %6:_(s1) = G_ICMP intpred(ule), %0(s64), %1
+    %7:_(s32) = G_ANYEXT %6(s1)
+    $v0 = COPY %7(s32)
+    RetRA implicit $v0
+
+...
Index: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll
===================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll
@@ -1,148 +1,343 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
 
-define i32 @eq(i32 %a, i32 %b){
-; MIPS32-LABEL: eq:
+define i1 @eq_i32(i32 %a, i32 %b){
+; MIPS32-LABEL: eq_i32:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    xor $1, $4, $5
-; MIPS32-NEXT:    sltiu $1, $1, 1
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    sltiu $2, $1, 1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp eq i32 %a, %b
-  %conv = zext i1 %cmp to i32
-  ret i32 %conv
+  ret i1 %cmp
 }
 
-define i32 @ne(i32 %a, i32 %b) {
-; MIPS32-LABEL: ne:
+define i1 @ne_i32(i32 %a, i32 %b) {
+; MIPS32-LABEL: ne_i32:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    xor $1, $4, $5
-; MIPS32-NEXT:    sltu $1, $zero, $1
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    sltu $2, $zero, $1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp ne i32 %a, %b
-  %conv = zext i1 %cmp to i32
-  ret i32 %conv
+  ret i1 %cmp
 }
 
-define i32 @sgt(i32 %a, i32 %b) {
-; MIPS32-LABEL: sgt:
+define i1 @sgt_i32(i32 %a, i32 %b) {
+; MIPS32-LABEL: sgt_i32:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    slt $1, $5, $4
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    slt $2, $5, $4
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp sgt i32 %a, %b
-  %conv = zext i1 %cmp to i32
-  ret i32 %conv
+  ret i1 %cmp
 }
 
-define i32 @sge(i32 %a, i32 %b) {
-; MIPS32-LABEL: sge:
+define i1 @sge_i32(i32 %a, i32 %b) {
+; MIPS32-LABEL: sge_i32:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    slt $1, $4, $5
-; MIPS32-NEXT:    xori $1, $1, 1
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    xori $2, $1, 1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp sge i32 %a, %b
-  %conv = zext i1 %cmp to i32
-  ret i32 %conv
+  ret i1 %cmp
 }
 
-define i32 @slt(i32 %a, i32 %b) {
-; MIPS32-LABEL: slt:
+define i1 @slt_i32(i32 %a, i32 %b) {
+; MIPS32-LABEL: slt_i32:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    slt $1, $4, $5
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    slt $2, $4, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp slt i32 %a, %b
-  %conv = zext i1 %cmp to i32
-  ret i32 %conv
+  ret i1 %cmp
 }
 
-define i32 @sle(i32 %a, i32 %b) {
-; MIPS32-LABEL: sle:
+define i1 @sle_i32(i32 %a, i32 %b) {
+; MIPS32-LABEL: sle_i32:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    slt $1, $5, $4
-; MIPS32-NEXT:    xori $1, $1, 1
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    xori $2, $1, 1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp sle i32 %a, %b
-  %conv = zext i1 %cmp to i32
-  ret i32 %conv
+  ret i1 %cmp
 }
 
-define i32 @ugt(i32 %a, i32 %b) {
-; MIPS32-LABEL: ugt:
+define i1 @ugt_i32(i32 %a, i32 %b) {
+; MIPS32-LABEL: ugt_i32:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    sltu $1, $5, $4
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    sltu $2, $5, $4
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp ugt i32 %a, %b
-  %conv = zext i1 %cmp to i32
-  ret i32 %conv
+  ret i1 %cmp
 }
 
-define i32 @uge(i32 %a, i32 %b) {
-; MIPS32-LABEL: uge:
+define i1 @uge_i32(i32 %a, i32 %b) {
+; MIPS32-LABEL: uge_i32:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    sltu $1, $4, $5
-; MIPS32-NEXT:    xori $1, $1, 1
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    xori $2, $1, 1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp uge i32 %a, %b
-  %conv = zext i1 %cmp to i32
-  ret i32 %conv
+  ret i1 %cmp
 }
 
-define i32 @ult(i32 %a, i32 %b) {
-; MIPS32-LABEL: ult:
+define i1 @ult_i32(i32 %a, i32 %b) {
+; MIPS32-LABEL: ult_i32:
 ; MIPS32:       # %bb.0: # %entry
-; MIPS32-NEXT:    sltu $1, $4, $5
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    sltu $2, $4, $5
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp ult i32 %a, %b
-  %conv = zext i1 %cmp to i32
-  ret i32 %conv
+  ret i1 %cmp
 }
 
-define i32 @ule(i32 %a, i32 %b) {
-; MIPS32-LABEL: ule:
+define i1 @ule_i32(i32 %a, i32 %b) {
+; MIPS32-LABEL: ule_i32:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    sltu $1, $5, $4
-; MIPS32-NEXT:    xori $1, $1, 1
-; MIPS32-NEXT:    ori $2, $zero, 1
-; MIPS32-NEXT:    and $2, $1, $2
+; MIPS32-NEXT:    xori $2, $1, 1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp ule i32 %a, %b
-  %conv = zext i1 %cmp to i32
-  ret i32 %conv
+  ret i1 %cmp
+}
+
+define i1 @eq_ptr(i32* %a, i32* %b){
+; MIPS32-LABEL: eq_ptr:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    xor $1, $4, $5
+; MIPS32-NEXT:    sltiu $2, $1, 1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp eq i32* %a, %b
+  ret i1 %cmp
+}
+
+define i1 @ult_i8(i8 %a, i8 %b) {
+; MIPS32-LABEL: ult_i8:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    ori $1, $zero, 255
+; MIPS32-NEXT:    and $2, $4, $1
+; MIPS32-NEXT:    and $1, $5, $1
+; MIPS32-NEXT:    sltu $2, $2, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp ult i8 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @slt_i16(i16 %a, i16 %b) {
+; MIPS32-LABEL: slt_i16:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sll $1, $4, 16
+; MIPS32-NEXT:    sra $1, $1, 16
+; MIPS32-NEXT:    sll $2, $5, 16
+; MIPS32-NEXT:    sra $2, $2, 16
+; MIPS32-NEXT:    slt $2, $1, $2
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp slt i16 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @eq_i64(i64 %a, i64 %b){
+; MIPS32-LABEL: eq_i64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    xor $1, $4, $6
+; MIPS32-NEXT:    xor $2, $5, $7
+; MIPS32-NEXT:    or $1, $1, $2
+; MIPS32-NEXT:    ori $2, $zero, 0
+; MIPS32-NEXT:    xor $1, $1, $2
+; MIPS32-NEXT:    sltiu $2, $1, 1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp eq i64 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @ne_i64(i64 %a, i64 %b) {
+; MIPS32-LABEL: ne_i64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    xor $1, $4, $6
+; MIPS32-NEXT:    xor $2, $5, $7
+; MIPS32-NEXT:    or $1, $1, $2
+; MIPS32-NEXT:    ori $2, $zero, 0
+; MIPS32-NEXT:    xor $1, $1, $2
+; MIPS32-NEXT:    sltu $2, $zero, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp ne i64 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @sgt_i64(i64 %a, i64 %b) {
+; MIPS32-LABEL: sgt_i64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    slt $1, $7, $5
+; MIPS32-NEXT:    xor $2, $5, $7
+; MIPS32-NEXT:    sltiu $2, $2, 1
+; MIPS32-NEXT:    sltu $3, $6, $4
+; MIPS32-NEXT:    ori $4, $zero, 1
+; MIPS32-NEXT:    and $2, $2, $4
+; MIPS32-NEXT:    movn $1, $3, $2
+; MIPS32-NEXT:    move $2, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp sgt i64 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @sge_i64(i64 %a, i64 %b) {
+; MIPS32-LABEL: sge_i64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    slt $1, $5, $7
+; MIPS32-NEXT:    xori $1, $1, 1
+; MIPS32-NEXT:    xor $2, $5, $7
+; MIPS32-NEXT:    sltiu $2, $2, 1
+; MIPS32-NEXT:    sltu $3, $4, $6
+; MIPS32-NEXT:    xori $3, $3, 1
+; MIPS32-NEXT:    ori $4, $zero, 1
+; MIPS32-NEXT:    and $2, $2, $4
+; MIPS32-NEXT:    movn $1, $3, $2
+; MIPS32-NEXT:    move $2, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp sge i64 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @slt_i64(i64 %a, i64 %b) {
+; MIPS32-LABEL: slt_i64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    slt $1, $5, $7
+; MIPS32-NEXT:    xor $2, $5, $7
+; MIPS32-NEXT:    sltiu $2, $2, 1
+; MIPS32-NEXT:    sltu $3, $4, $6
+; MIPS32-NEXT:    ori $4, $zero, 1
+; MIPS32-NEXT:    and $2, $2, $4
+; MIPS32-NEXT:    movn $1, $3, $2
+; MIPS32-NEXT:    move $2, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp slt i64 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @sle_i64(i64 %a, i64 %b) {
+; MIPS32-LABEL: sle_i64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    slt $1, $7, $5
+; MIPS32-NEXT:    xori $1, $1, 1
+; MIPS32-NEXT:    xor $2, $5, $7
+; MIPS32-NEXT:    sltiu $2, $2, 1
+; MIPS32-NEXT:    sltu $3, $6, $4
+; MIPS32-NEXT:    xori $3, $3, 1
+; MIPS32-NEXT:    ori $4, $zero, 1
+; MIPS32-NEXT:    and $2, $2, $4
+; MIPS32-NEXT:    movn $1, $3, $2
+; MIPS32-NEXT:    move $2, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp sle i64 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @ugt_i64(i64 %a, i64 %b) {
+; MIPS32-LABEL: ugt_i64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sltu $1, $7, $5
+; MIPS32-NEXT:    xor $2, $5, $7
+; MIPS32-NEXT:    sltiu $2, $2, 1
+; MIPS32-NEXT:    sltu $3, $6, $4
+; MIPS32-NEXT:    ori $4, $zero, 1
+; MIPS32-NEXT:    and $2, $2, $4
+; MIPS32-NEXT:    movn $1, $3, $2
+; MIPS32-NEXT:    move $2, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp ugt i64 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @uge_i64(i64 %a, i64 %b) {
+; MIPS32-LABEL: uge_i64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sltu $1, $5, $7
+; MIPS32-NEXT:    xori $1, $1, 1
+; MIPS32-NEXT:    xor $2, $5, $7
+; MIPS32-NEXT:    sltiu $2, $2, 1
+; MIPS32-NEXT:    sltu $3, $4, $6
+; MIPS32-NEXT:    xori $3, $3, 1
+; MIPS32-NEXT:    ori $4, $zero, 1
+; MIPS32-NEXT:    and $2, $2, $4
+; MIPS32-NEXT:    movn $1, $3, $2
+; MIPS32-NEXT:    move $2, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp uge i64 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @ult_i64(i64 %a, i64 %b) {
+; MIPS32-LABEL: ult_i64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sltu $1, $5, $7
+; MIPS32-NEXT:    xor $2, $5, $7
+; MIPS32-NEXT:    sltiu $2, $2, 1
+; MIPS32-NEXT:    sltu $3, $4, $6
+; MIPS32-NEXT:    ori $4, $zero, 1
+; MIPS32-NEXT:    and $2, $2, $4
+; MIPS32-NEXT:    movn $1, $3, $2
+; MIPS32-NEXT:    move $2, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp ult i64 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @ule_i64(i64 %a, i64 %b) {
+; MIPS32-LABEL: ule_i64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sltu $1, $7, $5
+; MIPS32-NEXT:    xori $1, $1, 1
+; MIPS32-NEXT:    xor $2, $5, $7
+; MIPS32-NEXT:    sltiu $2, $2, 1
+; MIPS32-NEXT:    sltu $3, $6, $4
+; MIPS32-NEXT:    xori $3, $3, 1
+; MIPS32-NEXT:    ori $4, $zero, 1
+; MIPS32-NEXT:    and $2, $2, $4
+; MIPS32-NEXT:    movn $1, $3, $2
+; MIPS32-NEXT:    move $2, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp ule i64 %a, %b
+  ret i1 %cmp
 }
Index: llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir
===================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/icmp.mir
@@ -2,20 +2,12 @@
 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
 --- |
 
-  define void @eq() {entry: ret void}
-  define void @ne() {entry: ret void}
-  define void @sgt() {entry: ret void}
-  define void @sge() {entry: ret void}
-  define void @slt() {entry: ret void}
-  define void @sle() {entry: ret void}
-  define void @ugt() {entry: ret void}
-  define void @uge() {entry: ret void}
-  define void @ult() {entry: ret void}
-  define void @ule() {entry: ret void}
+  define void @ne_i32() {entry: ret void}
+  define void @eq_ptr() {entry: ret void}
 
 ...
 ---
-name:            eq
+name:            ne_i32
 alignment:       2
 legalized:       true
 tracksRegLiveness: true
@@ -23,231 +15,24 @@
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: eq
-    ; MIPS32: liveins: $a0, $a1
-    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
-    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
-    ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %4:_(s32) = G_ICMP intpred(eq), %0(s32), %1
-    %5:_(s32) = G_CONSTANT i32 1
-    %6:_(s32) = COPY %4(s32)
-    %3:_(s32) = G_AND %6, %5
-    $v0 = COPY %3(s32)
-    RetRA implicit $v0
-
-...
----
-name:            ne
-alignment:       2
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.1.entry:
-    liveins: $a0, $a1
-
-    ; MIPS32-LABEL: name: ne
+    ; MIPS32-LABEL: name: ne_i32
     ; MIPS32: liveins: $a0, $a1
     ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
     ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
     ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
     ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: $v0 = COPY [[COPY2]](s32)
     ; MIPS32: RetRA implicit $v0
     %0:_(s32) = COPY $a0
     %1:_(s32) = COPY $a1
     %4:_(s32) = G_ICMP intpred(ne), %0(s32), %1
-    %5:_(s32) = G_CONSTANT i32 1
-    %6:_(s32) = COPY %4(s32)
-    %3:_(s32) = G_AND %6, %5
-    $v0 = COPY %3(s32)
-    RetRA implicit $v0
-
-...
----
-name:            sgt
-alignment:       2
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.1.entry:
-    liveins: $a0, $a1
-
-    ; MIPS32-LABEL: name: sgt
-    ; MIPS32: liveins: $a0, $a1
-    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
-    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
-    ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %4:_(s32) = G_ICMP intpred(sgt), %0(s32), %1
-    %5:_(s32) = G_CONSTANT i32 1
-    %6:_(s32) = COPY %4(s32)
-    %3:_(s32) = G_AND %6, %5
-    $v0 = COPY %3(s32)
-    RetRA implicit $v0
-
-...
----
-name:            sge
-alignment:       2
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.1.entry:
-    liveins: $a0, $a1
-
-    ; MIPS32-LABEL: name: sge
-    ; MIPS32: liveins: $a0, $a1
-    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
-    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(sge), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
-    ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %4:_(s32) = G_ICMP intpred(sge), %0(s32), %1
-    %5:_(s32) = G_CONSTANT i32 1
-    %6:_(s32) = COPY %4(s32)
-    %3:_(s32) = G_AND %6, %5
-    $v0 = COPY %3(s32)
-    RetRA implicit $v0
-
-...
----
-name:            slt
-alignment:       2
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.1.entry:
-    liveins: $a0, $a1
-
-    ; MIPS32-LABEL: name: slt
-    ; MIPS32: liveins: $a0, $a1
-    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
-    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
-    ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %4:_(s32) = G_ICMP intpred(slt), %0(s32), %1
-    %5:_(s32) = G_CONSTANT i32 1
-    %6:_(s32) = COPY %4(s32)
-    %3:_(s32) = G_AND %6, %5
-    $v0 = COPY %3(s32)
-    RetRA implicit $v0
-
-...
----
-name:            sle
-alignment:       2
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.1.entry:
-    liveins: $a0, $a1
-
-    ; MIPS32-LABEL: name: sle
-    ; MIPS32: liveins: $a0, $a1
-    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
-    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(sle), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
-    ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %4:_(s32) = G_ICMP intpred(sle), %0(s32), %1
-    %5:_(s32) = G_CONSTANT i32 1
-    %6:_(s32) = COPY %4(s32)
-    %3:_(s32) = G_AND %6, %5
-    $v0 = COPY %3(s32)
-    RetRA implicit $v0
-
-...
----
-name:            ugt
-alignment:       2
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.1.entry:
-    liveins: $a0, $a1
-
-    ; MIPS32-LABEL: name: ugt
-    ; MIPS32: liveins: $a0, $a1
-    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
-    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
-    ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %4:_(s32) = G_ICMP intpred(ugt), %0(s32), %1
-    %5:_(s32) = G_CONSTANT i32 1
-    %6:_(s32) = COPY %4(s32)
-    %3:_(s32) = G_AND %6, %5
-    $v0 = COPY %3(s32)
-    RetRA implicit $v0
-
-...
----
-name:            uge
-alignment:       2
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.1.entry:
-    liveins: $a0, $a1
-
-    ; MIPS32-LABEL: name: uge
-    ; MIPS32: liveins: $a0, $a1
-    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
-    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
-    ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %4:_(s32) = G_ICMP intpred(uge), %0(s32), %1
-    %5:_(s32) = G_CONSTANT i32 1
-    %6:_(s32) = COPY %4(s32)
-    %3:_(s32) = G_AND %6, %5
+    %3:_(s32) = COPY %4(s32)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...
 ---
-name:            ult
+name:            eq_ptr
 alignment:       2
 legalized:       true
 tracksRegLiveness: true
@@ -255,51 +40,18 @@
   bb.1.entry:
     liveins: $a0, $a1
 
-    ; MIPS32-LABEL: name: ult
+    ; MIPS32-LABEL: name: eq_ptr
     ; MIPS32: liveins: $a0, $a1
-    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
-    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+    ; MIPS32: [[COPY:%[0-9]+]]:gprb(p0) = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1
+    ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(eq), [[COPY]](p0), [[COPY1]]
     ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
+    ; MIPS32: $v0 = COPY [[COPY2]](s32)
     ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %4:_(s32) = G_ICMP intpred(ult), %0(s32), %1
-    %5:_(s32) = G_CONSTANT i32 1
-    %6:_(s32) = COPY %4(s32)
-    %3:_(s32) = G_AND %6, %5
-    $v0 = COPY %3(s32)
-    RetRA implicit $v0
-
-...
----
-name:            ule
-alignment:       2
-legalized:       true
-tracksRegLiveness: true
-body:             |
-  bb.1.entry:
-    liveins: $a0, $a1
-
-    ; MIPS32-LABEL: name: ule
-    ; MIPS32: liveins: $a0, $a1
-    ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
-    ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
-    ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ule), [[COPY]](s32), [[COPY1]]
-    ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
-    ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
-    ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY2]], [[C]]
-    ; MIPS32: $v0 = COPY [[AND]](s32)
-    ; MIPS32: RetRA implicit $v0
-    %0:_(s32) = COPY $a0
-    %1:_(s32) = COPY $a1
-    %4:_(s32) = G_ICMP intpred(ule), %0(s32), %1
-    %5:_(s32) = G_CONSTANT i32 1
-    %6:_(s32) = COPY %4(s32)
-    %3:_(s32) = G_AND %6, %5
+    %0:_(p0) = COPY $a0
+    %1:_(p0) = COPY $a1
+    %4:_(s32) = G_ICMP intpred(eq), %0(p0), %1
+    %3:_(s32) = COPY %4(s32)
     $v0 = COPY %3(s32)
     RetRA implicit $v0