diff --git a/llvm/lib/Target/PowerPC/P9InstrResources.td b/llvm/lib/Target/PowerPC/P9InstrResources.td
--- a/llvm/lib/Target/PowerPC/P9InstrResources.td
+++ b/llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -148,7 +148,7 @@
     (instregex "EXTS(B|H|W)(8)?(_32)?(_64)?(o)?$"),
     (instregex "ADD(4|8)(TLS)?(_)?$"),
     (instregex "NEG(8)?$"),
-    (instregex "ADDI(S)?toc(HA|L)$"),
+    (instregex "ADDI(S)?toc(HA(8)?|L)$"),
     COPY,
     MCRF,
     MCRXRX,
diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
--- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -720,8 +720,8 @@
     return;
   }
 
-  case PPC::ADDIStocHA: {
-    // Transform %xd = ADDIStocHA %x2, @sym
+  case PPC::ADDIStocHA8: {
+    // Transform %xd = ADDIStocHA8 %x2, @sym
     LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
 
     // Change the opcode to ADDIS8.  If the global address is external, has
@@ -732,7 +732,7 @@
     const MachineOperand &MO = MI->getOperand(2);
     assert((MO.isGlobal() || MO.isCPI() || MO.isJTI() ||
             MO.isBlockAddress()) &&
-           "Invalid operand for ADDIStocHA!");
+           "Invalid operand for ADDIStocHA8!");
     MCSymbol *MOSymbol = nullptr;
     bool GlobalToc = false;
 
@@ -799,7 +799,7 @@
           unsigned char GVFlags = Subtarget->classifyGlobalReference(GV);
           assert((GVFlags & PPCII::MO_NLP_FLAG) &&
                  "LDtocL used on symbol that could be accessed directly is "
-                 "invalid. Must match ADDIStocHA."));
+                 "invalid. Must match ADDIStocHA8."));
       MOSymbol = lookUpOrCreateTOCEntry(MOSymbol);
     }
 
diff --git a/llvm/lib/Target/PowerPC/PPCFastISel.cpp b/llvm/lib/Target/PowerPC/PPCFastISel.cpp
--- a/llvm/lib/Target/PowerPC/PPCFastISel.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFastISel.cpp
@@ -2031,8 +2031,8 @@
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
       .addImm(0).addReg(TmpReg).addMemOperand(MMO);
   } else {
-    // Otherwise we generate LF[SD](Idx[lo], ADDIStocHA(X2, Idx)).
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA),
+    // Otherwise we generate LF[SD](Idx[lo], ADDIStocHA8(X2, Idx)).
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA8),
             TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx);
     // But for large code model, we must generate a LDtocL followed
     // by the LF[SD].
@@ -2085,12 +2085,12 @@
     // or externally available linkage, a non-local function address, or a
     // jump table address (not yet needed), or if we are generating code
     // for large code model, we generate:
-    //       LDtocL(GV, ADDIStocHA(%x2, GV))
+    //       LDtocL(GV, ADDIStocHA8(%x2, GV))
     // Otherwise we generate:
-    //       ADDItocL(ADDIStocHA(%x2, GV), GV)
-    // Either way, start with the ADDIStocHA:
+    //       ADDItocL(ADDIStocHA8(%x2, GV), GV)
+    // Either way, start with the ADDIStocHA8:
     unsigned HighPartReg = createResultReg(RC);
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA),
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA8),
             HighPartReg).addReg(PPC::X2).addGlobalAddress(GV);
 
     unsigned char GVFlags = PPCSubTarget->classifyGlobalReference(GV);
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -5085,12 +5085,12 @@
 
     // The first source operand is a TargetGlobalAddress or a TargetJumpTable.
     // If it must be toc-referenced according to PPCSubTarget, we generate:
-    //   LDtocL(@sym, ADDIStocHA(%x2, @sym))
+    //   LDtocL(@sym, ADDIStocHA8(%x2, @sym))
     // Otherwise we generate:
-    //   ADDItocL(ADDIStocHA(%x2, @sym), @sym)
+    //   ADDItocL(ADDIStocHA8(%x2, @sym), @sym)
     SDValue GA = N->getOperand(0);
     SDValue TOCbase = N->getOperand(1);
-    SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64,
+    SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA8, dl, MVT::i64,
                                          TOCbase, GA);
     if (PPCLowering->isAccessedAsGotIndirect(GA)) {
       // If it is access as got-indirect, we need an extra LD to load
@@ -6456,7 +6456,7 @@
           continue;
 
         if (!HBase.isMachineOpcode() ||
-            HBase.getMachineOpcode() != PPC::ADDIStocHA)
+            HBase.getMachineOpcode() != PPC::ADDIStocHA8)
           continue;
 
         if (!Base.hasOneUse() || !HBase.hasOneUse())
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -14313,7 +14313,7 @@
   CodeModel::Model CModel = getTargetMachine().getCodeModel();
   // If it is small or large code model, module locals are accessed
   // indirectly by loading their address from .toc/.got. The difference
-  // is that for large code model we have ADDISTocHa + LDtocL and for
+  // is that for large code model we have ADDIStocHA8 + LDtocL and for
   // small code model we simply have LDtoc.
   if (CModel == CodeModel::Small || CModel == CodeModel::Large)
     return true;
diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1099,8 +1099,8 @@
 // Support for medium and large code model.
 let hasSideEffects = 0 in {
 let isReMaterializable = 1 in {
-def ADDIStocHA: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
-                       "#ADDIStocHA", []>, isPPC64;
+def ADDIStocHA8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
+                       "#ADDIStocHA8", []>, isPPC64;
 def ADDItocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
                      "#ADDItocL", []>, isPPC64;
 }
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -329,7 +329,7 @@
   case PPC::LIS:
   case PPC::LIS8:
   case PPC::QVGPCI:
-  case PPC::ADDIStocHA:
+  case PPC::ADDIStocHA8:
   case PPC::ADDItocL:
   case PPC::LOAD_STACK_GUARD:
   case PPC::XXLXORz:
diff --git a/llvm/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.mir b/llvm/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.mir
--- a/llvm/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.mir
+++ b/llvm/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.mir
@@ -26,7 +26,7 @@
   bb.0:
     liveins: $x2
 
-    %0:g8rc_and_g8rc_nox0 = ADDIStocHA $x2, @g_51
+    %0:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @g_51
     %1:g8rc_and_g8rc_nox0 = LDtocL @g_51, killed %0, implicit $x2 :: (load 8)
     %2:gprc = LI 0
     %3:crrc = CMPLWI killed %2, 0
@@ -62,7 +62,7 @@
 # the full MIR like this.
 #
 # CHECK:       bb.0:
-# CHECK:         %0:g8rc_and_g8rc_nox0 = ADDIStocHA $x2, @g_51
+# CHECK:         %0:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @g_51
 # CHECK-NEXT:    %1:g8rc_and_g8rc_nox0 = LDtocL @g_51, killed %0, implicit killed $x2 :: (load 8)
 # CHECK-NEXT:    %2:gprc = LI 0
 # CHECK-NEXT:    %3:crrc = CMPLWI killed %2, 0
diff --git a/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir b/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir
--- a/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir
+++ b/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir
@@ -77,7 +77,7 @@
     $x30 = OR8 $x4, $x4
     $x3 = LD 0, killed $x3 :: (load 8 from %ir.p1)
     $x29 = ADDI8 killed $x3, -48
-    $x3 = ADDIStocHA $x2, @tasklist_lock
+    $x3 = ADDIStocHA8 $x2, @tasklist_lock
     $x3 = LDtocL @tasklist_lock, killed $x3, implicit $x2 :: (load 8 from got)
     BL8_NOP @__raw_read_unlock, csr_svr464_altivec, implicit-def $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3
     $r3 = LI 0
diff --git a/llvm/test/CodeGen/PowerPC/licm-tocReg.ll b/llvm/test/CodeGen/PowerPC/licm-tocReg.ll
--- a/llvm/test/CodeGen/PowerPC/licm-tocReg.ll
+++ b/llvm/test/CodeGen/PowerPC/licm-tocReg.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
 
-; The instructions ADDIStocHA/LDtocL are used to calculate the address of
+; The instructions ADDIStocHA8/LDtocL are used to calculate the address of
 ; globals. The ones that are in bb.3.if.end could not be hoisted by Machine
 ; LICM due to BCTRL_LDinto_toc in bb2.if.then.  This call causes the compiler
 ; to insert a save TOC to stack before the call and load into X2 to restore TOC
@@ -16,10 +16,10 @@
 ;    liveins: %x3
 ;
 ;    %4 = COPY %x3
-;    %5 = ADDIStocHA %x2, @ga
+;    %5 = ADDIStocHA8 %x2, @ga
 ;    %6 = LDtocL @ga, killed %5 :: (load 8 from got)
 ;    %7 = LWZ 0, %6 :: (volatile dereferenceable load 4 from @ga)
-;    %8 = ADDIStocHA %x2, @gb
+;    %8 = ADDIStocHA8 %x2, @gb
 ;    %9 = LDtocL @gb, killed %8 :: (load 8 from got)
 ;    %10 = LWZ 0, killed %9 :: (volatile dereferenceable load 4 from @gb)
 ;    %0 = LWZ 0, %6 :: (volatile dereferenceable load 4 from @ga)
@@ -47,11 +47,11 @@
 ;
 ;    %2 = PHI %0, %bb.0.entry, %3, %bb.3.if.end
 ;    %12 = ADDI %2, 1
-;    %13 = ADDIStocHA %x2, @ga
+;    %13 = ADDIStocHA8 %x2, @ga
 ;    %14 = LDtocL @ga, killed %13 :: (load 8 from got)
 ;    STW killed %12, 0, %14 :: (volatile store 4 into @ga)
 ;    %15 = LWZ 0, %14 :: (volatile dereferenceable load 4 from @ga)
-;    %16 = ADDIStocHA %x2, @gb
+;    %16 = ADDIStocHA8 %x2, @gb
 ;    %17 = LDtocL @gb, killed %16 :: (load 8 from got)
 ;    %18 = LWZ 0, killed %17 :: (volatile dereferenceable load 4 from @gb)
 ;    %3 = LWZ 0, %14 :: (volatile dereferenceable load 4 from @ga)
diff --git a/llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir b/llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
--- a/llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
+++ b/llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
@@ -70,7 +70,7 @@
   bb.0.entry:
     liveins: $x2
 
-    %0 = ADDIStocHA $x2, @b
+    %0 = ADDIStocHA8 $x2, @b
     %1 = LD target-flags(ppc-toc-lo) @b, killed %0 :: (load 8 from @b)
     %2 = LWZ 0, %1 :: (load 4 from %ir.0)
     %3 = LI 0
diff --git a/llvm/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir b/llvm/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir
--- a/llvm/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir
+++ b/llvm/test/CodeGen/PowerPC/remove-copy-crunsetcrbit.mir
@@ -110,7 +110,7 @@
     successors: %bb.5(0x30000000), %bb.1(0x50000000)
     liveins: $x2
 
-    %3:g8rc_and_g8rc_nox0 = ADDIStocHA $x2, @b
+    %3:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @b
     %4:gprc = LWZ target-flags(ppc-toc-lo) @b, killed %3, implicit $x2 :: (dereferenceable load 4 from @b)
     %5:crrc = CMPLWI killed %4, 0
     BCC 76, killed %5, %bb.5
@@ -120,16 +120,16 @@
     successors: %bb.2(0x80000000)
     liveins: $x2
 
-    %6:g8rc_and_g8rc_nox0 = ADDIStocHA $x2, @d
+    %6:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @d
     %7:gprc = LWZ target-flags(ppc-toc-lo) @d, killed %6, implicit $x2 :: (dereferenceable load 4 from @d)
     %8:crrc = CMPWI killed %7, 0
     %0:crbitrc = COPY killed %8.sub_eq
     %9:crbitrc = CRUNSET
     %19:gprc_and_gprc_nor0 = LI 0
     %20:gprc_and_gprc_nor0 = LI 1
-    %22:g8rc_and_g8rc_nox0 = ADDIStocHA $x2, @c
-    %10:g8rc_and_g8rc_nox0 = ADDIStocHA $x2, @e
-    %13:g8rc_and_g8rc_nox0 = ADDIStocHA $x2, @a
+    %22:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @c
+    %10:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @e
+    %13:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @a
     %14:g8rc_and_g8rc_nox0 = ADDItocL killed %13, @a, implicit $x2
 
   bb.2.while.body: