Index: include/llvm/Support/TargetRegistry.h =================================================================== --- include/llvm/Support/TargetRegistry.h +++ include/llvm/Support/TargetRegistry.h @@ -108,7 +108,8 @@ typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T, const MCRegisterInfo &MRI, StringRef TT, - StringRef CPU); + StringRef CPU, + const MCTargetOptions &Options); typedef MCTargetAsmParser *(*MCAsmParserCtorTy)( MCSubtargetInfo &STI, MCAsmParser &P, @@ -356,10 +357,11 @@ /// /// \param Triple The target triple string. MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI, - StringRef Triple, StringRef CPU) const { + StringRef Triple, StringRef CPU, + const MCTargetOptions &Options) const { if (!MCAsmBackendCtorFn) return nullptr; - return MCAsmBackendCtorFn(*this, MRI, Triple, CPU); + return MCAsmBackendCtorFn(*this, MRI, Triple, CPU, Options); } /// createMCAsmParser - Create a target specific assembly parser. Index: lib/CodeGen/LLVMTargetMachine.cpp =================================================================== --- lib/CodeGen/LLVMTargetMachine.cpp +++ lib/CodeGen/LLVMTargetMachine.cpp @@ -192,7 +192,8 @@ MCE = getTarget().createMCCodeEmitter(MII, MRI, STI, *Context); MCAsmBackend *MAB = getTarget().createMCAsmBackend(MRI, getTargetTriple(), - TargetCPU); + TargetCPU, + Options.MCOptions); MCStreamer *S = getTarget().createAsmStreamer( *Context, Out, Options.MCOptions.AsmVerbose, Options.MCOptions.MCUseDwarfDirectory, InstPrinter, MCE, MAB, @@ -206,7 +207,8 @@ MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, STI, *Context); MCAsmBackend *MAB = getTarget().createMCAsmBackend(MRI, getTargetTriple(), - TargetCPU); + TargetCPU, + Options.MCOptions); if (!MCE || !MAB) return true; @@ -258,7 +260,8 @@ MCCodeEmitter *MCE = getTarget().createMCCodeEmitter( *getSubtargetImpl()->getInstrInfo(), MRI, STI, *Ctx); MCAsmBackend *MAB = getTarget().createMCAsmBackend(MRI, getTargetTriple(), - TargetCPU); + TargetCPU, + Options.MCOptions); if (!MCE || !MAB) return true; Index: lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp =================================================================== --- lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp +++ lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp @@ -509,7 +509,8 @@ MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T, const MCRegisterInfo &MRI, - StringRef TT, StringRef CPU) { + StringRef TT, StringRef CPU, + const MCTargetOptions&) { Triple TheTriple(TT); if (TheTriple.isOSDarwin()) @@ -522,7 +523,8 @@ MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T, const MCRegisterInfo &MRI, - StringRef TT, StringRef CPU) { + StringRef TT, StringRef CPU, + const MCTargetOptions&) { Triple TheTriple(TT); assert(TheTriple.isOSBinFormatELF() && Index: lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h =================================================================== --- lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h +++ lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h @@ -28,6 +28,7 @@ class MCObjectWriter; class MCStreamer; class MCSubtargetInfo; +class MCTargetOptions; class StringRef; class Target; class raw_ostream; @@ -42,10 +43,12 @@ MCContext &Ctx); MCAsmBackend *createAArch64leAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, - StringRef CPU); + StringRef CPU, + const MCTargetOptions &Options); MCAsmBackend *createAArch64beAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, - StringRef CPU); + StringRef CPUi, + const MCTargetOptions &Options); MCObjectWriter *createAArch64ELFObjectWriter(raw_ostream &OS, uint8_t OSABI, bool IsLittleEndian); Index: lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp =================================================================== --- lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp +++ lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp @@ -777,24 +777,28 @@ MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, - StringRef TT, StringRef CPU) { + StringRef TT, StringRef CPU, + const MCTargetOptions&) { return createARMAsmBackend(T, MRI, TT, CPU, true); } MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, - StringRef TT, StringRef CPU) { + StringRef TT, StringRef CPU, + const MCTargetOptions&) { return createARMAsmBackend(T, MRI, TT, CPU, false); } MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, - StringRef TT, StringRef CPU) { + StringRef TT, StringRef CPU, + const MCTargetOptions&) { return createARMAsmBackend(T, MRI, TT, CPU, true); } MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, - StringRef TT, StringRef CPU) { + StringRef TT, StringRef CPU, + const MCTargetOptions&) { return createARMAsmBackend(T, MRI, TT, CPU, false); } Index: lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h =================================================================== --- lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h +++ lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h @@ -29,6 +29,7 @@ class MCSubtargetInfo; class MCStreamer; class MCRelocationInfo; +class MCTargetOptions; class MCTargetStreamer; class StringRef; class Target; @@ -69,16 +70,20 @@ bool IsLittleEndian); MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, - StringRef TT, StringRef CPU); + StringRef TT, StringRef CPU, + const MCTargetOptions &Options); MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, - StringRef TT, StringRef CPU); + StringRef TT, StringRef CPU, + const MCTargetOptions &Options); MCAsmBackend *createThumbLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, - StringRef TT, StringRef CPU); + StringRef TT, StringRef CPU, + const MCTargetOptions &Options); MCAsmBackend *createThumbBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, - StringRef TT, StringRef CPU); + StringRef TT, StringRef CPU, + const MCTargetOptions &Options); /// createARMWinCOFFStreamer - Construct a PE/COFF machine code streamer which /// will generate a PE/COFF object file. Index: lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp =================================================================== --- lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp +++ lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp @@ -78,6 +78,6 @@ MCAsmBackend *llvm::createBPFAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, - StringRef CPU) { + StringRef CPU, const MCTargetOptions&) { return new BPFAsmBackend(); } Index: lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h =================================================================== --- lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h +++ lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h @@ -25,6 +25,7 @@ class MCObjectWriter; class MCRegisterInfo; class MCSubtargetInfo; +class MCTargetOptions; class Target; class StringRef; class raw_ostream; @@ -37,7 +38,8 @@ MCContext &Ctx); MCAsmBackend *createBPFAsmBackend(const Target &T, const MCRegisterInfo &MRI, - StringRef TT, StringRef CPU); + StringRef TT, StringRef CPU, + const MCTargetOptions &Options); MCObjectWriter *createBPFELFObjectWriter(raw_ostream &OS, uint8_t OSABI); } Index: lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp =================================================================== --- lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp +++ lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp @@ -67,7 +67,8 @@ namespace llvm { MCAsmBackend *createHexagonAsmBackend(Target const &T, MCRegisterInfo const & /*MRI*/, - StringRef TT, StringRef /*CPU*/) { + StringRef TT, StringRef /*CPU*/, + const MCTargetOptions&) { uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS()); return new ELFHexagonAsmBackend(T, OSABI); } Index: lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h =================================================================== --- lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h +++ lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h @@ -24,6 +24,7 @@ class MCObjectWriter; class MCRegisterInfo; class MCSubtargetInfo; +class MCTargetOptions; class Target; class StringRef; class raw_ostream; @@ -39,7 +40,8 @@ MCAsmBackend *createHexagonAsmBackend(Target const &T, MCRegisterInfo const &MRI, StringRef TT, - StringRef CPU); + StringRef CPU, + const MCTargetOptions &Options); MCObjectWriter *createHexagonELFObjectWriter(raw_ostream &OS, uint8_t OSABI, StringRef CPU); Index: lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp +++ lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp @@ -422,7 +422,8 @@ MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, const MCRegisterInfo &MRI, StringRef TT, - StringRef CPU) { + StringRef CPU, + const MCTargetOptions &Options) { return new MipsAsmBackend(T, Triple(TT).getOS(), /*IsLittle*/true, /*Is64Bit*/false); } @@ -430,7 +431,8 @@ MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, const MCRegisterInfo &MRI, StringRef TT, - StringRef CPU) { + StringRef CPU, + const MCTargetOptions &Options) { return new MipsAsmBackend(T, Triple(TT).getOS(), /*IsLittle*/false, /*Is64Bit*/false); } @@ -438,7 +440,8 @@ MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, const MCRegisterInfo &MRI, StringRef TT, - StringRef CPU) { + StringRef CPU, + const MCTargetOptions &Options) { return new MipsAsmBackend(T, Triple(TT).getOS(), /*IsLittle*/true, /*Is64Bit*/true); } @@ -446,7 +449,8 @@ MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, const MCRegisterInfo &MRI, StringRef TT, - StringRef CPU) { + StringRef CPU, + const MCTargetOptions &Options) { return new MipsAsmBackend(T, Triple(TT).getOS(), /*IsLittle*/false, /*Is64Bit*/true); } Index: lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h +++ lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h @@ -27,6 +27,7 @@ class StringRef; class Target; class raw_ostream; +class MCTargetOptions; extern Target TheMipsTarget; extern Target TheMipselTarget; @@ -44,16 +45,20 @@ MCAsmBackend *createMipsAsmBackendEB32(const Target &T, const MCRegisterInfo &MRI, StringRef TT, - StringRef CPU); + StringRef CPU, + const MCTargetOptions &Options); MCAsmBackend *createMipsAsmBackendEL32(const Target &T, const MCRegisterInfo &MRI, StringRef TT, - StringRef CPU); + StringRef CPU, + const MCTargetOptions &Options); MCAsmBackend *createMipsAsmBackendEB64(const Target &T, const MCRegisterInfo &MRI, StringRef TT, - StringRef CPU); + StringRef CPU, + const MCTargetOptions &Options); MCAsmBackend *createMipsAsmBackendEL64(const Target &T, const MCRegisterInfo &MRI, StringRef TT, - StringRef CPU); + StringRef CPU, + const MCTargetOptions &Options); MCObjectWriter *createMipsELFObjectWriter(raw_ostream &OS, uint8_t OSABI, bool IsLittleEndian, bool Is64Bit); Index: lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp =================================================================== --- lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp +++ lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp @@ -235,7 +235,8 @@ MCAsmBackend *llvm::createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI, - StringRef TT, StringRef CPU) { + StringRef TT, StringRef CPU, + const MCTargetOptions&) { if (Triple(TT).isOSDarwin()) return new DarwinPPCAsmBackend(T); Index: lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h =================================================================== --- lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h +++ lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h @@ -27,6 +27,7 @@ class MCObjectWriter; class MCRegisterInfo; class MCSubtargetInfo; +class MCTargetOptions; class Target; class StringRef; class raw_ostream; @@ -41,7 +42,8 @@ MCContext &Ctx); MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI, - StringRef TT, StringRef CPU); + StringRef TT, StringRef CPU, + const MCTargetOptions &Options); /// createPPCELFObjectWriter - Construct an PPC ELF object writer. MCObjectWriter *createPPCELFObjectWriter(raw_ostream &OS, Index: lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp =================================================================== --- lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp +++ lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp @@ -141,6 +141,7 @@ MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, - StringRef CPU) { + StringRef CPU, + const MCTargetOptions&) { return new ELFAMDGPUAsmBackend(T); } Index: lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.h =================================================================== --- lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.h +++ lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.h @@ -26,6 +26,7 @@ class MCObjectWriter; class MCRegisterInfo; class MCSubtargetInfo; +class MCTargetOptions; class Target; class raw_ostream; @@ -42,7 +43,8 @@ MCContext &Ctx); MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI, - StringRef TT, StringRef CPU); + StringRef TT, StringRef CPU, + const MCTargetOptions &Options); MCObjectWriter *createAMDGPUELFObjectWriter(raw_ostream &OS); } // End llvm namespace Index: lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp =================================================================== --- lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp +++ lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp @@ -256,6 +256,7 @@ MCAsmBackend *llvm::createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, - StringRef CPU) { + StringRef CPU, + const MCTargetOptions&) { return new ELFSparcAsmBackend(T, Triple(TT).getOS()); } Index: lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h =================================================================== --- lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h +++ lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h @@ -24,6 +24,7 @@ class MCObjectWriter; class MCRegisterInfo; class MCSubtargetInfo; +class MCTargetOptions; class Target; class StringRef; class raw_ostream; @@ -38,7 +39,8 @@ MCAsmBackend *createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, - StringRef CPU); + StringRef CPU, + const MCTargetOptions &Options); MCObjectWriter *createSparcELFObjectWriter(raw_ostream &OS, bool Is64Bit, uint8_t OSABI); Index: lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp =================================================================== --- lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp +++ lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp @@ -111,7 +111,8 @@ MCAsmBackend *llvm::createSystemZMCAsmBackend(const Target &T, const MCRegisterInfo &MRI, - StringRef TT, StringRef CPU) { + StringRef TT, StringRef CPU, + const MCTargetOptions&) { uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS()); return new SystemZMCAsmBackend(OSABI); } Index: lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h =================================================================== --- lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h +++ lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h @@ -21,6 +21,7 @@ class MCObjectWriter; class MCRegisterInfo; class MCSubtargetInfo; +class MCTargetOptions; class StringRef; class Target; class raw_ostream; @@ -76,7 +77,8 @@ MCAsmBackend *createSystemZMCAsmBackend(const Target &T, const MCRegisterInfo &MRI, - StringRef TT, StringRef CPU); + StringRef TT, StringRef CPU, + const MCTargetOptions &Options); MCObjectWriter *createSystemZObjectWriter(raw_ostream &OS, uint8_t OSABI); } // end namespace llvm Index: lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp =================================================================== --- lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp +++ lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp @@ -789,7 +789,8 @@ MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, - StringRef CPU) { + StringRef CPU, + const MCTargetOptions&) { Triple TheTriple(TT); if (TheTriple.isOSBinFormatMachO()) @@ -805,7 +806,8 @@ MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, - StringRef CPU) { + StringRef CPU, + const MCTargetOptions&) { Triple TheTriple(TT); if (TheTriple.isOSBinFormatMachO()) { Index: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h =================================================================== --- lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h +++ lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h @@ -27,6 +27,7 @@ class MCSubtargetInfo; class MCRelocationInfo; class MCStreamer; +class MCTargetOptions; class Target; class Triple; class StringRef; @@ -82,9 +83,11 @@ MCContext &Ctx); MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, - StringRef TT, StringRef CPU); + StringRef TT, StringRef CPU, + const MCTargetOptions &Options); MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, - StringRef TT, StringRef CPU); + StringRef TT, StringRef CPU, + const MCTargetOptions &Options); /// createX86WinCOFFStreamer - Construct an X86 Windows COFF machine code /// streamer which will generate PE/COFF format object files. Index: tools/llvm-mc/llvm-mc.cpp =================================================================== --- tools/llvm-mc/llvm-mc.cpp +++ tools/llvm-mc/llvm-mc.cpp @@ -458,7 +458,7 @@ MCAsmBackend *MAB = nullptr; if (ShowEncoding) { CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx); - MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU); + MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU, MCOptions); } Str.reset(TheTarget->createAsmStreamer(Ctx, FOS, /*asmverbose*/ true, /*useDwarfDirectory*/ true, IP, CE, @@ -469,7 +469,7 @@ } else { assert(FileType == OFT_ObjectFile && "Invalid file type!"); MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx); - MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU); + MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU, MCOptions); Str.reset(TheTarget->createMCObjectStreamer(TripleName, Ctx, *MAB, FOS, CE, *STI, RelaxAll)); if (NoExecStack)