diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -25022,8 +25022,11 @@
   APInt APIntShiftAmt;
   if (!isConstantSplat(Amt, APIntShiftAmt))
     return SDValue();
-  assert(APIntShiftAmt.ult(VT.getScalarSizeInBits()) &&
-         "Out of range shift amount");
+
+  // If the shift amount is out of range, return undef.
+  if (APIntShiftAmt.uge(VT.getScalarSizeInBits()))
+    return DAG.getUNDEF(VT);
+
   uint64_t ShiftAmt = APIntShiftAmt.getZExtValue();
 
   if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
diff --git a/llvm/test/CodeGen/X86/pr42615.ll b/llvm/test/CodeGen/X86/pr42615.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr42615.ll
@@ -0,0 +1,17 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-w64-windows-gnu -mattr=sse2 | FileCheck %s
+
+define <2 x i64> @_ZL14c_v256_ziphi_86c_v256S_() {
+; CHECK-LABEL: _ZL14c_v256_ziphi_86c_v256S_:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1]
+; CHECK-NEXT:    psllq $56, %xmm0
+; CHECK-NEXT:    retl
+entry:
+  %a.sroa.0.sroa.1.0.copyload = load i64, i64* undef, align 4
+  %0 = insertelement <2 x i64> undef, i64 %a.sroa.0.sroa.1.0.copyload, i32 1
+  %1 = shl <2 x i64> %0, <i64 56, i64 -72057594037927936>
+  %2 = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> <i32 0, i32 3>
+  ret <2 x i64> %2
+}