Index: lib/Target/AMDGPU/SIInstrInfo.td =================================================================== --- lib/Target/AMDGPU/SIInstrInfo.td +++ lib/Target/AMDGPU/SIInstrInfo.td @@ -622,8 +622,12 @@ return CurDAG->getTargetConstant(Bit, SDLoc(N), MVT::i1); }]>; -def SIMM16bit : PatLeaf <(imm), - [{return isInt<16>(N->getSExtValue());}] +def SIMM16bit : ImmLeaf (Imm);}] +>; + +def UIMM16bit : ImmLeaf (Imm); }] >; class InlineImm : PatLeaf <(vt imm), [{ Index: lib/Target/AMDGPU/SOPInstructions.td =================================================================== --- lib/Target/AMDGPU/SOPInstructions.td +++ lib/Target/AMDGPU/SOPInstructions.td @@ -1090,7 +1090,7 @@ let mayLoad = 1, mayStore = 1, hasSideEffects = 1 in def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "s_waitcnt $simm16", - [(int_amdgcn_s_waitcnt SIMM16bit:$simm16)]>; + [(int_amdgcn_s_waitcnt UIMM16bit:$simm16)]>; def S_SETHALT : SOPP <0x0000000d, (ins i16imm:$simm16), "s_sethalt $simm16">; def S_SETKILL : SOPP <0x0000000b, (ins i16imm:$simm16), "s_setkill $simm16">; Index: test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll =================================================================== --- test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll +++ test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll @@ -31,6 +31,18 @@ ret void } +; CHECK-LABEL: {{^}}test3: +; CHECK: image_load +; CHECK: s_waitcnt vmcnt(0) lgkmcnt(0) +; CHECK: image_store +define amdgpu_ps void @test3(<8 x i32> inreg %rsrc, i32 %c) { + %t = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %c, <8 x i32> %rsrc, i32 0, i32 0) + call void @llvm.amdgcn.s.waitcnt(i32 49279) ; not isInt<16>, but isUInt<16> + %c.1 = mul i32 %c, 2 + call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %t, i32 15, i32 %c.1, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + declare void @llvm.amdgcn.s.waitcnt(i32) #0 declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32, i32, <8 x i32>, i32, i32) #1