AMDGPU/GISel: Add support for vector shader inputs

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td

64

I think this should be handled by decomposing the incoming types into 32-bit pieces, and repacking. We do this for functions in the DAG and it's less constraining on the lowering. This also avoids SGPR alignment, since they will be repacked if necessary

[arsenm]

This can be abandoned, D64721 supersedes it

llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp

if (F.getCallingConv() == CallingConv::AMDGPU_PS &&
         Info->markPSInputEnabled(PSInputNum);
 
       ++PSInputNum;
     }
 
     CCAssignFn *AssignFn = CCAssignFnForCall(F.getCallingConv(),
                                              /*IsVarArg=*/false);
 
-    if (ValEVT.isVector()) {
-      EVT ElemVT = ValEVT.getVectorElementType();
-      if (!ValEVT.isSimple())
-        return false;
-      MVT ValVT = ElemVT.getSimpleVT();
-      bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full,
-                          OrigArg.Flags, CCInfo);
-      if (!Res)
-        return false;
-    } else {
-      MVT ValVT = ValEVT.getSimpleVT();
-      if (!ValEVT.isSimple())
-        return false;
-      bool Res =
-          AssignFn(i, ValVT, ValVT, CCValAssign::Full, OrigArg.Flags, CCInfo);
+    if (!ValEVT.isSimple()) {
+      if (!ValEVT.isVector() ||
+          ValEVT.getVectorNumElements() !=3 ||
+          ValEVT.getVectorElementType() != MVT::i32 ||
+          OrigArg.Flags.isInReg())
+
+      // Special case for v3i32 into vgprs
+      // Up to VGPR0-VGPR135
+      const TargetRegisterClass *RC = &AMDGPU::VReg_96RegClass;
+      unsigned NumRegs = 45;
+      ArrayRef<MCPhysReg> RegList = makeArrayRef(RC->begin(), NumRegs);
+      unsigned RegResult = CCInfo.AllocateReg(RegList);
+      CCInfo.addLoc(CCValAssign::getReg(i, MVT::Other, RegResult, MVT::Other,
+                                        CCValAssign::Full));
+      continue;
+    }
 
-      // Fail if we don't know how to handle this type.
-      if (Res)
-        return false;
-    }
-  }
 
   Function::const_arg_iterator Arg = F.arg_begin();
 
   if (F.getCallingConv() == CallingConv::AMDGPU_VS ||
       F.getCallingConv() == CallingConv::AMDGPU_PS) {
     for (unsigned i = 0, OrigArgIdx = 0;
          OrigArgIdx != NumArgs && i != ArgLocs.size(); ++Arg, ++OrigArgIdx) {
        if (Skipped.test(OrigArgIdx))

llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td

CCIfNotInReg<CCIfType<[f32, i32, f16, v2i16, v2f16] , CCAssignToReg<[
     VGPR72, VGPR73, VGPR74, VGPR75, VGPR76, VGPR77, VGPR78, VGPR79,
     VGPR80, VGPR81, VGPR82, VGPR83, VGPR84, VGPR85, VGPR86, VGPR87,
     VGPR88, VGPR89, VGPR90, VGPR91, VGPR92, VGPR93, VGPR94, VGPR95,
     VGPR96, VGPR97, VGPR98, VGPR99, VGPR100, VGPR101, VGPR102, VGPR103,
     VGPR104, VGPR105, VGPR106, VGPR107, VGPR108, VGPR109, VGPR110, VGPR111,
     VGPR112, VGPR113, VGPR114, VGPR115, VGPR116, VGPR117, VGPR118, VGPR119,
     VGPR120, VGPR121, VGPR122, VGPR123, VGPR124, VGPR125, VGPR126, VGPR127,
     VGPR128, VGPR129, VGPR130, VGPR131, VGPR132, VGPR133, VGPR134, VGPR135
-  ]>>>
+  ]>>>,
+
+  CCIfNotInReg<CCIfType<[v2i32, v2f32], CCCustom<"allocateVGPRTuple">>>
 ]>;
 
 def RetCC_SI_Shader : CallingConv<[
   CCIfType<[i32] , CCAssignToReg<[
     SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
     SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
     SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23,
     SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29, SGPR30, SGPR31,