diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td --- a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -1774,6 +1774,19 @@ def : StoreRegImmPat, FGR_64, ISA_MICROMIPS32R6; } +let isCall=1, hasDelaySlot=0, isCTI=1, Defs = [RA] in { + class JumpLinkMMR6 : + PseudoSE<(outs), (ins calltarget:$target), [], II_JAL>, + PseudoInstExpansion<(JumpInst Opnd:$target)>; +} + +def JAL_MMR6 : JumpLinkMMR6, ISA_MICROMIPS32R6; + +def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), + (JAL_MMR6 texternalsym:$dst)>, ISA_MICROMIPS32R6; +def : MipsPat<(MipsJmpLink (iPTR tglobaladdr:$dst)), + (JAL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6; + def TAILCALL_MMR6 : TailCall, ISA_MICROMIPS32R6; def TAILCALLREG_MMR6 : TailCallReg, ISA_MICROMIPS32R6; diff --git a/llvm/lib/Target/Mips/MipsScheduleGeneric.td b/llvm/lib/Target/Mips/MipsScheduleGeneric.td --- a/llvm/lib/Target/Mips/MipsScheduleGeneric.td +++ b/llvm/lib/Target/Mips/MipsScheduleGeneric.td @@ -384,7 +384,7 @@ BGTZC_MMR6, BLEZC_MMR6, BLTC_MMR6, BLTUC_MMR6, BLTZC_MMR6, BNEC_MMR6, BNEZC16_MMR6, BNEZC_MMR6, BNVC_MMR6, - BOVC_MMR6, DERET_MMR6, ERETNC_MMR6, + BOVC_MMR6, DERET_MMR6, ERETNC_MMR6, JAL_MMR6, ERET_MMR6, JIC_MMR6, JRADDIUSP, JRC16_MM, JRC16_MMR6, JRCADDIUSP_MMR6, SIGRIE_MMR6, B_MMR6_Pseudo, PseudoIndirectBranch_MMR6)>; diff --git a/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll b/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll --- a/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/fptosi.ll @@ -208,7 +208,7 @@ ; MMR6-SF-NEXT: # ; MMR6-SF-NEXT: # > ; MMR6-SF-NEXT: .cfi_offset 31, -4 -; MMR6-SF-NEXT: jalr __fixsfsi # > ; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload ; MMR6-SF-NEXT: # ; MMR6-SF-NEXT: # > ; MMR6-SF-NEXT: .cfi_offset 31, -4 -; MMR6-SF-NEXT: jalr __fixdfsi # > ; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload ; MMR6-SF-NEXT: #