Index: lib/Target/ARM/Disassembler/ARMDisassembler.cpp
===================================================================
--- lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -1114,16 +1114,20 @@
 
 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder) {
-  if (Val == 0xF) return MCDisassembler::Fail;
+  DecodeStatus Result = MCDisassembler::Success;
+  // Check for invalid condtions.
+  if (Val == 0xF)
+    Result = MCDisassembler::Fail;
   // AL predicate is not allowed on Thumb1 branches.
   if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
-    return MCDisassembler::Fail;
+    Result = MCDisassembler::Fail;
+
   Inst.addOperand(MCOperand::CreateImm(Val));
   if (Val == ARMCC::AL) {
     Inst.addOperand(MCOperand::CreateReg(0));
   } else
     Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
-  return MCDisassembler::Success;
+  return Result;
 }
 
 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
@@ -4100,6 +4104,7 @@
 
   unsigned R = fieldFromInstruction(Val, 5, 1);
   unsigned SysM = fieldFromInstruction(Val, 0, 5);
+  DecodeStatus Result = MCDisassembler::Success;
 
   // The table of encodings for these banked registers comes from B9.2.3 of the
   // ARM ARM. There are patterns, but nothing regular enough to make this logic
@@ -4107,15 +4112,15 @@
   if (!R) {
     if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
         SysM == 0x1a || SysM == 0x1b)
-      return MCDisassembler::SoftFail;
+      Result = MCDisassembler::SoftFail;
   } else {
     if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
         SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
-      return MCDisassembler::SoftFail;
+      Result = MCDisassembler::SoftFail;
   }
 
   Inst.addOperand(MCOperand::CreateImm(Val));
-  return MCDisassembler::Success;
+  return Result;
 }
 
 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,