Index: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp =================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -12030,8 +12030,8 @@ // Selection pass has a hard time dealing with FP constants. bool AllowNewConst = (Level < AfterLegalizeDAG); - // If 'unsafe math' or nnan is enabled, fold lots of things. - if ((Options.UnsafeFPMath || Flags.hasNoNaNs()) && AllowNewConst) { + // If nnan is enabled, fold lots of things. + if ((Options.NoNaNsFPMath || Flags.hasNoNaNs()) && AllowNewConst) { // If allowed, fold (fadd (fneg x), x) -> 0.0 if (N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) return DAG.getConstantFP(0.0, DL, VT); @@ -12171,7 +12171,7 @@ if (N0 == N1) { // (fsub x, x) -> 0.0 - if (Options.UnsafeFPMath || Flags.hasNoNaNs()) + if (Options.NoNaNsFPMath || Flags.hasNoNaNs()) return DAG.getConstantFP(0.0f, DL, VT); } @@ -12249,7 +12249,7 @@ if (SDValue NewSel = foldBinOpIntoSelect(N)) return NewSel; - if (Options.UnsafeFPMath || + if ((Options.NoNaNsFPMath && Options.NoSignedZerosFPMath) || (Flags.hasNoNaNs() && Flags.hasNoSignedZeros())) { // fold (fmul A, 0) -> 0 if (N1CFP && N1CFP->isZero()) Index: llvm/trunk/test/CodeGen/ARM/nnan-fsub.ll =================================================================== --- llvm/trunk/test/CodeGen/ARM/nnan-fsub.ll +++ llvm/trunk/test/CodeGen/ARM/nnan-fsub.ll @@ -0,0 +1,18 @@ +; RUN: llc -mcpu=cortex-a9 < %s | FileCheck -check-prefix=SAFE %s +; RUN: llc -mcpu=cortex-a9 --enable-no-nans-fp-math < %s | FileCheck -check-prefix=FAST %s + +target triple = "armv7-apple-ios" + +; SAFE: test +; FAST: test +define float @test(float %x, float %y) { +entry: +; SAFE: vmul.f32 +; SAFE: vsub.f32 +; FAST: mov r0, #0 + %0 = fmul float %x, %y + %1 = fsub float %0, %0 + ret float %1 +} + + Index: llvm/trunk/test/CodeGen/ARM/unsafe-fsub.ll =================================================================== --- llvm/trunk/test/CodeGen/ARM/unsafe-fsub.ll +++ llvm/trunk/test/CodeGen/ARM/unsafe-fsub.ll @@ -1,18 +0,0 @@ -; RUN: llc -mcpu=cortex-a9 < %s | FileCheck -check-prefix=SAFE %s -; RUN: llc -mcpu=cortex-a9 -enable-unsafe-fp-math < %s | FileCheck -check-prefix=FAST %s - -target triple = "armv7-apple-ios" - -; SAFE: test -; FAST: test -define float @test(float %x, float %y) { -entry: -; SAFE: vmul.f32 -; SAFE: vsub.f32 -; FAST: mov r0, #0 - %0 = fmul float %x, %y - %1 = fsub float %0, %0 - ret float %1 -} - - Index: llvm/trunk/test/CodeGen/X86/fmul-combines.ll =================================================================== --- llvm/trunk/test/CodeGen/X86/fmul-combines.ll +++ llvm/trunk/test/CodeGen/X86/fmul-combines.ll @@ -76,12 +76,12 @@ ret <4 x float> %y } -define <4 x float> @fmul0_v4f32(<4 x float> %x) #0 { -; CHECK-LABEL: fmul0_v4f32: +define <4 x float> @fmul0_v4f32_nsz_nnan(<4 x float> %x) #0 { +; CHECK-LABEL: fmul0_v4f32_nsz_nnan: ; CHECK: # %bb.0: ; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: retq - %y = fmul <4 x float> %x, + %y = fmul nnan nsz <4 x float> %x, ret <4 x float> %y } @@ -90,7 +90,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: retq - %y = fmul <4 x float> %x, + %y = fmul nnan nsz <4 x float> %x, ret <4 x float> %y } Index: llvm/trunk/test/CodeGen/X86/fp-fast.ll =================================================================== --- llvm/trunk/test/CodeGen/X86/fp-fast.ll +++ llvm/trunk/test/CodeGen/X86/fp-fast.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx -enable-unsafe-fp-math < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx -enable-unsafe-fp-math --enable-no-nans-fp-math < %s | FileCheck %s define float @test1(float %a) { ; CHECK-LABEL: test1: