Index: lib/Target/AMDGPU/AMDGPU.td
===================================================================
--- lib/Target/AMDGPU/AMDGPU.td
+++ lib/Target/AMDGPU/AMDGPU.td
@@ -666,8 +666,8 @@
    FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
    FeatureAddNoCarryInsts, FeatureFmaMixInsts, FeatureGFX8Insts,
    FeatureNoSdstCMPX, FeatureVscnt, FeatureRegisterBanking,
-   FeatureVOP3Literal, FeatureDPP8, FeatureNoDataDepHazard,
-   FeatureDoesNotSupportSRAMECC
+   FeatureVOP3Literal, FeatureDPP8,
+   FeatureNoDataDepHazard, FeaturePkFmacF16Inst, FeatureDoesNotSupportSRAMECC
   ]
 >;
 
Index: lib/Target/AMDGPU/VOP2Instructions.td
===================================================================
--- lib/Target/AMDGPU/VOP2Instructions.td
+++ lib/Target/AMDGPU/VOP2Instructions.td
@@ -711,10 +711,12 @@
 defm V_FMAC_F16 : VOP2Inst <"v_fmac_f16", VOP_MAC_F16>;
 }
 
-defm V_PK_FMAC_F16 : VOP2Inst<"v_pk_fmac_f16", VOP_V2F16_V2F16_V2F16>;
-
 } // End SubtargetPredicate = isGFX10Plus
 
+let SubtargetPredicate = HasPkFmacF16Inst in {
+defm V_PK_FMAC_F16 : VOP2Inst<"v_pk_fmac_f16", VOP_V2F16_V2F16_V2F16>;
+} // End SubtargetPredicate = HasPkFmacF16Inst
+
 // Note: 16-bit instructions produce a 0 result in the high 16-bits
 // on GFX8 and GFX9 and preserve high 16 bits on GFX10+
 def ClearHI16 : OutPatFrag<(ops node:$op),
@@ -1578,3 +1580,7 @@
 let SubtargetPredicate = HasDot3Insts in {
   defm V_DOT8C_I32_I4  : VOP2_Real_DOT_ACC_gfx9<0x3a>;
 }
+
+let SubtargetPredicate = HasPkFmacF16Inst in {
+defm V_PK_FMAC_F16 : VOP2_Real_e32_vi<0x3c>;
+} // End SubtargetPredicate = HasPkFmacF16Inst
Index: test/MC/AMDGPU/xdl-insts-gfx908.s
===================================================================
--- test/MC/AMDGPU/xdl-insts-gfx908.s
+++ test/MC/AMDGPU/xdl-insts-gfx908.s
@@ -371,3 +371,48 @@
 
 // CHECK: encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x08,0x00]
 v_dot8c_i32_i4_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+
+// CHECK: encoding: [0x01,0x05,0x0a,0x78]
+v_pk_fmac_f16 v5, v1, v2
+
+// CHECK: encoding: [0x01,0x05,0xfe,0x79]
+v_pk_fmac_f16 v255, v1, v2
+
+// CHECK: encoding: [0xff,0x05,0x0a,0x78]
+v_pk_fmac_f16 v5, v255, v2
+
+// CHECK: encoding: [0x01,0x04,0x0a,0x78]
+v_pk_fmac_f16 v5, s1, v2
+
+// CHECK: encoding: [0x6a,0x04,0x0a,0x78]
+v_pk_fmac_f16 v5, vcc_lo, v2
+
+// CHECK: encoding: [0x6b,0x04,0x0a,0x78]
+v_pk_fmac_f16 v5, vcc_hi, v2
+
+// CHECK: encoding: [0x77,0x04,0x0a,0x78]
+v_pk_fmac_f16 v5, ttmp11, v2
+
+// CHECK: encoding: [0x7c,0x04,0x0a,0x78]
+v_pk_fmac_f16 v5, m0, v2
+
+// CHECK: encoding: [0x7e,0x04,0x0a,0x78]
+v_pk_fmac_f16 v5, exec_lo, v2
+
+// CHECK: encoding: [0x7f,0x04,0x0a,0x78]
+v_pk_fmac_f16 v5, exec_hi, v2
+
+// CHECK: encoding: [0x80,0x04,0x0a,0x78]
+v_pk_fmac_f16 v5, 0, v2
+
+// CHECK: encoding: [0xc1,0x04,0x0a,0x78]
+v_pk_fmac_f16 v5, -1, v2
+
+// CHECK: encoding: [0xf0,0x04,0x0a,0x78]
+v_pk_fmac_f16 v5, 0.5, v2
+
+// CHECK: encoding: [0xf7,0x04,0x0a,0x78]
+v_pk_fmac_f16 v5, -4.0, v2
+
+// CHECK: encoding: [0x01,0xff,0x0b,0x78]
+v_pk_fmac_f16 v5, v1, v255
Index: test/MC/Disassembler/AMDGPU/xdl-insts-gfx908.txt
===================================================================
--- test/MC/Disassembler/AMDGPU/xdl-insts-gfx908.txt
+++ test/MC/Disassembler/AMDGPU/xdl-insts-gfx908.txt
@@ -347,3 +347,48 @@
 
 # CHECK: v_dot8c_i32_i4_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x08,0x00]
 0xfa,0x04,0x0a,0x74,0x01,0xe4,0x08,0x00
+
+# CHECK: v_pk_fmac_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x78]
+0x01,0x05,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x79]
+0x01,0x05,0xfe,0x79
+
+# CHECK: v_pk_fmac_f16_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x78]
+0xff,0x05,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x78]
+0x01,0x04,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x78]
+0x6a,0x04,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x78]
+0x6b,0x04,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v5, ttmp11, v2 ; encoding: [0x77,0x04,0x0a,0x78]
+0x77,0x04,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v5, m0, v2 ; encoding: [0x7c,0x04,0x0a,0x78]
+0x7c,0x04,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x78]
+0x7e,0x04,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x78]
+0x7f,0x04,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v5, 0, v2 ; encoding: [0x80,0x04,0x0a,0x78]
+0x80,0x04,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x78]
+0xc1,0x04,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x78]
+0xf0,0x04,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v5, -4.0, v2 ; encoding: [0xf7,0x04,0x0a,0x78]
+0xf7,0x04,0x0a,0x78
+
+# CHECK: v_pk_fmac_f16_e32 v5, v1, v255 ; encoding: [0x01,0xff,0x0b,0x78]
+0x01,0xff,0x0b,0x78