Index: llvm/trunk/docs/AMDGPUUsage.rst =================================================================== --- llvm/trunk/docs/AMDGPUUsage.rst +++ llvm/trunk/docs/AMDGPUUsage.rst @@ -207,6 +207,10 @@ names. ``gfx906`` ``amdgcn`` dGPU - xnack - Radeon Instinct MI50 [off] - Radeon Instinct MI60 + ``gfx908`` ``amdgcn`` dGPU - xnack *TBA* + [off] + sram-ecc + [on] ``gfx909`` ``amdgcn`` APU - xnack *TBA* (Raven Ridge 2) [on] .. TODO @@ -674,7 +678,7 @@ ``EF_AMDGPU_MACH_AMDGCN_GFX902`` 0x02d ``gfx902`` ``EF_AMDGPU_MACH_AMDGCN_GFX904`` 0x02e ``gfx904`` ``EF_AMDGPU_MACH_AMDGCN_GFX906`` 0x02f ``gfx906`` - *reserved* 0x030 Reserved. + ``EF_AMDGPU_MACH_AMDGCN_GFX908`` 0x030 ``gfx908`` ``EF_AMDGPU_MACH_AMDGCN_GFX909`` 0x031 ``gfx909`` *reserved* 0x032 Reserved. ``EF_AMDGPU_MACH_AMDGCN_GFX1010`` 0x033 ``gfx1010`` Index: llvm/trunk/include/llvm/BinaryFormat/ELF.h =================================================================== --- llvm/trunk/include/llvm/BinaryFormat/ELF.h +++ llvm/trunk/include/llvm/BinaryFormat/ELF.h @@ -702,6 +702,7 @@ EF_AMDGPU_MACH_AMDGCN_GFX902 = 0x02d, EF_AMDGPU_MACH_AMDGCN_GFX904 = 0x02e, EF_AMDGPU_MACH_AMDGCN_GFX906 = 0x02f, + EF_AMDGPU_MACH_AMDGCN_GFX908 = 0x030, EF_AMDGPU_MACH_AMDGCN_GFX909 = 0x031, // AMDGCN GFX10. EF_AMDGPU_MACH_AMDGCN_GFX1010 = 0x033, Index: llvm/trunk/include/llvm/Support/TargetParser.h =================================================================== --- llvm/trunk/include/llvm/Support/TargetParser.h +++ llvm/trunk/include/llvm/Support/TargetParser.h @@ -121,6 +121,7 @@ GK_GFX902 = 61, GK_GFX904 = 62, GK_GFX906 = 63, + GK_GFX908 = 64, GK_GFX909 = 65, GK_GFX1010 = 71, Index: llvm/trunk/lib/ObjectYAML/ELFYAML.cpp =================================================================== --- llvm/trunk/lib/ObjectYAML/ELFYAML.cpp +++ llvm/trunk/lib/ObjectYAML/ELFYAML.cpp @@ -410,6 +410,7 @@ BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX902, EF_AMDGPU_MACH); BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX904, EF_AMDGPU_MACH); BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX906, EF_AMDGPU_MACH); + BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX908, EF_AMDGPU_MACH); BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX909, EF_AMDGPU_MACH); BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX1010, EF_AMDGPU_MACH); BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX1011, EF_AMDGPU_MACH); Index: llvm/trunk/lib/Support/TargetParser.cpp =================================================================== --- llvm/trunk/lib/Support/TargetParser.cpp +++ llvm/trunk/lib/Support/TargetParser.cpp @@ -62,7 +62,7 @@ // This table should be sorted by the value of GPUKind // Don't bother listing the implicitly true features -constexpr GPUInfo AMDGCNGPUs[36] = { +constexpr GPUInfo AMDGCNGPUs[37] = { // Name Canonical Kind Features // Name {{"gfx600"}, {"gfx600"}, GK_GFX600, FEATURE_FAST_FMA_F32}, @@ -97,6 +97,7 @@ {{"gfx902"}, {"gfx902"}, GK_GFX902, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32}, {{"gfx904"}, {"gfx904"}, GK_GFX904, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32}, {{"gfx906"}, {"gfx906"}, GK_GFX906, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32}, + {{"gfx908"}, {"gfx908"}, GK_GFX908, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32}, {{"gfx909"}, {"gfx909"}, GK_GFX909, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32}, {{"gfx1010"}, {"gfx1010"}, GK_GFX1010, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32}, {{"gfx1011"}, {"gfx1011"}, GK_GFX1011, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32}, @@ -197,6 +198,7 @@ case GK_GFX902: return {9, 0, 2}; case GK_GFX904: return {9, 0, 4}; case GK_GFX906: return {9, 0, 6}; + case GK_GFX908: return {9, 0, 8}; case GK_GFX909: return {9, 0, 9}; case GK_GFX1010: return {10, 1, 0}; case GK_GFX1011: return {10, 1, 1}; Index: llvm/trunk/lib/Target/AMDGPU/AMDGPU.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPU.td +++ llvm/trunk/lib/Target/AMDGPU/AMDGPU.td @@ -384,6 +384,18 @@ "Has v_dot2_f32_f16, v_dot2_i32_i16, v_dot2_u32_u16, v_dot4_u32_u8, v_dot8_u32_u4 instructions" >; +def FeatureDot3Insts : SubtargetFeature<"dot3-insts", + "HasDot3Insts", + "true", + "Has v_dot8c_i32_i4 instruction" +>; + +def FeatureDot4Insts : SubtargetFeature<"dot4-insts", + "HasDot4Insts", + "true", + "Has v_dot2c_i32_i16 instruction" +>; + def FeatureDot5Insts : SubtargetFeature<"dot5-insts", "HasDot5Insts", "true", @@ -396,6 +408,25 @@ "Has v_dot4c_i32_i8 instruction" >; +def FeatureMAIInsts : SubtargetFeature<"mai-insts", + "HasMAIInsts", + "true", + "Has mAI instructions" +>; + +def FeaturePkFmacF16Inst : SubtargetFeature<"pk-fmac-f16-inst", + "HasPkFmacF16Inst", + "true", + "Has v_pk_fmac_f16 instruction" +>; + +def FeatureAtomicFaddInsts : SubtargetFeature<"atomic-fadd-insts", + "HasAtomicFaddInsts", + "true", + "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, " + "global_atomic_pk_add_f16 instructions" +>; + def FeatureDoesNotSupportSRAMECC : SubtargetFeature<"no-sram-ecc-support", "DoesNotSupportSRAMECC", "true", @@ -755,6 +786,24 @@ FeatureDoesNotSupportXNACK, FeatureCodeObjectV3]>; +def FeatureISAVersion9_0_8 : FeatureSet< + [FeatureGFX9, + HalfRate64Ops, + FeatureFmaMixInsts, + FeatureLDSBankCount32, + FeatureDLInsts, + FeatureDot1Insts, + FeatureDot2Insts, + FeatureDot3Insts, + FeatureDot4Insts, + FeatureDot5Insts, + FeatureDot6Insts, + FeatureMAIInsts, + FeaturePkFmacF16Inst, + FeatureAtomicFaddInsts, + FeatureSRAMECC, + FeatureCodeObjectV3]>; + def FeatureISAVersion9_0_9 : FeatureSet< [FeatureGFX9, FeatureMadMixInsts, @@ -1069,12 +1118,27 @@ def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">, AssemblerPredicate<"FeatureDot2Insts">; +def HasDot3Insts : Predicate<"Subtarget->hasDot3Insts()">, + AssemblerPredicate<"FeatureDot3Insts">; + +def HasDot4Insts : Predicate<"Subtarget->hasDot4Insts()">, + AssemblerPredicate<"FeatureDot4Insts">; + def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">, AssemblerPredicate<"FeatureDot5Insts">; def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">, AssemblerPredicate<"FeatureDot6Insts">; +def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">, + AssemblerPredicate<"FeatureMAIInsts">; + +def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">, + AssemblerPredicate<"FeaturePkFmacF16Inst">; + +def HasAtomicFaddInsts : Predicate<"Subtarget->hasAtomicFaddInsts()">, + AssemblerPredicate<"FeatureAtomicFaddInsts">; + def HasOffset3fBug : Predicate<"!Subtarget->hasOffset3fBug()">, AssemblerPredicate<"FeatureOffset3fBug">; Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h @@ -337,8 +337,13 @@ bool HasDLInsts; bool HasDot1Insts; bool HasDot2Insts; + bool HasDot3Insts; + bool HasDot4Insts; bool HasDot5Insts; bool HasDot6Insts; + bool HasMAIInsts; + bool HasPkFmacF16Inst; + bool HasAtomicFaddInsts; bool EnableSRAMECC; bool DoesNotSupportSRAMECC; bool HasNoSdstCMPX; @@ -779,6 +784,14 @@ return HasDot2Insts; } + bool hasDot3Insts() const { + return HasDot3Insts; + } + + bool hasDot4Insts() const { + return HasDot4Insts; + } + bool hasDot5Insts() const { return HasDot5Insts; } @@ -787,6 +800,18 @@ return HasDot6Insts; } + bool hasMAIInsts() const { + return HasMAIInsts; + } + + bool hasPkFmacF16Inst() const { + return HasPkFmacF16Inst; + } + + bool hasAtomicFaddInsts() const { + return HasAtomicFaddInsts; + } + bool isSRAMECCEnabled() const { return EnableSRAMECC; } Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp @@ -234,8 +234,13 @@ HasDLInsts(false), HasDot1Insts(false), HasDot2Insts(false), + HasDot3Insts(false), + HasDot4Insts(false), HasDot5Insts(false), HasDot6Insts(false), + HasMAIInsts(false), + HasPkFmacF16Inst(false), + HasAtomicFaddInsts(false), EnableSRAMECC(false), DoesNotSupportSRAMECC(false), HasNoSdstCMPX(false), Index: llvm/trunk/lib/Target/AMDGPU/GCNProcessors.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/GCNProcessors.td +++ llvm/trunk/lib/Target/AMDGPU/GCNProcessors.td @@ -160,6 +160,10 @@ FeatureISAVersion9_0_6.Features >; +def : ProcessorModel<"gfx908", SIQuarterSpeedModel, + FeatureISAVersion9_0_8.Features +>; + def : ProcessorModel<"gfx909", SIQuarterSpeedModel, FeatureISAVersion9_0_9.Features >; Index: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp +++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp @@ -91,6 +91,7 @@ case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break; case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break; case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break; + case ELF::EF_AMDGPU_MACH_AMDGCN_GFX908: AK = GK_GFX908; break; case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break; case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: AK = GK_GFX1010; break; case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011: AK = GK_GFX1011; break; @@ -141,6 +142,7 @@ case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902; case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904; case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906; + case GK_GFX908: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX908; case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909; case GK_GFX1010: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010; case GK_GFX1011: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011; Index: llvm/trunk/test/CodeGen/AMDGPU/elf-header-flags-mach.ll =================================================================== --- llvm/trunk/test/CodeGen/AMDGPU/elf-header-flags-mach.ll +++ llvm/trunk/test/CodeGen/AMDGPU/elf-header-flags-mach.ll @@ -46,6 +46,7 @@ ; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx902 < %s | llvm-readobj -file-headers - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX902 %s ; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx904 < %s | llvm-readobj -file-headers - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX904 %s ; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx906 < %s | llvm-readobj -file-headers - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX906 %s +; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx908 < %s | llvm-readobj -file-headers - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX908 %s ; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx909 < %s | llvm-readobj -file-headers - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX909 %s ; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx1010 < %s | llvm-readobj -file-headers - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1010 %s ; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx1011 < %s | llvm-readobj -file-headers - | FileCheck --check-prefixes=ALL,ARCH-GCN,GFX1011 %s @@ -89,6 +90,8 @@ ; GFX902-NEXT: EF_AMDGPU_XNACK (0x100) ; GFX904: EF_AMDGPU_MACH_AMDGCN_GFX904 (0x2E) ; GFX906: EF_AMDGPU_MACH_AMDGCN_GFX906 (0x2F) +; GFX908: EF_AMDGPU_MACH_AMDGCN_GFX908 (0x30) +; GFX908-NEXT: EF_AMDGPU_SRAM_ECC (0x200) ; GFX909: EF_AMDGPU_MACH_AMDGCN_GFX909 (0x31) ; GFX1010: EF_AMDGPU_MACH_AMDGCN_GFX1010 (0x33) ; GFX1011: EF_AMDGPU_MACH_AMDGCN_GFX1011 (0x34) Index: llvm/trunk/test/CodeGen/AMDGPU/elf-header-flags-sram-ecc.ll =================================================================== --- llvm/trunk/test/CodeGen/AMDGPU/elf-header-flags-sram-ecc.ll +++ llvm/trunk/test/CodeGen/AMDGPU/elf-header-flags-sram-ecc.ll @@ -7,6 +7,8 @@ ; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx906 -mattr=+sram-ecc < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=SRAM-ECC-GFX906 %s ; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx906 -mattr=+sram-ecc,+xnack < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=SRAM-ECC-XNACK-GFX906 %s +; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx908 < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=SRAM-ECC-GFX908 %s + ; NO-SRAM-ECC-GFX902: Flags [ ; NO-SRAM-ECC-GFX902-NEXT: EF_AMDGPU_MACH_AMDGCN_GFX902 (0x2D) ; NO-SRAM-ECC-GFX902-NEXT: EF_AMDGPU_XNACK (0x100) @@ -33,6 +35,11 @@ ; SRAM-ECC-XNACK-GFX906-NEXT: EF_AMDGPU_XNACK (0x100) ; SRAM-ECC-XNACK-GFX906-NEXT: ] +; SRAM-ECC-GFX908: Flags [ (0x230) +; SRAM-ECC-GFX908: EF_AMDGPU_MACH_AMDGCN_GFX908 (0x30) +; SRAM-ECC-GFX908: EF_AMDGPU_SRAM_ECC (0x200) +; SRAM-ECC-GFX908: ] + define amdgpu_kernel void @elf_header() { ret void } Index: llvm/trunk/test/CodeGen/AMDGPU/hsa-note-no-func.ll =================================================================== --- llvm/trunk/test/CodeGen/AMDGPU/hsa-note-no-func.ll +++ llvm/trunk/test/CodeGen/AMDGPU/hsa-note-no-func.ll @@ -23,6 +23,7 @@ ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx902 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX902 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx904 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX904 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx906 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX906 %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx908 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX908 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx909 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX909 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX1010 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1011 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX1011 %s @@ -44,6 +45,7 @@ ; HSA-GFX902: .hsa_code_object_isa 9,0,2,"AMD","AMDGPU" ; HSA-GFX904: .hsa_code_object_isa 9,0,4,"AMD","AMDGPU" ; HSA-GFX906: .hsa_code_object_isa 9,0,6,"AMD","AMDGPU" +; HSA-GFX908: .hsa_code_object_isa 9,0,8,"AMD","AMDGPU" ; HSA-GFX909: .hsa_code_object_isa 9,0,9,"AMD","AMDGPU" ; HSA-GFX1010: .hsa_code_object_isa 10,1,0,"AMD","AMDGPU" ; HSA-GFX1011: .hsa_code_object_isa 10,1,1,"AMD","AMDGPU" Index: llvm/trunk/test/MC/AMDGPU/dl-insts.s =================================================================== --- llvm/trunk/test/MC/AMDGPU/dl-insts.s +++ llvm/trunk/test/MC/AMDGPU/dl-insts.s @@ -1,4 +1,5 @@ // RUN: llvm-mc -arch=amdgcn -mcpu=gfx906 -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -mcpu=gfx908 -show-encoding %s | FileCheck %s // // VOP2 Instructions. Index: llvm/trunk/test/MC/Disassembler/AMDGPU/dl-insts.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/AMDGPU/dl-insts.txt +++ llvm/trunk/test/MC/Disassembler/AMDGPU/dl-insts.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -arch=amdgcn -mcpu=gfx906 -disassemble -show-encoding < %s | FileCheck %s +# RUN: llvm-mc -arch=amdgcn -mcpu=gfx908 -disassemble -show-encoding < %s | FileCheck %s # CHECK: v_fmac_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x76] 0x01,0x05,0x0a,0x76 Index: llvm/trunk/test/Object/AMDGPU/elf-header-flags-mach.yaml =================================================================== --- llvm/trunk/test/Object/AMDGPU/elf-header-flags-mach.yaml +++ llvm/trunk/test/Object/AMDGPU/elf-header-flags-mach.yaml @@ -92,11 +92,14 @@ # RUN: llvm-readobj -S --file-headers %t.o.31 | FileCheck --check-prefixes=ELF-ALL,ELF-GFX906 %s # RUN: obj2yaml %t.o.31 | FileCheck --check-prefixes=YAML-GFX906 %s # RUN: yaml2obj -docnum=32 %s > %t.o.32 -# RUN: llvm-readobj -S --file-headers %t.o.32 | FileCheck --check-prefixes=ELF-ALL,ELF-GFX909 %s -# RUN: obj2yaml %t.o.32 | FileCheck --check-prefixes=YAML-GFX909 %s +# RUN: llvm-readobj -s -file-headers %t.o.32 | FileCheck --check-prefixes=ELF-ALL,ELF-GFX908 %s +# RUN: obj2yaml %t.o.32 | FileCheck --check-prefixes=YAML-GFX908 %s # RUN: yaml2obj -docnum=33 %s > %t.o.33 -# RUN: llvm-readobj -s -file-headers %t.o.33 | FileCheck --check-prefixes=ELF-ALL,ELF-GFX1010 %s -# RUN: obj2yaml %t.o.33 | FileCheck --check-prefixes=YAML-GFX1010 %s +# RUN: llvm-readobj -s -file-headers %t.o.33 | FileCheck --check-prefixes=ELF-ALL,ELF-GFX909 %s +# RUN: obj2yaml %t.o.33 | FileCheck --check-prefixes=YAML-GFX909 %s +# RUN: yaml2obj -docnum=34 %s > %t.o.34 +# RUN: llvm-readobj -s -file-headers %t.o.34 | FileCheck --check-prefixes=ELF-ALL,ELF-GFX1010 %s +# RUN: obj2yaml %t.o.34 | FileCheck --check-prefixes=YAML-GFX1010 %s # ELF-ALL: Flags [ # ELF-R600: EF_AMDGPU_MACH_R600_R600 (0x1) @@ -130,6 +133,7 @@ # ELF-GFX902: EF_AMDGPU_MACH_AMDGCN_GFX902 (0x2D) # ELF-GFX904: EF_AMDGPU_MACH_AMDGCN_GFX904 (0x2E) # ELF-GFX906: EF_AMDGPU_MACH_AMDGCN_GFX906 (0x2F) +# ELF-GFX908: EF_AMDGPU_MACH_AMDGCN_GFX908 (0x30) # ELF-GFX909: EF_AMDGPU_MACH_AMDGCN_GFX909 (0x31) # ELF-GFX1010: EF_AMDGPU_MACH_AMDGCN_GFX1010 (0x33) # ELF-ALL: ] @@ -165,6 +169,7 @@ # YAML-GFX902: Flags: [ EF_AMDGPU_MACH_AMDGCN_GFX902 ] # YAML-GFX904: Flags: [ EF_AMDGPU_MACH_AMDGCN_GFX904 ] # YAML-GFX906: Flags: [ EF_AMDGPU_MACH_AMDGCN_GFX906 ] +# YAML-GFX908: Flags: [ EF_AMDGPU_MACH_AMDGCN_GFX908 ] # YAML-GFX909: Flags: [ EF_AMDGPU_MACH_AMDGCN_GFX909 ] # YAML-GFX1010: Flags: [ EF_AMDGPU_MACH_AMDGCN_GFX1010 ] @@ -517,7 +522,7 @@ OSABI: ELFOSABI_NONE Type: ET_REL Machine: EM_AMDGPU - Flags: [ EF_AMDGPU_MACH_AMDGCN_GFX909 ] + Flags: [ EF_AMDGPU_MACH_AMDGCN_GFX908 ] ... # Doc33 @@ -528,5 +533,17 @@ OSABI: ELFOSABI_NONE Type: ET_REL Machine: EM_AMDGPU + Flags: [ EF_AMDGPU_MACH_AMDGCN_GFX909 ] +... + +# Doc34 +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + OSABI: ELFOSABI_NONE + Type: ET_REL + Machine: EM_AMDGPU Flags: [ EF_AMDGPU_MACH_AMDGCN_GFX1010 ] ... + Index: llvm/trunk/tools/llvm-readobj/ELFDumper.cpp =================================================================== --- llvm/trunk/tools/llvm-readobj/ELFDumper.cpp +++ llvm/trunk/tools/llvm-readobj/ELFDumper.cpp @@ -1294,6 +1294,7 @@ LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX902), LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX904), LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX906), + LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX908), LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX909), LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1010), LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1011),