Index: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
@@ -2591,7 +2591,7 @@
 // VFP/NEON Instruction aliases for type suffices.
 // Note: When EmitPriority == 1, the alias will be used for printing
 class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result, bit EmitPriority = 0> :
-  InstAlias<!strconcat(opc, dt, "\t", asm), Result, EmitPriority>, Requires<[HasVFP2]>;
+  InstAlias<!strconcat(opc, dt, "\t", asm), Result, EmitPriority>, Requires<[HasFPRegs]>;
 
 // Note: When EmitPriority == 1, the alias will be used for printing
 multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result, bit EmitPriority = 0> {
Index: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
@@ -302,13 +302,13 @@
 }
 
 def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r), 0>,
-                Requires<[HasVFP2]>;
+                Requires<[HasFPRegs]>;
 def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r), 0>,
-                Requires<[HasVFP2]>;
+                Requires<[HasFPRegs]>;
 def : InstAlias<"vpop${p} $r",  (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r), 0>,
-                Requires<[HasVFP2]>;
+                Requires<[HasFPRegs]>;
 def : InstAlias<"vpop${p} $r",  (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r), 0>,
-                Requires<[HasVFP2]>;
+                Requires<[HasFPRegs]>;
 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
                          (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>;
 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
Index: llvm/trunk/test/MC/ARM/mve-fp-registers.s
===================================================================
--- llvm/trunk/test/MC/ARM/mve-fp-registers.s
+++ llvm/trunk/test/MC/ARM/mve-fp-registers.s
@@ -45,18 +45,50 @@
 # FP32: vldmia  r0, {d0}               @ encoding: [0x90,0xec,0x02,0x0b]
 # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
 
+vpop    {d0-d15}
+# FP32: vpop {{.*}}                     @ encoding: [0xbd,0xec,0x20,0x0b]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
+vpop.64    {d0-d15}
+# FP32: vpop {{.*}}                     @ encoding: [0xbd,0xec,0x20,0x0b]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
 vstmia  r0, {d0}
 # FP32: vstmia  r0, {d0}                @ encoding: [0x80,0xec,0x02,0x0b]
 # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
 
+vpush    {d0-d15}
+# FP32: vpush {{.*}}                    @ encoding: [0x2d,0xed,0x20,0x0b]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
+vpush.64    {d0-d15}
+# FP32: vpush {{.*}}                    @ encoding: [0x2d,0xed,0x20,0x0b]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
 vldmia  r0, {s0}
 # FP32: vldmia  r0, {s0}                @ encoding: [0x90,0xec,0x01,0x0a]
 # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
 
+vpop {s0-s31}
+# FP32: vpop {{.*}}                     @ encoding: [0xbd,0xec,0x20,0x0a]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
+vpop.32 {s0-s31}
+# FP32: vpop {{.*}}                     @ encoding: [0xbd,0xec,0x20,0x0a]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
 vstmia  r0, {s0}
 # FP32: vstmia  r0, {s0}                @ encoding: [0x80,0xec,0x01,0x0a]
 # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
 
+vpush {s0-s31}
+# FP32: vpush {{.*}}                    @ encoding: [0x2d,0xed,0x20,0x0a]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
+vpush.32 {s0-s31}
+# FP32: vpush {{.*}}                    @ encoding: [0x2d,0xed,0x20,0x0a]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
 fldmdbx r0!, {d0}
 # FP32: fldmdbx r0!, {d0}               @ encoding: [0x30,0xed,0x03,0x0b]
 # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers