Index: include/llvm/IR/PatternMatch.h
===================================================================
--- include/llvm/IR/PatternMatch.h
+++ include/llvm/IR/PatternMatch.h
@@ -69,6 +69,9 @@
 /// Match an arbitrary value and ignore it.
 inline class_match<Value> m_Value() { return class_match<Value>(); }
 
+/// Matches any instruction and ignore it.
+inline class_match<Instruction> m_Instruction() { return class_match<Instruction>(); }
+
 /// Match an arbitrary binary operation and ignore it.
 inline class_match<BinaryOperator> m_BinOp() {
   return class_match<BinaryOperator>();
Index: lib/Analysis/InstructionSimplify.cpp
===================================================================
--- lib/Analysis/InstructionSimplify.cpp
+++ lib/Analysis/InstructionSimplify.cpp
@@ -69,6 +69,41 @@
 static Value *SimplifyGEPInst(Type *, ArrayRef<Value *>, const SimplifyQuery &,
                               unsigned);
 
+/// We want to turn:
+///   (select (icmp sgt x, C), lshr (X, Y), ashr (X, Y)); iff C s>= -1
+///   (select (icmp slt x, C), ashr (X, Y), lshr (X, Y)); iff C s>= 0
+/// into:
+///   ashr (X, Y)
+static Value *foldSelectICmpLshrAshr(const ICmpInst::Predicate Pred,
+                                     const Value *CmpLHS, const Value *CmpRHS,
+                                     Value *TrueVal, Value *FalseVal) {
+  Value *X, *Y;
+  unsigned Bitwidth = CmpRHS->getType()->getScalarSizeInBits();
+  if ((Pred != ICmpInst::ICMP_SGT ||
+       !match(CmpRHS,
+              m_SpecificInt_ICMP(ICmpInst::ICMP_SGE, APInt(Bitwidth, -1)))) &&
+      (Pred != ICmpInst::ICMP_SLT ||
+       !match(CmpRHS,
+              m_SpecificInt_ICMP(ICmpInst::ICMP_SGE, APInt(Bitwidth, 0)))))
+    return nullptr;
+
+  // Canonicalize so that `ashr` is in FalseVal.
+  if (Pred == ICmpInst::ICMP_SLT)
+    std::swap(TrueVal, FalseVal);
+
+  if (match(TrueVal, m_LShr(m_Value(X), m_Value(Y))) &&
+      match(FalseVal, m_AShr(m_Specific(X), m_Specific(Y))) &&
+      match(CmpLHS, m_Specific(X)) &&
+      (!match(FalseVal, m_Exact(m_Instruction())) ||
+       match(TrueVal, m_Exact(m_Instruction())))) {
+    // If either the `ashr` is non-`exact`, or `lshr` is exact too,
+    // then we can just return the `ashr` instruction.
+    return FalseVal;
+  }
+
+  return nullptr;
+}
+
 static Value *foldSelectWithBinaryOp(Value *Cond, Value *TrueVal,
                                      Value *FalseVal) {
   BinaryOperator::BinaryOps BinOpCode;
@@ -3736,6 +3771,10 @@
       return TrueVal;
   }
 
+  if (Value *V =
+          foldSelectICmpLshrAshr(Pred, CmpLHS, CmpRHS, TrueVal, FalseVal))
+    return V;
+
   return nullptr;
 }
 
Index: lib/Transforms/InstCombine/InstCombineSelect.cpp
===================================================================
--- lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -532,6 +532,45 @@
 }
 
 /// We want to turn:
+///   (select (icmp sgt x, C), lshr (X, Y), ashr (X, Y)); iff C s>= -1
+///   (select (icmp slt x, C), ashr (X, Y), lshr (X, Y)); iff C s>= 0
+/// into:
+///   ashr (X, Y)
+/// It is assumed that InstSimplify has already run.
+static Value *foldSelectICmpLshrAshr(const ICmpInst *IC, Value *TrueVal,
+                                     Value *FalseVal,
+                                     InstCombiner::BuilderTy &Builder) {
+  ICmpInst::Predicate Pred = IC->getPredicate();
+  Value *CmpLHS = IC->getOperand(0);
+  Value *CmpRHS = IC->getOperand(1);
+
+  Value *X, *Y;
+  unsigned Bitwidth = CmpRHS->getType()->getScalarSizeInBits();
+  if ((Pred != ICmpInst::ICMP_SGT ||
+       !match(CmpRHS,
+              m_SpecificInt_ICMP(ICmpInst::ICMP_SGE, APInt(Bitwidth, -1)))) &&
+      (Pred != ICmpInst::ICMP_SLT ||
+       !match(CmpRHS,
+              m_SpecificInt_ICMP(ICmpInst::ICMP_SGE, APInt(Bitwidth, 0)))))
+    return nullptr;
+
+  // Canonicalize so that `ashr` is in FalseVal.
+  if (Pred == ICmpInst::ICMP_SLT)
+    std::swap(TrueVal, FalseVal);
+
+  if (match(TrueVal, m_LShr(m_Value(X), m_Value(Y))) &&
+      match(FalseVal, m_AShr(m_Specific(X), m_Specific(Y))) &&
+      match(CmpLHS, m_Specific(X))) {
+    const auto *Ashr = cast<Instruction>(FalseVal);
+    // This new ashr must not be exact.
+    return Builder.CreateAShr(Ashr->getOperand(0), Ashr->getOperand(1),
+                              Ashr->getName(), /*isExact=*/false);
+  }
+
+  return nullptr;
+}
+
+/// We want to turn:
 ///   (select (icmp eq (and X, C1), 0), Y, (or Y, C2))
 /// into:
 ///   (or (shl (and X, C1), C3), Y)
@@ -1112,6 +1151,9 @@
   if (Value *V = foldSelectICmpAndOr(ICI, TrueVal, FalseVal, Builder))
     return replaceInstUsesWith(SI, V);
 
+  if (Value *V = foldSelectICmpLshrAshr(ICI, TrueVal, FalseVal, Builder))
+    return replaceInstUsesWith(SI, V);
+
   if (Value *V = foldSelectCttzCtlz(ICI, TrueVal, FalseVal, Builder))
     return replaceInstUsesWith(SI, V);
 
Index: test/Transforms/InstCombine/ashr-lshr.ll
===================================================================
--- test/Transforms/InstCombine/ashr-lshr.ll
+++ test/Transforms/InstCombine/ashr-lshr.ll
@@ -3,11 +3,8 @@
 
 define i32 @ashr_lshr(i32 %x, i32 %y) {
 ; CHECK-LABEL: @ashr_lshr(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
-; CHECK-NEXT:    [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
-; CHECK-NEXT:    [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
-; CHECK-NEXT:    ret i32 [[RET]]
+; CHECK-NEXT:    [[R1:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i32 [[R1]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %l = lshr i32 %x, %y
@@ -18,11 +15,8 @@
 
 define i32 @ashr_lshr2(i32 %x, i32 %y) {
 ; CHECK-LABEL: @ashr_lshr2(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], 5
-; CHECK-NEXT:    [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
-; CHECK-NEXT:    [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
-; CHECK-NEXT:    ret i32 [[RET]]
+; CHECK-NEXT:    [[R1:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i32 [[R1]]
 ;
   %cmp = icmp sgt i32 %x, 5
   %l = lshr i32 %x, %y
@@ -31,13 +25,10 @@
   ret i32 %ret
 }
 
-define <2 x i32> @ashr_lshr_vec(<2 x i32> %x, <2 x i32> %y) {
-; CHECK-LABEL: @ashr_lshr_vec(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
-; CHECK-NEXT:    [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
-; CHECK-NEXT:    [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
-; CHECK-NEXT:    ret <2 x i32> [[RET]]
+define <2 x i32> @ashr_lshr_splat_vec(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @ashr_lshr_splat_vec(
+; CHECK-NEXT:    [[R1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret <2 x i32> [[R1]]
 ;
   %cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
   %l = lshr <2 x i32> %x, %y
@@ -46,13 +37,22 @@
   ret <2 x i32> %ret
 }
 
+define <2 x i32> @ashr_lshr_nonsplat_vec(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @ashr_lshr_nonsplat_vec(
+; CHECK-NEXT:    [[R1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret <2 x i32> [[R1]]
+;
+  %cmp = icmp sgt <2 x i32> %x, <i32 8, i32 7>
+  %l = lshr <2 x i32> %x, %y
+  %r = ashr exact <2 x i32> %x, %y
+  %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
+  ret <2 x i32> %ret
+}
+
 define i32 @ashr_lshr_cst(i32 %x, i32 %y) {
 ; CHECK-LABEL: @ashr_lshr_cst(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 1
-; CHECK-NEXT:    [[L:%.*]] = lshr i32 [[X]], 8
-; CHECK-NEXT:    [[R:%.*]] = ashr exact i32 [[X]], 8
-; CHECK-NEXT:    [[RET:%.*]] = select i1 [[CMP]], i32 [[R]], i32 [[L]]
-; CHECK-NEXT:    ret i32 [[RET]]
+; CHECK-NEXT:    [[R1:%.*]] = ashr i32 [[X:%.*]], 8
+; CHECK-NEXT:    ret i32 [[R1]]
 ;
   %cmp = icmp slt i32 %x, 1
   %l = lshr i32 %x, 8
@@ -63,11 +63,8 @@
 
 define i32 @ashr_lshr_cst2(i32 %x, i32 %y) {
 ; CHECK-LABEL: @ashr_lshr_cst2(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
-; CHECK-NEXT:    [[L:%.*]] = lshr i32 [[X]], 8
-; CHECK-NEXT:    [[R:%.*]] = ashr exact i32 [[X]], 8
-; CHECK-NEXT:    [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
-; CHECK-NEXT:    ret i32 [[RET]]
+; CHECK-NEXT:    [[R1:%.*]] = ashr i32 [[X:%.*]], 8
+; CHECK-NEXT:    ret i32 [[R1]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %l = lshr i32 %x, 8
@@ -78,11 +75,8 @@
 
 define i32 @ashr_lshr_inv(i32 %x, i32 %y) {
 ; CHECK-LABEL: @ashr_lshr_inv(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 1
-; CHECK-NEXT:    [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
-; CHECK-NEXT:    [[RET:%.*]] = select i1 [[CMP]], i32 [[R]], i32 [[L]]
-; CHECK-NEXT:    ret i32 [[RET]]
+; CHECK-NEXT:    [[R1:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i32 [[R1]]
 ;
   %cmp = icmp slt i32 %x, 1
   %l = lshr i32 %x, %y
@@ -93,11 +87,8 @@
 
 define i32 @ashr_lshr_inv2(i32 %x, i32 %y) {
 ; CHECK-LABEL: @ashr_lshr_inv2(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 7
-; CHECK-NEXT:    [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
-; CHECK-NEXT:    [[RET:%.*]] = select i1 [[CMP]], i32 [[R]], i32 [[L]]
-; CHECK-NEXT:    ret i32 [[RET]]
+; CHECK-NEXT:    [[R1:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i32 [[R1]]
 ;
   %cmp = icmp slt i32 %x, 7
   %l = lshr i32 %x, %y
@@ -106,13 +97,10 @@
   ret i32 %ret
 }
 
-define <2 x i32> @ashr_lshr_inv_vec(<2 x i32> %x, <2 x i32> %y) {
-; CHECK-LABEL: @ashr_lshr_inv_vec(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]], <i32 1, i32 1>
-; CHECK-NEXT:    [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
-; CHECK-NEXT:    [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
-; CHECK-NEXT:    ret <2 x i32> [[RET]]
+define <2 x i32> @ashr_lshr_inv_splat_vec(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @ashr_lshr_inv_splat_vec(
+; CHECK-NEXT:    [[R1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret <2 x i32> [[R1]]
 ;
   %cmp = icmp slt <2 x i32> %x, <i32 1, i32 1>
   %l = lshr <2 x i32> %x, %y
@@ -121,6 +109,18 @@
   ret <2 x i32> %ret
 }
 
+define <2 x i32> @ashr_lshr_inv_nonsplat_vec(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @ashr_lshr_inv_nonsplat_vec(
+; CHECK-NEXT:    [[R1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret <2 x i32> [[R1]]
+;
+  %cmp = icmp slt <2 x i32> %x, <i32 4, i32 5>
+  %l = lshr <2 x i32> %x, %y
+  %r = ashr exact <2 x i32> %x, %y
+  %ret = select <2 x i1> %cmp, <2 x i32> %r, <2 x i32> %l
+  ret <2 x i32> %ret
+}
+
 ; Negative tests
 
 define i32 @ashr_lshr_wrong_cst(i32 %x, i32 %y) {
@@ -303,13 +303,36 @@
   ret <2 x i32> %ret
 }
 
+define <2 x i32> @ashr_lshr_vec_undef(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @ashr_lshr_vec_undef(
+; CHECK-NEXT:    [[R1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret <2 x i32> [[R1]]
+;
+  %cmp = icmp sgt <2 x i32> %x, <i32 undef, i32 -1>
+  %l = lshr <2 x i32> %x, %y
+  %r = ashr exact <2 x i32> %x, %y
+  %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
+  ret <2 x i32> %ret
+}
+
+define <2 x i32> @ashr_lshr_vec_undef2(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @ashr_lshr_vec_undef2(
+; CHECK-NEXT:    [[R1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret <2 x i32> [[R1]]
+;
+  %cmp = icmp slt <2 x i32> %x, <i32 1, i32 undef>
+  %l = lshr <2 x i32> %x, %y
+  %r = ashr exact <2 x i32> %x, %y
+  %ret = select <2 x i1> %cmp, <2 x i32> %r, <2 x i32> %l
+  ret <2 x i32> %ret
+}
+
+; Simplified by InstSimplify
+
 define i32 @ashr_lshr_no_exact(i32 %x, i32 %y) {
 ; CHECK-LABEL: @ashr_lshr_no_exact(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
-; CHECK-NEXT:    [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X]], [[Y]]
-; CHECK-NEXT:    [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
-; CHECK-NEXT:    ret i32 [[RET]]
+; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i32 [[R]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %l = lshr i32 %x, %y
@@ -321,11 +344,8 @@
 
 define i32 @ashr_lshr_exact_both(i32 %x, i32 %y) {
 ; CHECK-LABEL: @ashr_lshr_exact_both(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
-; CHECK-NEXT:    [[L:%.*]] = lshr exact i32 [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
-; CHECK-NEXT:    [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
-; CHECK-NEXT:    ret i32 [[RET]]
+; CHECK-NEXT:    [[R:%.*]] = ashr exact i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i32 [[R]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %l = lshr exact i32 %x, %y
@@ -334,13 +354,10 @@
   ret i32 %ret
 }
 
-define i32 @ashr_lshr_exact_mismatch2(i32 %x, i32 %y) {
-; CHECK-LABEL: @ashr_lshr_exact_mismatch2(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
-; CHECK-NEXT:    [[L:%.*]] = lshr exact i32 [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X]], [[Y]]
-; CHECK-NEXT:    [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
-; CHECK-NEXT:    ret i32 [[RET]]
+define i32 @ashr_lshr_exact_lshr_only(i32 %x, i32 %y) {
+; CHECK-LABEL: @ashr_lshr_exact_lshr_only(
+; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i32 [[R]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %l = lshr exact i32 %x, %y
@@ -348,33 +365,3 @@
   %ret = select i1 %cmp, i32 %l, i32 %r
   ret i32 %ret
 }
-
-define <2 x i32> @ashr_lshr_vec_undef(<2 x i32> %x, <2 x i32> %y) {
-; CHECK-LABEL: @ashr_lshr_vec_undef(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 undef, i32 -1>
-; CHECK-NEXT:    [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
-; CHECK-NEXT:    [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
-; CHECK-NEXT:    ret <2 x i32> [[RET]]
-;
-  %cmp = icmp sgt <2 x i32> %x, <i32 undef, i32 -1>
-  %l = lshr <2 x i32> %x, %y
-  %r = ashr exact <2 x i32> %x, %y
-  %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
-  ret <2 x i32> %ret
-}
-
-define <2 x i32> @ashr_lshr_vec_undef2(<2 x i32> %x, <2 x i32> %y) {
-; CHECK-LABEL: @ashr_lshr_vec_undef2(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]], <i32 1, i32 undef>
-; CHECK-NEXT:    [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
-; CHECK-NEXT:    [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
-; CHECK-NEXT:    ret <2 x i32> [[RET]]
-;
-  %cmp = icmp slt <2 x i32> %x, <i32 1, i32 undef>
-  %l = lshr <2 x i32> %x, %y
-  %r = ashr exact <2 x i32> %x, %y
-  %ret = select <2 x i1> %cmp, <2 x i32> %r, <2 x i32> %l
-  ret <2 x i32> %ret
-}
Index: test/Transforms/InstSimplify/ashr-lshr.ll
===================================================================
--- test/Transforms/InstSimplify/ashr-lshr.ll
+++ test/Transforms/InstSimplify/ashr-lshr.ll
@@ -3,11 +3,8 @@
 
 define i32 @ashr_lshr(i32 %x, i32 %y) {
 ; CHECK-LABEL: @ashr_lshr(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
-; CHECK-NEXT:    [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X]], [[Y]]
-; CHECK-NEXT:    [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
-; CHECK-NEXT:    ret i32 [[RET]]
+; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i32 [[R]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %l = lshr i32 %x, %y
@@ -18,11 +15,8 @@
 
 define i32 @ashr_lshr2(i32 %x, i32 %y) {
 ; CHECK-LABEL: @ashr_lshr2(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], 8
-; CHECK-NEXT:    [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X]], [[Y]]
-; CHECK-NEXT:    [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
-; CHECK-NEXT:    ret i32 [[RET]]
+; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i32 [[R]]
 ;
   %cmp = icmp sgt i32 %x, 8
   %l = lshr i32 %x, %y
@@ -33,11 +27,8 @@
 
 define i32 @ashr_lshr_exact_both(i32 %x, i32 %y) {
 ; CHECK-LABEL: @ashr_lshr_exact_both(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
-; CHECK-NEXT:    [[L:%.*]] = lshr exact i32 [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
-; CHECK-NEXT:    [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
-; CHECK-NEXT:    ret i32 [[RET]]
+; CHECK-NEXT:    [[R:%.*]] = ashr exact i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i32 [[R]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %l = lshr exact i32 %x, %y
@@ -48,11 +39,8 @@
 
 define i32 @ashr_lshr_exact_lshr_only(i32 %x, i32 %y) {
 ; CHECK-LABEL: @ashr_lshr_exact_lshr_only(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
-; CHECK-NEXT:    [[L:%.*]] = lshr exact i32 [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X]], [[Y]]
-; CHECK-NEXT:    [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
-; CHECK-NEXT:    ret i32 [[RET]]
+; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i32 [[R]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %l = lshr exact i32 %x, %y
@@ -61,13 +49,10 @@
   ret i32 %ret
 }
 
-define <2 x i32> @ashr_lshr_vec(<2 x i32> %x, <2 x i32> %y) {
-; CHECK-LABEL: @ashr_lshr_vec(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
-; CHECK-NEXT:    [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
-; CHECK-NEXT:    [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
-; CHECK-NEXT:    ret <2 x i32> [[RET]]
+define <2 x i32> @ashr_lshr_splat_vec(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @ashr_lshr_splat_vec(
+; CHECK-NEXT:    [[R:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
   %cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
   %l = lshr <2 x i32> %x, %y
@@ -76,13 +61,10 @@
   ret <2 x i32> %ret
 }
 
-define <2 x i32> @ashr_lshr_vec2(<2 x i32> %x, <2 x i32> %y) {
-; CHECK-LABEL: @ashr_lshr_vec2(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
-; CHECK-NEXT:    [[L:%.*]] = lshr exact <2 x i32> [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
-; CHECK-NEXT:    [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
-; CHECK-NEXT:    ret <2 x i32> [[RET]]
+define <2 x i32> @ashr_lshr_splat_vec2(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @ashr_lshr_splat_vec2(
+; CHECK-NEXT:    [[R:%.*]] = ashr exact <2 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
   %cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
   %l = lshr exact <2 x i32> %x, %y
@@ -91,13 +73,10 @@
   ret <2 x i32> %ret
 }
 
-define <2 x i32> @ashr_lshr_vec3(<2 x i32> %x, <2 x i32> %y) {
-; CHECK-LABEL: @ashr_lshr_vec3(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
-; CHECK-NEXT:    [[L:%.*]] = lshr exact <2 x i32> [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
-; CHECK-NEXT:    [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
-; CHECK-NEXT:    ret <2 x i32> [[RET]]
+define <2 x i32> @ashr_lshr_splat_vec3(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @ashr_lshr_splat_vec3(
+; CHECK-NEXT:    [[R:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
   %cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
   %l = lshr exact <2 x i32> %x, %y
@@ -106,13 +85,46 @@
   ret <2 x i32> %ret
 }
 
+define <2 x i32> @ashr_lshr_nonsplat_vec(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @ashr_lshr_nonsplat_vec(
+; CHECK-NEXT:    [[R:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 1>
+  %l = lshr <2 x i32> %x, %y
+  %r = ashr <2 x i32> %x, %y
+  %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
+  ret <2 x i32> %ret
+}
+
+define <2 x i32> @ashr_lshr_nonsplat_vec2(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @ashr_lshr_nonsplat_vec2(
+; CHECK-NEXT:    [[R:%.*]] = ashr exact <2 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %cmp = icmp sgt <2 x i32> %x, <i32 2, i32 4>
+  %l = lshr exact <2 x i32> %x, %y
+  %r = ashr exact <2 x i32> %x, %y
+  %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
+  ret <2 x i32> %ret
+}
+
+define <2 x i32> @ashr_lshr_nonsplat_vec3(<2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @ashr_lshr_nonsplat_vec3(
+; CHECK-NEXT:    [[R:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %cmp = icmp sgt <2 x i32> %x, <i32 5, i32 6>
+  %l = lshr exact <2 x i32> %x, %y
+  %r = ashr <2 x i32> %x, %y
+  %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
+  ret <2 x i32> %ret
+}
+
 define i32 @ashr_lshr_inv(i32 %x, i32 %y) {
 ; CHECK-LABEL: @ashr_lshr_inv(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 1
-; CHECK-NEXT:    [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X]], [[Y]]
-; CHECK-NEXT:    [[RET:%.*]] = select i1 [[CMP]], i32 [[R]], i32 [[L]]
-; CHECK-NEXT:    ret i32 [[RET]]
+; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i32 [[R]]
 ;
   %cmp = icmp slt i32 %x, 1
   %l = lshr i32 %x, %y
@@ -123,11 +135,8 @@
 
 define i32 @ashr_lshr_inv2(i32 %x, i32 %y) {
 ; CHECK-LABEL: @ashr_lshr_inv2(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 5
-; CHECK-NEXT:    [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X]], [[Y]]
-; CHECK-NEXT:    [[RET:%.*]] = select i1 [[CMP]], i32 [[R]], i32 [[L]]
-; CHECK-NEXT:    ret i32 [[RET]]
+; CHECK-NEXT:    [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i32 [[R]]
 ;
   %cmp = icmp slt i32 %x, 5
   %l = lshr i32 %x, %y
@@ -138,11 +147,8 @@
 
 define <2 x i32> @ashr_lshr_inv_vec(<2 x i32> %x, <2 x i32> %y) {
 ; CHECK-LABEL: @ashr_lshr_inv_vec(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]], <i32 1, i32 1>
-; CHECK-NEXT:    [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
-; CHECK-NEXT:    [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
-; CHECK-NEXT:    ret <2 x i32> [[RET]]
+; CHECK-NEXT:    [[R:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
   %cmp = icmp slt <2 x i32> %x, <i32 1, i32 1>
   %l = lshr <2 x i32> %x, %y
@@ -335,11 +341,8 @@
 
 define <2 x i32> @ashr_lshr_undef2(<2 x i32> %x, <2 x i32> %y) {
 ; CHECK-LABEL: @ashr_lshr_undef2(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 undef, i32 -1>
-; CHECK-NEXT:    [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
-; CHECK-NEXT:    [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
-; CHECK-NEXT:    ret <2 x i32> [[RET]]
+; CHECK-NEXT:    [[R:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
   %cmp = icmp sgt <2 x i32> %x, <i32 undef, i32 -1>
   %l = lshr <2 x i32> %x, %y
@@ -350,11 +353,8 @@
 
 define <2 x i32> @ashr_lshr_undef3(<2 x i32> %x, <2 x i32> %y) {
 ; CHECK-LABEL: @ashr_lshr_undef3(
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]], <i32 1, i32 undef>
-; CHECK-NEXT:    [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
-; CHECK-NEXT:    [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
-; CHECK-NEXT:    [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
-; CHECK-NEXT:    ret <2 x i32> [[RET]]
+; CHECK-NEXT:    [[R:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
   %cmp = icmp slt <2 x i32> %x, <i32 1, i32 undef>
   %l = lshr <2 x i32> %x, %y