Index: lib/Target/Mips/Disassembler/MipsDisassembler.cpp
===================================================================
--- lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -1521,10 +1521,6 @@
   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
-  if (Inst.getOpcode() == Mips::SC ||
-      Inst.getOpcode() == Mips::SCD)
-    Inst.addOperand(MCOperand::createReg(Reg));
-
   Inst.addOperand(MCOperand::createReg(Reg));
   Inst.addOperand(MCOperand::createReg(Base));
   Inst.addOperand(MCOperand::createImm(Offset));
@@ -1543,9 +1539,6 @@
   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
-   if (Inst.getOpcode() == Mips::SCE)
-     Inst.addOperand(MCOperand::createReg(Reg));
-
   Inst.addOperand(MCOperand::createReg(Reg));
   Inst.addOperand(MCOperand::createReg(Base));
   Inst.addOperand(MCOperand::createImm(Offset));
@@ -1854,9 +1847,6 @@
   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
-  if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6)
-    Inst.addOperand(MCOperand::createReg(Reg));
-
   Inst.addOperand(MCOperand::createReg(Reg));
   Inst.addOperand(MCOperand::createReg(Base));
   Inst.addOperand(MCOperand::createImm(Offset));
@@ -1884,9 +1874,6 @@
     Inst.addOperand(MCOperand::createReg(Base));
     Inst.addOperand(MCOperand::createImm(Offset));
     break;
-  case Mips::SC_MM:
-    Inst.addOperand(MCOperand::createReg(Reg));
-    LLVM_FALLTHROUGH;
   default:
     Inst.addOperand(MCOperand::createReg(Reg));
     if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
@@ -2034,10 +2021,6 @@
   Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 
-  if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
-    Inst.addOperand(MCOperand::createReg(Rt));
-  }
-
   Inst.addOperand(MCOperand::createReg(Rt));
   Inst.addOperand(MCOperand::createReg(Base));
   Inst.addOperand(MCOperand::createImm(Offset));
Index: lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
===================================================================
--- lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
+++ lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
@@ -239,15 +239,9 @@
   case Mips::SDC1:
   case Mips::SWL:
   case Mips::SWR:
-    *AddrIdx = 1;
-    if (IsStore)
-      *IsStore = true;
-    return true;
-
-  // Store instructions with base address register in position 2.
   case Mips::SC:
   case Mips::SC_R6:
-    *AddrIdx = 2;
+    *AddrIdx = 1;
     if (IsStore)
       *IsStore = true;
     return true;
Index: lib/Target/Mips/MicroMips32r6InstrInfo.td
===================================================================
--- lib/Target/Mips/MicroMips32r6InstrInfo.td
+++ lib/Target/Mips/MicroMips32r6InstrInfo.td
@@ -826,13 +826,11 @@
                                             II_GINVT>;
 
 class SC_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
-  dag OutOperandList = (outs GPR32Opnd:$dst);
   dag InOperandList = (ins GPR32Opnd:$rt, mem_mm_9:$addr);
   string AsmString = !strconcat(opstr, "\t$rt, $addr");
   InstrItinClass Itinerary = itin;
   string BaseOpcode = opstr;
   bit mayStore = 1;
-  string Constraints = "$rt = $dst";
   string DecoderMethod = "DecodeMemMMImm9";
 }
 
Index: lib/Target/Mips/MicroMipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MicroMipsInstrInfo.td
+++ lib/Target/Mips/MicroMipsInstrInfo.td
@@ -272,20 +272,18 @@
 }
 
 class SCBaseMM<string opstr, RegisterOperand RO> :
-  InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
+  InstSE<(outs), (ins RO:$rt, mem_mm_12:$addr),
          !strconcat(opstr, "\t$rt, $addr"), [], II_SC, FrmI> {
   let DecoderMethod = "DecodeMemMMImm12";
   let mayStore = 1;
-  let Constraints = "$rt = $dst";
 }
 
 class SCEBaseMM<string opstr, RegisterOperand RO> :
-  InstSE<(outs RO:$dst), (ins RO:$rt, mem_simm9:$addr),
+  InstSE<(outs), (ins RO:$rt, mem_simm9:$addr),
          !strconcat(opstr, "\t$rt, $addr"), [], II_SCE, FrmI> {
   let DecoderMethod = "DecodeMemMMImm9";
   string BaseOpcode = opstr;
   let mayStore = 1;
-  let Constraints = "$rt = $dst";
 }
 
 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
Index: lib/Target/Mips/Mips32r6InstrInfo.td
===================================================================
--- lib/Target/Mips/Mips32r6InstrInfo.td
+++ lib/Target/Mips/Mips32r6InstrInfo.td
@@ -769,12 +769,10 @@
 
 class SC_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
                       InstrItinClass itin> {
-  dag OutOperandList = (outs GPROpnd:$dst);
   dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr);
   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
   list<dag> Pattern = [];
   bit mayStore = 1;
-  string Constraints = "$rt = $dst";
   InstrItinClass Itinerary = itin;
 }
 
Index: lib/Target/Mips/MipsEVAInstrInfo.td
===================================================================
--- lib/Target/Mips/MipsEVAInstrInfo.td
+++ lib/Target/Mips/MipsEVAInstrInfo.td
@@ -138,13 +138,11 @@
 
 class SCE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
                     InstrItinClass itin = NoItinerary> {
-  dag OutOperandList = (outs GPROpnd:$dst);
   dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr);
   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
   list<dag> Pattern = [];
   string BaseOpcode = instr_asm;
   bit mayStore = 1;
-  string Constraints = "$rt = $dst";
   string DecoderMethod = "DecodeMemEVA";
   InstrItinClass Itinerary = itin;
 }
Index: lib/Target/Mips/MipsExpandPseudo.cpp
===================================================================
--- lib/Target/Mips/MipsExpandPseudo.cpp
+++ lib/Target/Mips/MipsExpandPseudo.cpp
@@ -152,7 +152,7 @@
   // loop2MBB:
   //   and dest, dest, mask2
   //   or dest, dest, ShiftNewVal
-  //   sc dest, dest, 0(ptr)
+  //   sc dest, 0(ptr)
   //   beq dest, $0, loop1MBB
   BuildMI(loop2MBB, DL, TII->get(Mips::AND), Scratch)
       .addReg(Scratch, RegState::Kill)
@@ -160,8 +160,8 @@
   BuildMI(loop2MBB, DL, TII->get(Mips::OR), Scratch)
       .addReg(Scratch, RegState::Kill)
       .addReg(ShiftNewVal);
-  BuildMI(loop2MBB, DL, TII->get(SC), Scratch)
-      .addReg(Scratch, RegState::Kill)
+  BuildMI(loop2MBB, DL, TII->get(SC))
+      .addReg(Scratch)
       .addReg(Ptr)
       .addImm(0);
   BuildMI(loop2MBB, DL, TII->get(BEQ))
@@ -281,10 +281,10 @@
 
   // loop2MBB:
   //   move scratch, NewVal
-  //   sc Scratch, Scratch, 0(ptr)
+  //   sc Scratch, 0(ptr)
   //   beq Scratch, $0, loop1MBB
   BuildMI(loop2MBB, DL, TII->get(MOVE), Scratch).addReg(NewVal).addReg(ZERO);
-  BuildMI(loop2MBB, DL, TII->get(SC), Scratch)
+  BuildMI(loop2MBB, DL, TII->get(SC))
     .addReg(Scratch).addReg(Ptr).addImm(0);
   BuildMI(loop2MBB, DL, TII->get(BEQ))
     .addReg(Scratch, RegState::Kill).addReg(ZERO).addMBB(loop1MBB);
@@ -433,13 +433,13 @@
 
   // and StoreVal, OlddVal, Mask2
   // or StoreVal, StoreVal, BinOpRes
-  // StoreVal<tied1> = sc StoreVal, 0(Ptr)
+  // sc StoreVal, 0(Ptr)
   // beq StoreVal, zero, loopMBB
   BuildMI(loopMBB, DL, TII->get(Mips::AND), StoreVal)
     .addReg(OldVal).addReg(Mask2);
   BuildMI(loopMBB, DL, TII->get(Mips::OR), StoreVal)
     .addReg(StoreVal).addReg(BinOpRes);
-  BuildMI(loopMBB, DL, TII->get(SC), StoreVal)
+  BuildMI(loopMBB, DL, TII->get(SC))
     .addReg(StoreVal).addReg(Ptr).addImm(0);
   BuildMI(loopMBB, DL, TII->get(BEQ))
     .addReg(StoreVal).addReg(Mips::ZERO).addMBB(loopMBB);
@@ -604,7 +604,7 @@
     BuildMI(loopMBB, DL, TII->get(OR), Scratch).addReg(Incr).addReg(ZERO);
   }
 
-  BuildMI(loopMBB, DL, TII->get(SC), Scratch).addReg(Scratch).addReg(Ptr).addImm(0);
+  BuildMI(loopMBB, DL, TII->get(SC)).addReg(Scratch).addReg(Ptr).addImm(0);
   BuildMI(loopMBB, DL, TII->get(BEQ)).addReg(Scratch).addReg(ZERO).addMBB(loopMBB);
 
   NMBBI = BB.end();
Index: lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- lib/Target/Mips/MipsInstrInfo.td
+++ lib/Target/Mips/MipsInstrInfo.td
@@ -1895,11 +1895,10 @@
 }
 
 class SCBase<string opstr, RegisterOperand RO> :
-  InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
+  InstSE<(outs), (ins RO:$rt, mem:$addr),
          !strconcat(opstr, "\t$rt, $addr"), [], II_SC, FrmI> {
   let DecoderMethod = "DecodeMem";
   let mayStore = 1;
-  let Constraints = "$rt = $dst";
 }
 
 class MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD,
Index: test/CodeGen/Mips/micromips-eva.mir
===================================================================
--- test/CodeGen/Mips/micromips-eva.mir
+++ test/CodeGen/Mips/micromips-eva.mir
@@ -183,8 +183,8 @@
 
     %4:gpr32 = LLE %2, 0
     %6:gpr32 = ADDu %4, %3
-    %8:gpr32 = SCE %6, %2, 0
-    BEQ %8, $zero, %bb.1, implicit-def $at
+    SCE %6, %2, 0
+    BEQ %6, $zero, %bb.1, implicit-def $at
 
   bb.2.entry:
     SYNC 0
Index: test/MC/Mips/sym-sc.s
===================================================================
--- /dev/null
+++ test/MC/Mips/sym-sc.s
@@ -0,0 +1,51 @@
+# RUN: llvm-mc -filetype=obj -triple mips -mcpu=mips2 %s -o - \
+# RUN:   | llvm-objdump -d -r - | FileCheck %s --check-prefix=MIPS
+# RUN: llvm-mc -filetype=obj -triple mips -mcpu=mips32 %s -o - \
+# RUN:   | llvm-objdump -d -r - | FileCheck %s --check-prefix=MIPS
+# RUN: llvm-mc -filetype=obj -triple mips -mcpu=mips32r2 %s -o - \
+# RUN:   | llvm-objdump -d -r - | FileCheck %s --check-prefix=MIPS
+# RUN: llvm-mc -filetype=obj -triple mips -mcpu=mips3 %s -o - \
+# RUN:   | llvm-objdump -d -r - | FileCheck %s --check-prefix=MIPS
+# RUN: llvm-mc -filetype=obj -triple mips -mcpu=mips64 %s -o - \
+# RUN:   | llvm-objdump -d -r - | FileCheck %s --check-prefix=MIPS
+# RUN: llvm-mc -filetype=obj -triple mips -mcpu=mips64r2 %s -o - \
+# RUN:   | llvm-objdump -d -r - | FileCheck %s --check-prefix=MIPS
+# RUN: llvm-mc -filetype=obj -triple mips -mcpu=mips32r6 %s -o - \
+# RUN:   | llvm-objdump -d -r - | FileCheck %s --check-prefix=MIPSR6
+# RUN: llvm-mc -filetype=obj -triple mips -mcpu=mips64r6 %s -o - \
+# RUN:   | llvm-objdump -d -r - | FileCheck %s --check-prefix=MIPSR6
+# RUN: llvm-mc -filetype=obj -triple mips -mcpu=mips32r2 -mattr=+micromips %s -o - \
+# RUN:   | llvm-objdump -d -r - | FileCheck %s --check-prefix=MICROMIPSR2
+# RUN: llvm-mc -filetype=obj -triple mips -mcpu=mips32r6 -mattr=+micromips %s -o - \
+# RUN:   | llvm-objdump -d -r - | FileCheck %s --check-prefix=MICROMIPSR6
+
+# MIPS:         0:  e0 6c 00 00    sc   $12, 0($3)
+# MIPSR6:       0:  7c 6c 00 26    sc   $12, 0($3)
+# MICROMIPS:    0:  61 83 b0 00    sc   $12, 0($3)
+sc $12, 0($3)
+
+# MIPS:         4:  e0 6c 00 04    sc   $12, 4($3)
+# MIPSR6:       4:  7c 6c 02 26    sc   $12, 4($3)
+# MICROMIPS:    4:  61 83 b0 04    sc   $12, 4($3)
+sc $12, 4($3)
+
+# MIPS:         8:  3c 01 00 00    lui  $1, 0
+# MIPS:         00000008:  R_MIPS_HI16	some_random_symbol_name
+# MIPS:         c:  e0 2c 00 00    sc   $12, 0($1)
+# MIPS:         0000000c:  R_MIPS_LO16	some_random_symbol_name
+
+# MIPSR6:       8:  3c 01 00 00    aui  $1, $zero, 0
+# MIPSR6:       00000008:  R_MIPS_HI16	some_random_symbol_name
+# MIPSR6:       c:  7c 2c 00 26    sc   $12, 0($1)
+# MIPSR6:       0000000c:  R_MIPS_LO16	some_random_symbol_name
+
+# MICROMIPSR2:  8:  41 a1 00 00    lui  $1, 0
+# MICROMIPSR2:  00000008:  R_MICROMIPS_HI16  some_random_symbol_name
+# MICROMIPSR2:  c:  61 81 b0 00    sc   $12, 0($1)
+# MICROMIPSR2:  0000000c:  R_MICROMIPS_LO16  some_random_symbol_name
+
+# MICROMIPSR6:  8:  3c 01 00 00    lh   $zero, 0($1)
+# MICROMIPSR6:  00000008:  R_MICROMIPS_HI16  some_random_symbol_name
+# MICROMIPSR6:  c:  61 81 b0 00    sc   $12, 0($1)
+# MICROMIPSR6:  0000000c:  R_MICROMIPS_LO16  some_random_symbol_name
+sc $12, some_random_symbol_name