Index: llvm/trunk/lib/Target/ARM/ARMInstrMVE.td =================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrMVE.td +++ llvm/trunk/lib/Target/ARM/ARMInstrMVE.td @@ -2202,6 +2202,15 @@ def MVE_VNEGs16 : MVE_VABSNEG_int<"vneg", "s16", 0b01, 0b1>; def MVE_VNEGs32 : MVE_VABSNEG_int<"vneg", "s32", 0b10, 0b1>; +let Predicates = [HasMVEInt] in { + def : Pat<(v16i8 (vnegq (v16i8 MQPR:$v))), + (v16i8 (MVE_VNEGs8 $v))>; + def : Pat<(v8i16 (vnegq (v8i16 MQPR:$v))), + (v8i16 (MVE_VNEGs16 $v))>; + def : Pat<(v4i32 (vnegq (v4i32 MQPR:$v))), + (v4i32 (MVE_VNEGs32 $v))>; +} + class MVE_VQABSNEG size, bit negate, list pattern=[]> : MVEIntSingleSrc { Index: llvm/trunk/test/CodeGen/Thumb2/mve-neg.ll =================================================================== --- llvm/trunk/test/CodeGen/Thumb2/mve-neg.ll +++ llvm/trunk/test/CodeGen/Thumb2/mve-neg.ll @@ -0,0 +1,32 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s + +define arm_aapcs_vfpcc <16 x i8> @neg_v16i8(<16 x i8> %s1) { +; CHECK-LABEL: neg_v16i8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vneg.s8 q0, q0 +; CHECK-NEXT: bx lr +entry: + %0 = sub nsw <16 x i8> zeroinitializer, %s1 + ret <16 x i8> %0 +} + +define arm_aapcs_vfpcc <8 x i16> @neg_v8i16(<8 x i16> %s1) { +; CHECK-LABEL: neg_v8i16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vneg.s16 q0, q0 +; CHECK-NEXT: bx lr +entry: + %0 = sub nsw <8 x i16> zeroinitializer, %s1 + ret <8 x i16> %0 +} + +define arm_aapcs_vfpcc <4 x i32> @neg_v4i32(<4 x i32> %s1) { +; CHECK-LABEL: neg_v4i32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vneg.s32 q0, q0 +; CHECK-NEXT: bx lr +entry: + %0 = sub nsw <4 x i32> zeroinitializer, %s1 + ret <4 x i32> %0 +}