Index: llvm/lib/Target/PowerPC/PPC.td =================================================================== --- llvm/lib/Target/PowerPC/PPC.td +++ llvm/lib/Target/PowerPC/PPC.td @@ -164,11 +164,17 @@ "Enable Hardware Transactional Memory instructions">; def FeatureMFTB : SubtargetFeature<"", "FeatureMFTB", "true", "Implement mftb using the mfspr instruction">; -def FeaturePPCPreRASched: - SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true", +def FeaturePreRASched : + SubtargetFeature<"use-prera-sched", "UsePreRASched", "true", + "Schedule before register allocation">; +def FeaturePostRASched : + SubtargetFeature<"use-postra-sched", "UsePostRASched", "true", + "Schedule again after register allocation">; +def FeaturePPCPreRASchedStrategy: + SubtargetFeature<"ppc-prera-sched-strategy", "UsePPCPreRASchedStrategy", "true", "Use PowerPC pre-RA scheduling strategy">; -def FeaturePPCPostRASched: - SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true", +def FeaturePPCPostRASchedStrategy: + SubtargetFeature<"ppc-postra-sched-strategy", "UsePPCPostRASchedStrategy", "true", "Use PowerPC post-RA scheduling strategy">; def FeatureFloat128 : SubtargetFeature<"float128", "HasFloat128", "true", @@ -228,7 +234,8 @@ FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit /*, Feature64BitRegs */, FeatureBPERMD, FeatureExtDiv, - FeatureMFTB, DeprecatedDST, FeatureTwoConstNR]; + FeatureMFTB, DeprecatedDST, FeatureTwoConstNR, + FeaturePreRASched, FeaturePostRASched]; list Power8SpecificFeatures = [DirectivePwr8, FeatureP8Altivec, FeatureP8Vector, FeatureP8Crypto, FeatureHTM, FeatureDirectMove, FeatureICBT, FeaturePartwordAtomic]; @@ -236,7 +243,8 @@ !listconcat(Power7FeatureList, Power8SpecificFeatures); list Power9SpecificFeatures = [DirectivePwr9, FeatureP9Altivec, FeatureP9Vector, FeatureISA3_0, - FeatureVectorsUseTwoUnits, FeaturePPCPreRASched, FeaturePPCPostRASched]; + FeatureVectorsUseTwoUnits, FeaturePPCPreRASchedStrategy, + FeaturePPCPostRASchedStrategy]; list Power9FeatureList = !listconcat(Power8FeatureList, Power9SpecificFeatures); } @@ -314,79 +322,100 @@ // def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat, - FeatureMFTB]>; + FeatureMFTB, FeaturePreRASched, + FeaturePostRASched]>; def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, FeatureFRES, FeatureFRSQRTE, FeatureICBT, FeatureBookE, - FeatureMSYNC, FeatureMFTB]>; + FeatureMSYNC, FeatureMFTB, + FeaturePreRASched, FeaturePostRASched]>; def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, FeatureFRES, FeatureFRSQRTE, FeatureICBT, FeatureBookE, - FeatureMSYNC, FeatureMFTB]>; -def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>; + FeatureMSYNC, FeatureMFTB, + FeaturePreRASched, FeaturePostRASched]>; +def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU, + FeaturePreRASched, FeaturePostRASched]>; def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU, - FeatureMFTB]>; + FeatureMFTB, FeaturePreRASched, + FeaturePostRASched]>; def : Processor<"603", G3Itineraries, [Directive603, FeatureFRES, FeatureFRSQRTE, - FeatureMFTB]>; + FeatureMFTB, FeaturePreRASched, + FeaturePostRASched]>; def : Processor<"603e", G3Itineraries, [Directive603, FeatureFRES, FeatureFRSQRTE, - FeatureMFTB]>; + FeatureMFTB, FeaturePreRASched, + FeaturePostRASched]>; def : Processor<"603ev", G3Itineraries, [Directive603, FeatureFRES, FeatureFRSQRTE, - FeatureMFTB]>; + FeatureMFTB, FeaturePreRASched, + FeaturePostRASched]>; def : Processor<"604", G3Itineraries, [Directive604, FeatureFRES, FeatureFRSQRTE, - FeatureMFTB]>; + FeatureMFTB, FeaturePreRASched, + FeaturePostRASched]>; def : Processor<"604e", G3Itineraries, [Directive604, FeatureFRES, FeatureFRSQRTE, - FeatureMFTB]>; + FeatureMFTB, FeaturePreRASched, + FeaturePostRASched]>; def : Processor<"620", G3Itineraries, [Directive620, FeatureFRES, FeatureFRSQRTE, - FeatureMFTB]>; + FeatureMFTB, FeaturePreRASched, + FeaturePostRASched]>; def : Processor<"750", G4Itineraries, [Directive750, FeatureFRES, FeatureFRSQRTE, - FeatureMFTB]>; + FeatureMFTB, FeaturePreRASched, + FeaturePostRASched]>; def : Processor<"g3", G3Itineraries, [Directive750, FeatureFRES, FeatureFRSQRTE, - FeatureMFTB]>; + FeatureMFTB, FeaturePreRASched, + FeaturePostRASched]>; def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec, FeatureFRES, FeatureFRSQRTE, - FeatureMFTB]>; + FeatureMFTB, FeaturePreRASched, + FeaturePostRASched]>; def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec, FeatureFRES, FeatureFRSQRTE, - FeatureMFTB]>; + FeatureMFTB, FeaturePreRASched, + FeaturePostRASched]>; def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, FeatureFRES, FeatureFRSQRTE, - FeatureMFTB]>; + FeatureMFTB, FeaturePreRASched, + FeaturePostRASched]>; def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, FeatureFRES, FeatureFRSQRTE, - FeatureMFTB]>; + FeatureMFTB, FeaturePreRASched, + FeaturePostRASched]>; def : ProcessorModel<"970", G5Model, [Directive970, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, Feature64Bit /*, Feature64BitRegs */, - FeatureMFTB]>; + FeatureMFTB, FeaturePreRASched, FeaturePostRASched]>; def : ProcessorModel<"g5", G5Model, [Directive970, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, FeatureFRES, FeatureFRSQRTE, Feature64Bit /*, Feature64BitRegs */, - FeatureMFTB, DeprecatedDST]>; + FeatureMFTB, DeprecatedDST, + FeaturePreRASched, FeaturePostRASched]>; def : ProcessorModel<"e500", PPCE500Model, [DirectiveE500, FeatureICBT, FeatureBookE, - FeatureISEL, FeatureMFTB]>; + FeatureISEL, FeatureMFTB, + FeaturePreRASched, FeaturePostRASched]>; def : ProcessorModel<"e500mc", PPCE500mcModel, [DirectiveE500mc, FeatureSTFIWX, FeatureICBT, FeatureBookE, - FeatureISEL, FeatureMFTB]>; + FeatureISEL, FeatureMFTB, + FeaturePreRASched, FeaturePostRASched]>; def : ProcessorModel<"e5500", PPCE5500Model, [DirectiveE5500, FeatureMFOCRF, Feature64Bit, FeatureSTFIWX, FeatureICBT, FeatureBookE, - FeatureISEL, FeatureMFTB]>; + FeatureISEL, FeatureMFTB, + FeaturePreRASched, FeaturePostRASched]>; def : ProcessorModel<"a2", PPCA2Model, [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, @@ -394,7 +423,8 @@ FeatureSTFIWX, FeatureLFIWAX, FeatureFPRND, FeatureFPCVT, FeatureISEL, FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX, - Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>; + Feature64Bit /*, Feature64BitRegs */, FeatureMFTB, + FeaturePreRASched, FeaturePostRASched]>; def : ProcessorModel<"a2q", PPCA2Model, [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, @@ -403,54 +433,62 @@ FeatureFPRND, FeatureFPCVT, FeatureISEL, FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit /*, Feature64BitRegs */, FeatureQPX, - FeatureMFTB]>; + FeatureMFTB, FeaturePreRASched, FeaturePostRASched]>; def : ProcessorModel<"pwr3", G5Model, [DirectivePwr3, FeatureAltivec, FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, - FeatureSTFIWX, Feature64Bit]>; + FeatureSTFIWX, Feature64Bit, FeaturePreRASched, + FeaturePostRASched]>; def : ProcessorModel<"pwr4", G5Model, [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, - FeatureSTFIWX, Feature64Bit, FeatureMFTB]>; + FeatureSTFIWX, Feature64Bit, FeatureMFTB, + FeaturePreRASched, FeaturePostRASched]>; def : ProcessorModel<"pwr5", G5Model, [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureSTFIWX, Feature64Bit, - FeatureMFTB, DeprecatedDST]>; + FeatureMFTB, DeprecatedDST, FeaturePreRASched, + FeaturePostRASched]>; def : ProcessorModel<"pwr5x", G5Model, [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureSTFIWX, FeatureFPRND, Feature64Bit, - FeatureMFTB, DeprecatedDST]>; + FeatureMFTB, DeprecatedDST, FeaturePreRASched, + FeaturePostRASched]>; def : ProcessorModel<"pwr6", G5Model, [DirectivePwr6, FeatureAltivec, FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, FeatureFPRND, Feature64Bit /*, Feature64BitRegs */, - FeatureMFTB, DeprecatedDST]>; + FeatureMFTB, DeprecatedDST, FeaturePreRASched, + FeaturePostRASched]>; def : ProcessorModel<"pwr6x", G5Model, [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, FeatureFPRND, Feature64Bit, - FeatureMFTB, DeprecatedDST]>; + FeatureMFTB, DeprecatedDST, FeaturePreRASched, + FeaturePostRASched]>; def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>; def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>; def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.Power9FeatureList>; def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat, - FeatureMFTB]>; + FeatureMFTB, FeaturePreRASched, + FeaturePostRASched]>; def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat, - FeatureMFTB]>; + FeatureMFTB, FeaturePreRASched, + FeaturePostRASched]>; def : ProcessorModel<"ppc64", G5Model, [Directive64, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, Feature64Bit /*, Feature64BitRegs */, - FeatureMFTB]>; + FeatureMFTB, FeaturePreRASched, FeaturePostRASched]>; def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.Power8FeatureList>; //===----------------------------------------------------------------------===// Index: llvm/lib/Target/PowerPC/PPCSubtarget.h =================================================================== --- llvm/lib/Target/PowerPC/PPCSubtarget.h +++ llvm/lib/Target/PowerPC/PPCSubtarget.h @@ -138,6 +138,8 @@ bool VectorsUseTwoUnits; bool UsePPCPreRASchedStrategy; bool UsePPCPostRASchedStrategy; + bool UsePreRASched; + bool UsePostRASched; POPCNTDKind HasPOPCNTD; Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp =================================================================== --- llvm/lib/Target/PowerPC/PPCSubtarget.cpp +++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp @@ -115,6 +115,8 @@ VectorsUseTwoUnits = false; UsePPCPreRASchedStrategy = false; UsePPCPostRASchedStrategy = false; + UsePreRASched = false; + UsePostRASched = false; HasPOPCNTD = POPCNTD_Unavailable; } @@ -186,7 +188,7 @@ return false; } -bool PPCSubtarget::enableMachineScheduler() const { return true; } +bool PPCSubtarget::enableMachineScheduler() const { return UsePreRASched; } bool PPCSubtarget::enableMachinePipeliner() const { return (DarwinDirective == PPC::DIR_PWR9) && EnableMachinePipeliner; @@ -195,7 +197,7 @@ bool PPCSubtarget::useDFAforSMS() const { return false; } // This overrides the PostRAScheduler bit in the SchedModel for each CPU. -bool PPCSubtarget::enablePostRAScheduler() const { return true; } +bool PPCSubtarget::enablePostRAScheduler() const { return UsePostRASched; } PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const { return TargetSubtargetInfo::ANTIDEP_ALL; Index: llvm/test/CodeGen/PowerPC/scheduling-mem-dependency.ll =================================================================== --- llvm/test/CodeGen/PowerPC/scheduling-mem-dependency.ll +++ llvm/test/CodeGen/PowerPC/scheduling-mem-dependency.ll @@ -1,5 +1,8 @@ ; REQUIRES: asserts ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=-use-prera-sched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK-NOPRERA-SCHED +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=-use-postra-sched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK-NOPOSTRA-SCHED +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=-use-postra-sched -mattr=-use-prera-sched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK-NO-SCHED define i64 @store_disjoint_memory(i64* nocapture %P, i64 %v) { entry: @@ -16,4 +19,10 @@ %arrayidx1 = getelementptr inbounds i64, i64* %P, i64 2 store i64 %v, i64* %arrayidx1 ret i64 %v +; CHECK-NOPRERA-SCHED-NOT: ScheduleDAGMILive::schedule starting +; CHECK-NOPRERA-SCHED: ScheduleDAGMI::schedule starting +; CHECK-NOPOSTRA-SCHED: ScheduleDAGMILive::schedule starting +; CHECK-NOPOSTRA-SCHED-NOT: ScheduleDAGMI::schedule starting +; CHECK-NO-SCHED-NOT: ScheduleDAGMILive::schedule starting +; CHECK-NO-SCHED-NOT: ScheduleDAGMI::schedule starting }