[NFC][PowerPC] Add the feature control for PreRA and PostRA scheduler

[steven.zhang]

Summary

We may need to disable the Pre-RA or Post-RA scheduler. Add the feature control for it.

[hfinkel]

We may need to disable the Pre-RA or Post-RA scheduler. Add the feature control for it.

Why? If this is just for debugging, then my thought is: We do have cl::opts that control this, and if we want this on a per-function basis, then this is not a ppc-specific problem and should introduce some target-independent attribute.

[hfinkel]

In D64198#1570496, @hfinkel wrote:

We may need to disable the Pre-RA or Post-RA scheduler. Add the feature control for it.

Why? If this is just for debugging, then my thought is: We do have cl::opts that control this, and if we want this on a per-function basis, then this is not a ppc-specific problem and should introduce some target-independent attribute.

(oops, I didn't really mean to mark this as accepted)

[steven.zhang]

I am sorry that, I didn't put enough background for this change. The idea is not for per-function basis. We have the pre-ra scheduler and post-ra scheduler you know, and they should be able to be configured for different CPU processor. (Some cpu might need the post-ra scheduler, and some didn't, though we enable it for all cpus on PowerPC now) This is done by adding features and included by different cpu. And it also gives us the ability to turn on/off the specific scheduler.

[jsji]

As Hal mentioned, enable-misched and enable-post-misched should be able to turn on/off the pre-ra/post-ra scheduler.
Regarding to different subtarget (cpu), why we need to turn on/off with feature at runtime? Shouldn't that be configured in code?

yeah, per function control might be more useful here.

[steven.zhang]

In D64198#1570920, @jsji wrote:

As Hal mentioned, enable-misched and enable-post-misched should be able to turn on/off the pre-ra/post-ra scheduler.
Regarding to different subtarget (cpu), why we need to turn on/off with feature at runtime? Shouldn't that be configured in code?

yeah, per function control might be more useful here.

Ah, I didn't realize the option you mentioned, and yes, they can turn on/off the scheduler target independent for all cpu.
But if we want to turn on/off the scheduler for specific cpu, we have to add the feature for it. And the feature supports to be configured at runtime.

I am ok to abandon this patch as I have got the options to turn on/off the scheduler for PowerPC. However, I didn't see the harm to add this feature for PowerPC, as, it is the right way if we want to custom the scheduler for different cpu model. Any thoughts ?

[hfinkel]

In D64198#1570936, @steven.zhang wrote:

In D64198#1570920, @jsji wrote:

As Hal mentioned, enable-misched and enable-post-misched should be able to turn on/off the pre-ra/post-ra scheduler.
Regarding to different subtarget (cpu), why we need to turn on/off with feature at runtime? Shouldn't that be configured in code?

yeah, per function control might be more useful here.

Ah, I didn't realize the option you mentioned, and yes, they can turn on/off the scheduler target independent for all cpu.
But if we want to turn on/off the scheduler for specific cpu, we have to add the feature for it. And the feature supports to be configured at runtime.

I am ok to abandon this patch as I have got the options to turn on/off the scheduler for PowerPC. However, I didn't see the harm to add this feature for PowerPC, as, it is the right way if we want to custom the scheduler for different cpu model. Any thoughts ?

I understand conventional wisdom is that post-RA scheduling is mostly useful for simpler cores, but at least as of the pwr8, it provided a noticeable performance enhancement even for the server-class cores as well. As a result, it seemed to benefit all PowerPC cores we had tested, and so we just had it on for nearly everything. Have you come across cores for which we want it off?

[steven.zhang]

No. I didn't have the requirement to custom cpu for the scheduler yet. I will abandon this patch and we can add the feature if we indeed find some cases that need it.

llvm/lib/Target/PowerPC/PPC.td

SubtargetFeature<"invariant-function-descriptors",
                    "HasInvariantFunctionDescriptors", "true",
                    "Assume function descriptors are invariant">;
 def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true",
                                        "Always use indirect calls">;
 def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true",
                                   "Enable Hardware Transactional Memory instructions">;
 def FeatureMFTB   : SubtargetFeature<"", "FeatureMFTB", "true",
                                         "Implement mftb using the mfspr instruction">;
-def FeaturePPCPreRASched:
-  SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true",
+def FeaturePreRASched :
+  SubtargetFeature<"use-prera-sched", "UsePreRASched", "true",
+                   "Schedule before register allocation">;
+def FeaturePostRASched :
+  SubtargetFeature<"use-postra-sched", "UsePostRASched", "true",
+                   "Schedule again after register allocation">;
+def FeaturePPCPreRASchedStrategy:
+  SubtargetFeature<"ppc-prera-sched-strategy", "UsePPCPreRASchedStrategy", "true",
                    "Use PowerPC pre-RA scheduling strategy">;
-def FeaturePPCPostRASched:
-  SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true",
+def FeaturePPCPostRASchedStrategy:
+  SubtargetFeature<"ppc-postra-sched-strategy", "UsePPCPostRASchedStrategy", "true",
                    "Use PowerPC post-RA scheduling strategy">;
 def FeatureFloat128 :
   SubtargetFeature<"float128", "HasFloat128", "true",
                    "Enable the __float128 data type for IEEE-754R Binary128.",
                    [FeatureVSX]>;
 def FeaturePOPCNTD   : SubtargetFeature<"popcntd","HasPOPCNTD",
                                         "POPCNTD_Fast",
                                         "Enable the popcnt[dw] instructions">;
list<SubtargetFeature> Power7FeatureList =
       [DirectivePwr7, FeatureAltivec, FeatureVSX,
        FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
        FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
        FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
        FeatureFPRND, FeatureFPCVT, FeatureISEL,
        FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX,
        Feature64Bit /*, Feature64BitRegs */,
        FeatureBPERMD, FeatureExtDiv,
-       FeatureMFTB, DeprecatedDST, FeatureTwoConstNR];
+       FeatureMFTB, DeprecatedDST, FeatureTwoConstNR,
+       FeaturePreRASched, FeaturePostRASched];
   list<SubtargetFeature> Power8SpecificFeatures =
       [DirectivePwr8, FeatureP8Altivec, FeatureP8Vector, FeatureP8Crypto,
        FeatureHTM, FeatureDirectMove, FeatureICBT, FeaturePartwordAtomic];
   list<SubtargetFeature> Power8FeatureList =
       !listconcat(Power7FeatureList, Power8SpecificFeatures);
   list<SubtargetFeature> Power9SpecificFeatures =
       [DirectivePwr9, FeatureP9Altivec, FeatureP9Vector, FeatureISA3_0,
-       FeatureVectorsUseTwoUnits, FeaturePPCPreRASched, FeaturePPCPostRASched];
+       FeatureVectorsUseTwoUnits, FeaturePPCPreRASchedStrategy,
+       FeaturePPCPostRASchedStrategy];
   list<SubtargetFeature> Power9FeatureList =
       !listconcat(Power8FeatureList, Power9SpecificFeatures);
 }
 
 // Note: Future features to add when support is extended to more
 // recent ISA levels:
 //
 // DFP          p6, p6x, p7        decimal floating-point instructions

 include "PPCRegisterInfo.td"
 include "PPCSchedule.td"
 
 //===----------------------------------------------------------------------===//
 // PowerPC processors supported.
 //
 
 def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat,
-                                           FeatureMFTB]>;
+                                           FeatureMFTB, FeaturePreRASched,
+                                           FeaturePostRASched]>;
 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
                                           FeatureFRES, FeatureFRSQRTE,
                                           FeatureICBT, FeatureBookE,
-                                          FeatureMSYNC, FeatureMFTB]>;
+                                          FeatureMSYNC, FeatureMFTB,
+                                          FeaturePreRASched, FeaturePostRASched]>;
 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
                                           FeatureFRES, FeatureFRSQRTE,
                                           FeatureICBT, FeatureBookE,
-                                          FeatureMSYNC, FeatureMFTB]>;
-def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>;
+                                          FeatureMSYNC, FeatureMFTB,
+                                          FeaturePreRASched, FeaturePostRASched]>;
+def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU,
+                                       FeaturePreRASched, FeaturePostRASched]>;
 def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU,
-                                       FeatureMFTB]>;
+                                       FeatureMFTB, FeaturePreRASched,
+                                       FeaturePostRASched]>;
 def : Processor<"603", G3Itineraries, [Directive603,
                                        FeatureFRES, FeatureFRSQRTE,
-                                       FeatureMFTB]>;
+                                       FeatureMFTB, FeaturePreRASched,
+                                       FeaturePostRASched]>;
 def : Processor<"603e", G3Itineraries, [Directive603,
                                         FeatureFRES, FeatureFRSQRTE,
-                                        FeatureMFTB]>;
+                                        FeatureMFTB, FeaturePreRASched,
+                                        FeaturePostRASched]>;
 def : Processor<"603ev", G3Itineraries, [Directive603,
                                          FeatureFRES, FeatureFRSQRTE,
-                                         FeatureMFTB]>;
+                                         FeatureMFTB, FeaturePreRASched,
+                                         FeaturePostRASched]>;
 def : Processor<"604", G3Itineraries, [Directive604,
                                        FeatureFRES, FeatureFRSQRTE,
-                                       FeatureMFTB]>;
+                                       FeatureMFTB, FeaturePreRASched,
+                                       FeaturePostRASched]>;
 def : Processor<"604e", G3Itineraries, [Directive604,
                                         FeatureFRES, FeatureFRSQRTE,
-                                        FeatureMFTB]>;
+                                        FeatureMFTB, FeaturePreRASched,
+                                        FeaturePostRASched]>;
 def : Processor<"620", G3Itineraries, [Directive620,
                                        FeatureFRES, FeatureFRSQRTE,
-                                       FeatureMFTB]>;
+                                       FeatureMFTB, FeaturePreRASched,
+                                       FeaturePostRASched]>;
 def : Processor<"750", G4Itineraries, [Directive750,
                                        FeatureFRES, FeatureFRSQRTE,
-                                       FeatureMFTB]>;
+                                       FeatureMFTB, FeaturePreRASched,
+                                       FeaturePostRASched]>;
 def : Processor<"g3", G3Itineraries, [Directive750,
                                       FeatureFRES, FeatureFRSQRTE,
-                                      FeatureMFTB]>;
+                                      FeatureMFTB, FeaturePreRASched,
+                                      FeaturePostRASched]>;
 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
                                         FeatureFRES, FeatureFRSQRTE,
-                                        FeatureMFTB]>;
+                                        FeatureMFTB, FeaturePreRASched,
+                                        FeaturePostRASched]>;
 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
                                       FeatureFRES, FeatureFRSQRTE,
-                                      FeatureMFTB]>;
+                                      FeatureMFTB, FeaturePreRASched,
+                                      FeaturePostRASched]>;
 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
                                             FeatureFRES, FeatureFRSQRTE,
-                                            FeatureMFTB]>;
+                                            FeatureMFTB, FeaturePreRASched,
+                                            FeaturePostRASched]>;
 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
                                            FeatureFRES, FeatureFRSQRTE,
-                                           FeatureMFTB]>;
+                                           FeatureMFTB, FeaturePreRASched,
+                                           FeaturePostRASched]>;
 
 def : ProcessorModel<"970", G5Model,
                   [Directive970, FeatureAltivec,
                    FeatureMFOCRF, FeatureFSqrt,
                    FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
                    Feature64Bit /*, Feature64BitRegs */,
-                   FeatureMFTB]>;
+                   FeatureMFTB, FeaturePreRASched, FeaturePostRASched]>;
 def : ProcessorModel<"g5", G5Model,
                   [Directive970, FeatureAltivec,
                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
                    FeatureFRES, FeatureFRSQRTE,
                    Feature64Bit /*, Feature64BitRegs */,
-                   FeatureMFTB, DeprecatedDST]>;
+                   FeatureMFTB, DeprecatedDST,
+                   FeaturePreRASched, FeaturePostRASched]>;
 def : ProcessorModel<"e500", PPCE500Model,
                   [DirectiveE500,
                    FeatureICBT, FeatureBookE,
-                   FeatureISEL, FeatureMFTB]>;
+                   FeatureISEL, FeatureMFTB,
+                   FeaturePreRASched, FeaturePostRASched]>;
 def : ProcessorModel<"e500mc", PPCE500mcModel,
                   [DirectiveE500mc,
                    FeatureSTFIWX, FeatureICBT, FeatureBookE,
-                   FeatureISEL, FeatureMFTB]>;
+                   FeatureISEL, FeatureMFTB,
+                   FeaturePreRASched, FeaturePostRASched]>;
 def : ProcessorModel<"e5500", PPCE5500Model,
                   [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
                    FeatureSTFIWX, FeatureICBT, FeatureBookE,
-                   FeatureISEL, FeatureMFTB]>;
+                   FeatureISEL, FeatureMFTB,
+                   FeaturePreRASched, FeaturePostRASched]>;
 def : ProcessorModel<"a2", PPCA2Model,
                   [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
                    FeatureSTFIWX, FeatureLFIWAX,
                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
                    FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
-                   Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>;
+                   Feature64Bit /*, Feature64BitRegs */, FeatureMFTB,
+                   FeaturePreRASched, FeaturePostRASched]>;
 def : ProcessorModel<"a2q", PPCA2Model,
                   [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
                    FeatureSTFIWX, FeatureLFIWAX,
                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
                    FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
                    Feature64Bit /*, Feature64BitRegs */, FeatureQPX,
-                   FeatureMFTB]>;
+                   FeatureMFTB, FeaturePreRASched, FeaturePostRASched]>;
 def : ProcessorModel<"pwr3", G5Model,
                   [DirectivePwr3, FeatureAltivec,
                    FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
-                   FeatureSTFIWX, Feature64Bit]>;
+                   FeatureSTFIWX, Feature64Bit, FeaturePreRASched,
+                   FeaturePostRASched]>;
 def : ProcessorModel<"pwr4", G5Model,
                   [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
                    FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
-                   FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;
+                   FeatureSTFIWX, Feature64Bit, FeatureMFTB,
+                   FeaturePreRASched, FeaturePostRASched]>;
 def : ProcessorModel<"pwr5", G5Model,
                   [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
                    FeatureFSqrt, FeatureFRE, FeatureFRES,
                    FeatureFRSQRTE, FeatureFRSQRTES,
                    FeatureSTFIWX, Feature64Bit,
-                   FeatureMFTB, DeprecatedDST]>;
+                   FeatureMFTB, DeprecatedDST, FeaturePreRASched,
+                   FeaturePostRASched]>;
 def : ProcessorModel<"pwr5x", G5Model,
                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
                    FeatureFSqrt, FeatureFRE, FeatureFRES,
                    FeatureFRSQRTE, FeatureFRSQRTES,
                    FeatureSTFIWX, FeatureFPRND, Feature64Bit,
-                   FeatureMFTB, DeprecatedDST]>;
+                   FeatureMFTB, DeprecatedDST, FeaturePreRASched,
+                   FeaturePostRASched]>;
 def : ProcessorModel<"pwr6", G5Model,
                   [DirectivePwr6, FeatureAltivec,
                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
                    FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
-                   FeatureMFTB, DeprecatedDST]>;
+                   FeatureMFTB, DeprecatedDST, FeaturePreRASched,
+                   FeaturePostRASched]>;
 def : ProcessorModel<"pwr6x", G5Model,
                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
                    FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
                    FeatureFPRND, Feature64Bit,
-                   FeatureMFTB, DeprecatedDST]>;
+                   FeatureMFTB, DeprecatedDST, FeaturePreRASched,
+                   FeaturePostRASched]>;
 def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>;
 def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>;
 def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.Power9FeatureList>;
 def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat,
-                                       FeatureMFTB]>;
+                                       FeatureMFTB, FeaturePreRASched,
+                                       FeaturePostRASched]>;
 def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat,
-                                         FeatureMFTB]>;
+                                         FeatureMFTB, FeaturePreRASched,
+                                         FeaturePostRASched]>;
 def : ProcessorModel<"ppc64", G5Model,
                   [Directive64, FeatureAltivec,
                    FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
                    FeatureFRSQRTE, FeatureSTFIWX,
                    Feature64Bit /*, Feature64BitRegs */,
-                   FeatureMFTB]>;
+                   FeatureMFTB, FeaturePreRASched, FeaturePostRASched]>;
 def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.Power8FeatureList>;
 
 //===----------------------------------------------------------------------===//
 // Calling Conventions
 //===----------------------------------------------------------------------===//
 
 include "PPCCallingConv.td"
 

llvm/lib/Target/PowerPC/PPCSubtarget.h

protected:
   bool HasHTM;
   bool HasFloat128;
   bool IsISA3_0;
   bool UseLongCalls;
   bool SecurePlt;
   bool VectorsUseTwoUnits;
   bool UsePPCPreRASchedStrategy;
   bool UsePPCPostRASchedStrategy;
+  bool UsePreRASched;
+  bool UsePostRASched;
 
   POPCNTDKind HasPOPCNTD;
 
   /// When targeting QPX running a stock PPC64 Linux kernel where the stack
   /// alignment has not been changed, we need to keep the 16-byte alignment
   /// of the stack.
   bool IsQPXStackUnaligned;
 

llvm/lib/Target/PowerPC/PPCSubtarget.cpp

void PPCSubtarget::initializeEnvironment() {
   HasHTM = false;
   HasFloat128 = false;
   IsISA3_0 = false;
   UseLongCalls = false;
   SecurePlt = false;
   VectorsUseTwoUnits = false;
   UsePPCPreRASchedStrategy = false;
   UsePPCPostRASchedStrategy = false;
+  UsePreRASched = false;
+  UsePostRASched = false;
 
   HasPOPCNTD = POPCNTD_Unavailable;
 }
 
 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
   // Determine default and user specified characteristics
   std::string CPUName = CPU;
   if (CPUName.empty() || CPU == "generic") {
bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV) const {
   // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
   // the section that is being relocated. This means we have to use o load even
   // for GVs that are known to be local to the dso.
   if (GV->isDeclarationForLinker() || GV->hasCommonLinkage())
     return true;
   return false;
 }
 
-bool PPCSubtarget::enableMachineScheduler() const { return true; }
+bool PPCSubtarget::enableMachineScheduler() const { return UsePreRASched; }
 
 bool PPCSubtarget::enableMachinePipeliner() const {
   return (DarwinDirective == PPC::DIR_PWR9) && EnableMachinePipeliner;
 }
 
 bool PPCSubtarget::useDFAforSMS() const { return false; }
 
 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
-bool PPCSubtarget::enablePostRAScheduler() const { return true; }
+bool PPCSubtarget::enablePostRAScheduler() const { return UsePostRASched; }
 
 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
   return TargetSubtargetInfo::ANTIDEP_ALL;
 }
 
 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
   CriticalPathRCs.clear();
   CriticalPathRCs.push_back(isPPC64() ?

llvm/test/CodeGen/PowerPC/scheduling-mem-dependency.ll

 ; REQUIRES: asserts
 ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=-use-prera-sched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK-NOPRERA-SCHED
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=-use-postra-sched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK-NOPOSTRA-SCHED
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=-use-postra-sched -mattr=-use-prera-sched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK-NO-SCHED
 
 define i64 @store_disjoint_memory(i64* nocapture %P, i64 %v) {
 entry:
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-LABEL: store_disjoint_memory:%bb.0
 ; CHECK:SU(2):   STD renamable $x4, 24, renamable $x5 :: (store 8 into %ir.arrayidx)
 ; CHECK-NOT: Successors:
 ; CHECK-NOT:    SU(3): Ord  Latency=0 Memory
 ; CHECK:SU(3):   STD renamable $x4, 16, renamable $x5 :: (store 8 into %ir.arrayidx1)
 ; CHECK: Predecessors:
 ; CHECK-NOT:    SU(2): Ord  Latency=0 Memory
   %arrayidx = getelementptr inbounds i64, i64* %P, i64 3
   store i64 %v, i64* %arrayidx
   %arrayidx1 = getelementptr inbounds i64, i64* %P, i64 2
   store i64 %v, i64* %arrayidx1
   ret i64 %v
+; CHECK-NOPRERA-SCHED-NOT: ScheduleDAGMILive::schedule starting 
+; CHECK-NOPRERA-SCHED: ScheduleDAGMI::schedule starting
+; CHECK-NOPOSTRA-SCHED: ScheduleDAGMILive::schedule starting 
+; CHECK-NOPOSTRA-SCHED-NOT: ScheduleDAGMI::schedule starting 
+; CHECK-NO-SCHED-NOT: ScheduleDAGMILive::schedule starting 
+; CHECK-NO-SCHED-NOT: ScheduleDAGMI::schedule starting 
 }