diff --git a/llvm/include/llvm/CodeGen/ExpandISelPseudos.h b/llvm/include/llvm/CodeGen/ExpandISelPseudos.h new file mode 100644 --- /dev/null +++ b/llvm/include/llvm/CodeGen/ExpandISelPseudos.h @@ -0,0 +1,29 @@ +//===-- llvm/CodeGen/ExpandISelPseudos.h ----------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Expand Pseudo-instructions produced by ISel. These are usually to allow +// the expansion to contain control flow, such as a conditional move +// implemented with a conditional branch and a phi, or an atomic operation +// implemented with a loop. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_EXPAND_ISEL_PSEUDOS_H +#define LLVM_CODEGEN_EXPAND_ISEL_PSEUDOS_H + +#include "llvm/CodeGen/PassManager.h" +#include "llvm/IR/PassManager.h" + +namespace llvm { + +struct ExpandISelPseudosPass : PassInfoMixin { + PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &); +}; +} // namespace llvm + +#endif // LLVM_CODEGEN_EXPAND_ISEL_PSEUDOS_H diff --git a/llvm/include/llvm/CodeGen/MIRPrintingPass.h b/llvm/include/llvm/CodeGen/MIRPrintingPass.h new file mode 100644 --- /dev/null +++ b/llvm/include/llvm/CodeGen/MIRPrintingPass.h @@ -0,0 +1,33 @@ +//===- MIRPrintingPass.cpp - Pass that prints out using the MIR format ----===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file descibes the pass that prints out the LLVM module using the MIR +// serialization format. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_MIRPRINTINGPASS_H +#define LLVM_CODEGEN_MIRPRINTINGPASS_H + +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/IR/PassManager.h" +#include "llvm/CodeGen/PassManager.h" +#include "llvm/Support/raw_ostream.h" + +namespace llvm { + +// The MIR Printing pass. +struct MIRPrintingPass : PassInfoMixin { + raw_ostream &OS; + MIRPrintingPass(raw_ostream &OS) : OS(OS){}; + PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &); + PreservedAnalyses run(Module &M, ModuleAnalysisManager &); +}; +} + +#endif // LLVM_CODEGEN_MIRPRINTINGPASS_H diff --git a/llvm/include/llvm/CodeGen/MachineCSE.h b/llvm/include/llvm/CodeGen/MachineCSE.h new file mode 100644 --- /dev/null +++ b/llvm/include/llvm/CodeGen/MachineCSE.h @@ -0,0 +1,28 @@ +//===- MachineCSE.h - Machine Common Subexpression Elimination Pass -----===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This pass performs global common subexpression elimination on machine +// instructions using a scoped hash table based value numbering scheme. It +// must be run while the machine function is still in SSA form. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_MACHINE_CSE_H +#define LLVM_CODEGEN_MACHINE_CSE_H + +#include "llvm/CodeGen/PassManager.h" +#include "llvm/IR/PassManager.h" + +namespace llvm { + +struct MachineCSEPass : PassInfoMixin { + PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &AM); +}; +} // namespace llvm + +#endif // LLVM_CODEGEN_MACHINE_CSE_H diff --git a/llvm/include/llvm/CodeGen/MachineCopyPropagation.h b/llvm/include/llvm/CodeGen/MachineCopyPropagation.h new file mode 100644 --- /dev/null +++ b/llvm/include/llvm/CodeGen/MachineCopyPropagation.h @@ -0,0 +1,56 @@ +//===- MachineCopyPropagation.h - Machine Copy Propagation Pass ---------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This is an extremely simple MachineInstr-level copy propagation pass. +// +// This pass forwards the source of COPYs to the users of their destinations +// when doing so is legal. For example: +// +// %reg1 = COPY %reg0 +// ... +// ... = OP %reg1 +// +// If +// - %reg0 has not been clobbered by the time of the use of %reg1 +// - the register class constraints are satisfied +// - the COPY def is the only value that reaches OP +// then this pass replaces the above with: +// +// %reg1 = COPY %reg0 +// ... +// ... = OP %reg0 +// +// This pass also removes some redundant COPYs. For example: +// +// %R1 = COPY %R0 +// ... // No clobber of %R1 +// %R0 = COPY %R1 <<< Removed +// +// or +// +// %R1 = COPY %R0 +// ... // No clobber of %R0 +// %R1 = COPY %R0 <<< Removed +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_MACHINE_COPY_PROPAGATION_H +#define LLVM_CODEGEN_MACHINE_COPY_PROPAGATION_H + +#include "llvm/CodeGen/PassManager.h" +#include "llvm/IR/PassManager.h" + +namespace llvm { + +// The Machine Copy Propagation pass. +struct MachineCopyPropagationPass : PassInfoMixin { + PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &AM); +}; +} // namespace llvm + +#endif // LLVM_CODEGEN_MACHINE_COPY_PROPAGATION_H diff --git a/llvm/include/llvm/CodeGen/MachineDominators.h b/llvm/include/llvm/CodeGen/MachineDominators.h --- a/llvm/include/llvm/CodeGen/MachineDominators.h +++ b/llvm/include/llvm/CodeGen/MachineDominators.h @@ -19,6 +19,7 @@ #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/PassManager.h" #include "llvm/Support/GenericDomTree.h" #include "llvm/Support/GenericDomTreeConstruction.h" #include @@ -43,7 +44,9 @@ /// DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to /// compute a normal dominator tree. /// -class MachineDominatorTree : public MachineFunctionPass { +class MachineDominatorTree { + friend class MachineDominatorTreeWrapperPass; + friend class MachineDominatorTreeAnalysis; /// Helper structure used to hold all the basic blocks /// involved in the split of a critical edge. struct CriticalEdge { @@ -76,9 +79,6 @@ void applySplitCriticalEdges() const; public: - static char ID; // Pass ID, replacement for typeid - - MachineDominatorTree(); DomTreeBase &getBase() { if (!DT) DT.reset(new DomTreeBase()); @@ -86,8 +86,6 @@ return *DT; } - void getAnalysisUsage(AnalysisUsage &AU) const override; - /// getRoots - Return the root blocks of the current CFG. This may include /// multiple blocks if we are computing post dominators. For forward /// dominators, this will always be a single block (the entry node). @@ -107,8 +105,6 @@ return DT->getRootNode(); } - bool runOnMachineFunction(MachineFunction &F) override; - inline bool dominates(const MachineDomTreeNode* A, const MachineDomTreeNode* B) const { applySplitCriticalEdges(); @@ -221,12 +217,6 @@ return DT->isReachableFromEntry(A); } - void releaseMemory() override; - - void verifyAnalysis() const override; - - void print(raw_ostream &OS, const Module*) const override; - /// Record that the critical edge (FromBB, ToBB) has been /// split with NewBB. /// This is best to use this method instead of directly update the @@ -248,6 +238,44 @@ "A basic block inserted via edge splitting cannot appear twice"); CriticalEdgesToSplit.push_back({FromBB, ToBB, NewBB}); } + + void releaseMemory(); + + void verifyAnalysis() const; +}; + +class MachineDominatorTreeWrapperPass : public MachineFunctionPass { + MachineDominatorTree DT; +public: + static char ID; // Pass ID, replacement for typeid + + MachineDominatorTreeWrapperPass(); + + MachineDominatorTree &getMachineDominatorTree() { return DT; } + const MachineDominatorTree &getMachineDominatorTree() const { return DT; } + + void releaseMemory() override; + + void getAnalysisUsage(AnalysisUsage &AU) const override; + + bool runOnMachineFunction(MachineFunction &F) override; + + void print(raw_ostream &OS, const Module*) const override; + + void verifyAnalysis() const override; +}; + +/// \brief Analysis pass which compute a \c MachineDominatorTree +class MachineDominatorTreeAnalysis : public AnalysisInfoMixin { + friend AnalysisInfoMixin; + + static AnalysisKey Key; +public: + /// \brief Provide the result typedef for this analysis pass. + using Result = MachineDominatorTree; + + /// Run the analysis pass over a function and produce a dominator tree. + MachineDominatorTree run(MachineFunction &MF, MachineFunctionAnalysisManager &AM); }; //===------------------------------------- diff --git a/llvm/include/llvm/CodeGen/MachineModuleInfo.h b/llvm/include/llvm/CodeGen/MachineModuleInfo.h --- a/llvm/include/llvm/CodeGen/MachineModuleInfo.h +++ b/llvm/include/llvm/CodeGen/MachineModuleInfo.h @@ -33,6 +33,7 @@ #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/PointerIntPair.h" +#include "llvm/IR/PassManager.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCSymbol.h" #include "llvm/Pass.h" @@ -74,7 +75,10 @@ /// made by different debugging and exception handling schemes and reformated /// for specific use. /// -class MachineModuleInfo : public ImmutablePass { +class MachineModuleInfo { + friend class MachineModuleInfoWrapperPass; + friend class MachineModuleAnalysis; + const LLVMTargetMachine &TM; /// This is the MCContext used for the entire code generator. @@ -144,11 +148,14 @@ static char ID; // Pass identification, replacement for typeid explicit MachineModuleInfo(const LLVMTargetMachine *TM = nullptr); - ~MachineModuleInfo() override; - // Initialization and Finalization - bool doInitialization(Module &) override; - bool doFinalization(Module &) override; + MachineModuleInfo(MachineModuleInfo &&MMII); + MachineModuleInfo &operator=(MachineModuleInfo &&MMII) = default; + + ~MachineModuleInfo(); + + void initialize(); + void finalize(); const LLVMTargetMachine &getTarget() const { return TM; } @@ -254,6 +261,39 @@ /// \} }; // End class MachineModuleInfo +class MachineModuleInfoWrapperPass : public ImmutablePass { + MachineModuleInfo MMI; + +public: + static char ID; // Pass identification, replacement for typeid + explicit MachineModuleInfoWrapperPass(const LLVMTargetMachine *TM = nullptr); + explicit MachineModuleInfoWrapperPass(const MachineModuleInfo &MMI); + + // Initialization and Finalization + bool doInitialization(Module &) override; + bool doFinalization(Module &) override; + + MachineModuleInfo &getMMI() { return MMI; } + const MachineModuleInfo &getMMI() const { return MMI; } +}; + +/// An analysis that produces \c MachineInfo for a module. +class MachineModuleAnalysis : public AnalysisInfoMixin { + friend AnalysisInfoMixin; + static AnalysisKey Key; + + const LLVMTargetMachine *TM; + +public: + /// Provide the result type for this analysis pass. + using Result = MachineModuleInfo; + + MachineModuleAnalysis(const LLVMTargetMachine *TM) : TM(TM){}; + + /// Run the analysis pass and produce machine module information. + MachineModuleInfo run(Module &M, ModuleAnalysisManager &); +}; + } // end namespace llvm #endif // LLVM_CODEGEN_MACHINEMODULEINFO_H diff --git a/llvm/include/llvm/CodeGen/MachinePipeliner.h b/llvm/include/llvm/CodeGen/MachinePipeliner.h --- a/llvm/include/llvm/CodeGen/MachinePipeliner.h +++ b/llvm/include/llvm/CodeGen/MachinePipeliner.h @@ -91,7 +91,7 @@ AU.addRequired(); AU.addPreserved(); AU.addRequired(); - AU.addRequired(); + AU.addRequired(); AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } diff --git a/llvm/include/llvm/CodeGen/PassManager.h b/llvm/include/llvm/CodeGen/PassManager.h new file mode 100644 --- /dev/null +++ b/llvm/include/llvm/CodeGen/PassManager.h @@ -0,0 +1,133 @@ +//===- PassManager.h ---------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Interface for the pass manager functionality used for CodeGen. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_PASS_MANAGER_H +#define LLVM_CODEGEN_PASS_MANAGER_H + +#include "llvm/Analysis/OptimizationRemarkEmitter.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h" +#include "llvm/IR/PassManager.h" +#include "llvm/IR/PassManagerInternal.h" + +namespace llvm { +using namespace ore; + +/// Convenience typedef for the MachineFunction analysis manager. +using MachineFunctionAnalysisManager = AnalysisManager; +/// Convenience typedef for a pass manager over functions. +using MachineFunctionPassManager = PassManager; + +using MachineFunctionAnalysisManagerFunctionProxy = + InnerAnalysisManagerProxy; + +using FunctionAnalysisManagerMachineFunctionProxy = + OuterAnalysisManagerProxy; + +template +class FunctionToMachineFunctionPassAdaptor + : public PassInfoMixin> { +public: + explicit FunctionToMachineFunctionPassAdaptor(MachineFunctionPassT Pass) + : Pass(std::move(Pass)) {} + + PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM) { + PreservedAnalyses PA = PreservedAnalyses::all(); + + // Do not codegen any 'available_externally' functions at all, they have + // definitions outside the translation unit. + if (F.hasAvailableExternallyLinkage()) + return PA; + + MachineFunctionAnalysisManager &MFAM = + AM.getResult(F) + .getManager(); + + MachineModuleInfo *MMI = + AM.getResult(F) + .getManager() + .getCachedResult(*F.getParent()); + MachineFunction &MF = MMI->getOrCreateMachineFunction(F); + + // Collect the MI count of the function before the pass. + unsigned CountBefore, CountAfter; + + // Check if the user asked for size remarks. + bool ShouldEmitSizeRemarks = + F.getParent()->shouldEmitInstrCountChangedRemark(); + + // If we want size remarks, collect the number of MachineInstrs in our + // MachineFunction before the pass runs. + if (ShouldEmitSizeRemarks) + CountBefore = MF.getInstructionCount(); + + // Request PassInstrumentation from analysis manager, will use it to run + // instrumenting callbacks for the passes later. + // TODO PASS INSTRUMENTATION + // PassInstrumentation PI = AM.getResult(F); + + // if (PI.runBeforePass(Pass, MF)) + // PA = Pass.run(MF, MFAM); + + // PI.runAfterPass(Pass, MF); + + Pass.run(MF, MFAM); + + if (ShouldEmitSizeRemarks) { + // We wanted size remarks. Check if there was a change to the number of + // MachineInstrs in the module. Emit a remark if there was a change. + CountAfter = MF.getInstructionCount(); + if (CountBefore != CountAfter) { + MachineOptimizationRemarkEmitter MORE(MF, nullptr); + MORE.emit([&]() { + int64_t Delta = static_cast(CountAfter) - + static_cast(CountBefore); + MachineOptimizationRemarkAnalysis R("size-info", "FunctionMISizeChange", + MF.getFunction().getSubprogram(), + &MF.front()); + R << NV("Pass", getTypeName()) + << ": Function: " << NV("Function", F.getName()) << ": " + << "MI Instruction count changed from " + << NV("MIInstrsBefore", CountBefore) << " to " + << NV("MIInstrsAfter", CountAfter) + << "; Delta: " << NV("Delta", Delta); + return R; + }); + } + } + + // The FunctionAnalysisManagerModuleProxy is preserved because (we assume) + // the function passes we ran didn't add or remove any functions. + // + // We also preserve all analyses on Machine Functions, because we did all the + // invalidation we needed to do above. + PA.preserveSet>(); + PA.preserve(); + assert(PA.areAllPreserved()); + return PA; + } + +private: + MachineFunctionPassT Pass; +}; + +template +FunctionToMachineFunctionPassAdaptor +createFunctionToMachineFunctionPassAdaptor(MachineFunctionPassT Pass) { + return FunctionToMachineFunctionPassAdaptor( + std::move(Pass)); +} + +} // end namespace llvm + +#endif // LLVM_CODEGEN_PASS_MANAGER_H diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h --- a/llvm/include/llvm/InitializePasses.h +++ b/llvm/include/llvm/InitializePasses.h @@ -137,7 +137,7 @@ void initializeEdgeBundlesPass(PassRegistry&); void initializeEliminateAvailableExternallyLegacyPassPass(PassRegistry&); void initializeEntryExitInstrumenterPass(PassRegistry&); -void initializeExpandISelPseudosPass(PassRegistry&); +void initializeExpandISelPseudosLegacyPassPass(PassRegistry&); void initializeExpandMemCmpPassPass(PassRegistry&); void initializeExpandPostRAPass(PassRegistry&); void initializeExpandReductionsPass(PassRegistry&); @@ -250,20 +250,20 @@ void initializeLowerSwitchPass(PassRegistry&); void initializeLowerTypeTestsPass(PassRegistry&); void initializeMIRCanonicalizerPass(PassRegistry &); -void initializeMIRPrintingPassPass(PassRegistry&); +void initializeMIRPrintingLegacyPassPass(PassRegistry &); void initializeMachineBlockFrequencyInfoPass(PassRegistry&); void initializeMachineBlockPlacementPass(PassRegistry&); void initializeMachineBlockPlacementStatsPass(PassRegistry&); void initializeMachineBranchProbabilityInfoPass(PassRegistry&); -void initializeMachineCSEPass(PassRegistry&); +void initializeMachineCSELegacyPassPass(PassRegistry&); void initializeMachineCombinerPass(PassRegistry&); -void initializeMachineCopyPropagationPass(PassRegistry&); +void initializeMachineCopyPropagationLegacyPassPass(PassRegistry&); void initializeMachineDominanceFrontierPass(PassRegistry&); -void initializeMachineDominatorTreePass(PassRegistry&); +void initializeMachineDominatorTreeWrapperPassPass(PassRegistry&); void initializeMachineFunctionPrinterPassPass(PassRegistry&); void initializeMachineLICMPass(PassRegistry&); void initializeMachineLoopInfoPass(PassRegistry&); -void initializeMachineModuleInfoPass(PassRegistry&); +void initializeMachineModuleInfoWrapperPassPass(PassRegistry &); void initializeMachineOptimizationRemarkEmitterPassPass(PassRegistry&); void initializeMachineOutlinerPass(PassRegistry&); void initializeMachinePipelinerPass(PassRegistry&); diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h --- a/llvm/include/llvm/Target/TargetMachine.h +++ b/llvm/include/llvm/Target/TargetMachine.h @@ -25,7 +25,7 @@ class Function; class GlobalValue; -class MachineModuleInfo; +class MachineModuleInfoWrapperPass; class Mangler; class MCAsmInfo; class MCContext; @@ -284,12 +284,12 @@ /// emitted. Typically this will involve several steps of code generation. /// This method should return true if emission of this file type is not /// supported, or false on success. - /// \p MMI is an optional parameter that, if set to non-nullptr, + /// \p MMIWP is an optional parameter that, if set to non-nullptr, /// will be used to set the MachineModuloInfo for this PM. virtual bool addPassesToEmitFile(PassManagerBase &, raw_pwrite_stream &, raw_pwrite_stream *, CodeGenFileType, bool /*DisableVerify*/ = true, - MachineModuleInfo *MMI = nullptr) { + MachineModuleInfoWrapperPass *MMIWP = nullptr) { return true; } @@ -341,12 +341,12 @@ /// Add passes to the specified pass manager to get the specified file /// emitted. Typically this will involve several steps of code generation. - /// \p MMI is an optional parameter that, if set to non-nullptr, - /// will be used to set the MachineModuloInfofor this PM. + /// \p MMIWP is an optional parameter that, if set to non-nullptr, + /// will be used to set the MachineModuloInfo for this PM. bool addPassesToEmitFile(PassManagerBase &PM, raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut, CodeGenFileType FileType, bool DisableVerify = true, - MachineModuleInfo *MMI = nullptr) override; + MachineModuleInfoWrapperPass *MMIWP = nullptr) override; /// Add passes to the specified pass manager to get machine code emitted with /// the MCJIT. This method returns true if machine code is not supported. It @@ -365,7 +365,7 @@ /// Adds an AsmPrinter pass to the pipeline that prints assembly or /// machine code from the MI representation. bool addAsmPrinter(PassManagerBase &PM, raw_pwrite_stream &Out, - raw_pwrite_stream *DwoOut, CodeGenFileType FileTYpe, + raw_pwrite_stream *DwoOut, CodeGenFileType FileType, MCContext &Context); /// True if the target uses physical regs at Prolog/Epilog insertion diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -247,13 +247,13 @@ void AsmPrinter::getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesAll(); MachineFunctionPass::getAnalysisUsage(AU); - AU.addRequired(); + AU.addRequired(); AU.addRequired(); AU.addRequired(); } bool AsmPrinter::doInitialization(Module &M) { - MMI = getAnalysisIfAvailable(); + MMI = &getAnalysisIfAvailable()->getMMI(); // Initialize TargetLoweringObjectFile. const_cast(getObjFileLowering()) @@ -1021,11 +1021,13 @@ if (isVerbose()) { // Get MachineDominatorTree or compute it on the fly if it's unavailable - MDT = getAnalysisIfAvailable(); - if (!MDT) { + MachineDominatorTreeWrapperPass *MDTWP = getAnalysisIfAvailable(); + if (!MDTWP) { OwnedMDT = make_unique(); OwnedMDT->getBase().recalculate(*MF); MDT = OwnedMDT.get(); + } else { + MDT = &MDTWP->getMachineDominatorTree(); } // Get MachineLoopInfo or compute it on the fly if it's unavailable diff --git a/llvm/lib/CodeGen/BranchFolding.cpp b/llvm/lib/CodeGen/BranchFolding.cpp --- a/llvm/lib/CodeGen/BranchFolding.cpp +++ b/llvm/lib/CodeGen/BranchFolding.cpp @@ -129,9 +129,9 @@ getAnalysis()); BranchFolder Folder(EnableTailMerge, /*CommonHoist=*/true, MBBFreqInfo, getAnalysis()); - return Folder.OptimizeFunction(MF, MF.getSubtarget().getInstrInfo(), - MF.getSubtarget().getRegisterInfo(), - getAnalysisIfAvailable()); + return Folder.OptimizeFunction( + MF, MF.getSubtarget().getInstrInfo(), MF.getSubtarget().getRegisterInfo(), + &getAnalysisIfAvailable()->getMMI()); } BranchFolder::BranchFolder(bool defaultEnableTailMerge, bool CommonHoist, diff --git a/llvm/lib/CodeGen/CMakeLists.txt b/llvm/lib/CodeGen/CMakeLists.txt --- a/llvm/lib/CodeGen/CMakeLists.txt +++ b/llvm/lib/CodeGen/CMakeLists.txt @@ -100,6 +100,7 @@ MacroFusion.cpp OptimizePHIs.cpp ParallelCG.cpp + PassManager.cpp PeepholeOptimizer.cpp PHIElimination.cpp PHIEliminationUtils.cpp diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp --- a/llvm/lib/CodeGen/CodeGen.cpp +++ b/llvm/lib/CodeGen/CodeGen.cpp @@ -30,7 +30,7 @@ initializeEarlyIfConverterPass(Registry); initializeEarlyMachineLICMPass(Registry); initializeEarlyTailDuplicatePass(Registry); - initializeExpandISelPseudosPass(Registry); + initializeExpandISelPseudosLegacyPassPass(Registry); initializeExpandMemCmpPassPass(Registry); initializeExpandPostRAPass(Registry); initializeFEntryInserterPass(Registry); @@ -56,14 +56,14 @@ initializeMachineBlockFrequencyInfoPass(Registry); initializeMachineBlockPlacementPass(Registry); initializeMachineBlockPlacementStatsPass(Registry); - initializeMachineCSEPass(Registry); + initializeMachineCSELegacyPassPass(Registry); initializeMachineCombinerPass(Registry); - initializeMachineCopyPropagationPass(Registry); - initializeMachineDominatorTreePass(Registry); + initializeMachineCopyPropagationLegacyPassPass(Registry); + initializeMachineDominatorTreeWrapperPassPass(Registry); initializeMachineFunctionPrinterPassPass(Registry); initializeMachineLICMPass(Registry); initializeMachineLoopInfoPass(Registry); - initializeMachineModuleInfoPass(Registry); + initializeMachineModuleInfoWrapperPassPass(Registry); initializeMachineOptimizationRemarkEmitterPassPass(Registry); initializeMachineOutlinerPass(Registry); initializeMachinePipelinerPass(Registry); diff --git a/llvm/lib/CodeGen/EarlyIfConversion.cpp b/llvm/lib/CodeGen/EarlyIfConversion.cpp --- a/llvm/lib/CodeGen/EarlyIfConversion.cpp +++ b/llvm/lib/CodeGen/EarlyIfConversion.cpp @@ -626,15 +626,15 @@ INITIALIZE_PASS_BEGIN(EarlyIfConverter, DEBUG_TYPE, "Early If Converter", false, false) INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineTraceMetrics) INITIALIZE_PASS_END(EarlyIfConverter, DEBUG_TYPE, "Early If Converter", false, false) void EarlyIfConverter::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); AU.addRequired(); AU.addPreserved(); AU.addRequired(); @@ -804,7 +804,7 @@ TRI = STI.getRegisterInfo(); SchedModel = STI.getSchedModel(); MRI = &MF.getRegInfo(); - DomTree = &getAnalysis(); + DomTree = &getAnalysis().getMachineDominatorTree(); Loops = getAnalysisIfAvailable(); Traces = &getAnalysis(); MinInstr = nullptr; diff --git a/llvm/lib/CodeGen/ExpandISelPseudos.cpp b/llvm/lib/CodeGen/ExpandISelPseudos.cpp --- a/llvm/lib/CodeGen/ExpandISelPseudos.cpp +++ b/llvm/lib/CodeGen/ExpandISelPseudos.cpp @@ -13,6 +13,8 @@ // //===----------------------------------------------------------------------===// +#include "llvm/CodeGen/ExpandISelPseudos.h" + #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/Passes.h" @@ -24,10 +26,10 @@ #define DEBUG_TYPE "expand-isel-pseudos" namespace { - class ExpandISelPseudos : public MachineFunctionPass { + class ExpandISelPseudosLegacyPass : public MachineFunctionPass { public: static char ID; // Pass identification, replacement for typeid - ExpandISelPseudos() : MachineFunctionPass(ID) {} + ExpandISelPseudosLegacyPass() : MachineFunctionPass(ID) {} private: bool runOnMachineFunction(MachineFunction &MF) override; @@ -38,12 +40,12 @@ }; } // end anonymous namespace -char ExpandISelPseudos::ID = 0; -char &llvm::ExpandISelPseudosID = ExpandISelPseudos::ID; -INITIALIZE_PASS(ExpandISelPseudos, DEBUG_TYPE, +char ExpandISelPseudosLegacyPass::ID = 0; +char &llvm::ExpandISelPseudosID = ExpandISelPseudosLegacyPass::ID; +INITIALIZE_PASS(ExpandISelPseudosLegacyPass, DEBUG_TYPE, "Expand ISel Pseudo-instructions", false, false) -bool ExpandISelPseudos::runOnMachineFunction(MachineFunction &MF) { +static bool expandISelPseudos(MachineFunction &MF) { bool Changed = false; const TargetLowering *TLI = MF.getSubtarget().getTargetLowering(); @@ -68,6 +70,15 @@ } } } - return Changed; } + +PreservedAnalyses +ExpandISelPseudosPass::run(MachineFunction &MF, + MachineFunctionAnalysisManager &) { + return expandISelPseudos(MF) ? PreservedAnalyses::all() : PreservedAnalyses::none(); +} + +bool ExpandISelPseudosLegacyPass::runOnMachineFunction(MachineFunction &MF) { + return expandISelPseudos(MF); +} diff --git a/llvm/lib/CodeGen/GCRootLowering.cpp b/llvm/lib/CodeGen/GCRootLowering.cpp --- a/llvm/lib/CodeGen/GCRootLowering.cpp +++ b/llvm/lib/CodeGen/GCRootLowering.cpp @@ -249,7 +249,7 @@ void GCMachineCodeAnalysis::getAnalysisUsage(AnalysisUsage &AU) const { MachineFunctionPass::getAnalysisUsage(AU); AU.setPreservesAll(); - AU.addRequired(); + AU.addRequired(); AU.addRequired(); } @@ -310,7 +310,7 @@ return false; FI = &getAnalysis().getFunctionInfo(MF.getFunction()); - MMI = &getAnalysis(); + MMI = &getAnalysis().getMMI(); TII = MF.getSubtarget().getInstrInfo(); // Find the size of the stack frame. There may be no correct static frame diff --git a/llvm/lib/CodeGen/IfConversion.cpp b/llvm/lib/CodeGen/IfConversion.cpp --- a/llvm/lib/CodeGen/IfConversion.cpp +++ b/llvm/lib/CodeGen/IfConversion.cpp @@ -356,8 +356,9 @@ if (!PreRegAlloc) { // Tail merge tend to expose more if-conversion opportunities. BranchFolder BF(true, false, MBFI, *MBPI); - BFChange = BF.OptimizeFunction(MF, TII, ST.getRegisterInfo(), - getAnalysisIfAvailable()); + BFChange = BF.OptimizeFunction( + MF, TII, ST.getRegisterInfo(), + &getAnalysisIfAvailable()->getMMI()); } LLVM_DEBUG(dbgs() << "\nIfcvt: function (" << ++FnNum << ") \'" @@ -496,8 +497,9 @@ if (MadeChange && IfCvtBranchFold) { BranchFolder BF(false, false, MBFI, *MBPI); - BF.OptimizeFunction(MF, TII, MF.getSubtarget().getRegisterInfo(), - getAnalysisIfAvailable()); + BF.OptimizeFunction( + MF, TII, MF.getSubtarget().getRegisterInfo(), + &getAnalysisIfAvailable()->getMMI()); } MadeChange |= BFChange; diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp --- a/llvm/lib/CodeGen/InlineSpiller.cpp +++ b/llvm/lib/CodeGen/InlineSpiller.cpp @@ -141,7 +141,7 @@ : MF(mf), LIS(pass.getAnalysis()), LSS(pass.getAnalysis()), AA(&pass.getAnalysis().getAAResults()), - MDT(pass.getAnalysis()), + MDT(pass.getAnalysis().getMachineDominatorTree()), Loops(pass.getAnalysis()), VRM(vrm), MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()), TRI(*mf.getSubtarget().getRegisterInfo()), @@ -197,7 +197,7 @@ : MF(mf), LIS(pass.getAnalysis()), LSS(pass.getAnalysis()), AA(&pass.getAnalysis().getAAResults()), - MDT(pass.getAnalysis()), + MDT(pass.getAnalysis().getMachineDominatorTree()), Loops(pass.getAnalysis()), VRM(vrm), MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()), TRI(*mf.getSubtarget().getRegisterInfo()), diff --git a/llvm/lib/CodeGen/LLVMTargetMachine.cpp b/llvm/lib/CodeGen/LLVMTargetMachine.cpp --- a/llvm/lib/CodeGen/LLVMTargetMachine.cpp +++ b/llvm/lib/CodeGen/LLVMTargetMachine.cpp @@ -96,14 +96,15 @@ /// addPassesToX helper drives creation and initialization of TargetPassConfig. static TargetPassConfig * addPassesToGenerateCode(LLVMTargetMachine &TM, PassManagerBase &PM, - bool DisableVerify, MachineModuleInfo &MMI) { + bool DisableVerify, + MachineModuleInfoWrapperPass &MMIWP) { // Targets may override createPassConfig to provide a target-specific // subclass. TargetPassConfig *PassConfig = TM.createPassConfig(PM); // Set PassConfig options provided by TargetMachine. PassConfig->setDisableVerify(DisableVerify); PM.add(PassConfig); - PM.add(&MMI); + PM.add(&MMIWP); if (PassConfig->addISelPasses()) return nullptr; @@ -186,17 +187,15 @@ return false; } -bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM, - raw_pwrite_stream &Out, - raw_pwrite_stream *DwoOut, - CodeGenFileType FileType, - bool DisableVerify, - MachineModuleInfo *MMI) { +bool LLVMTargetMachine::addPassesToEmitFile( + PassManagerBase &PM, raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut, + CodeGenFileType FileType, bool DisableVerify, + MachineModuleInfoWrapperPass *MMIWP) { // Add common CodeGen passes. - if (!MMI) - MMI = new MachineModuleInfo(this); + if (!MMIWP) + MMIWP = new MachineModuleInfoWrapperPass(this); TargetPassConfig *PassConfig = - addPassesToGenerateCode(*this, PM, DisableVerify, *MMI); + addPassesToGenerateCode(*this, PM, DisableVerify, *MMIWP); if (!PassConfig) return true; @@ -206,12 +205,13 @@ // testing to be meaningful, we need to ensure that the symbols created // are MCSymbolXCOFF variants, which requires that // the TargetLoweringObjectFile instance has been initialized. - MCContext &Ctx = MMI->getContext(); + MCContext &Ctx = MMIWP->getMMI().getContext(); const_cast(*this->getObjFileLowering()) .Initialize(Ctx, *this); } PM.add(createPrintMIRPass(Out)); - } else if (addAsmPrinter(PM, Out, DwoOut, FileType, MMI->getContext())) + } else if (addAsmPrinter(PM, Out, DwoOut, FileType, + MMIWP->getMMI().getContext())) return true; PM.add(createFreeMachineFunctionPass()); @@ -227,15 +227,15 @@ raw_pwrite_stream &Out, bool DisableVerify) { // Add common CodeGen passes. - MachineModuleInfo *MMI = new MachineModuleInfo(this); + MachineModuleInfoWrapperPass *MMIWP = new MachineModuleInfoWrapperPass(this); TargetPassConfig *PassConfig = - addPassesToGenerateCode(*this, PM, DisableVerify, *MMI); + addPassesToGenerateCode(*this, PM, DisableVerify, *MMIWP); if (!PassConfig) return true; assert(TargetPassConfig::willCompleteCodeGenPipeline() && "Cannot emit MC with limited codegen pipeline"); - Ctx = &MMI->getContext(); + Ctx = &MMIWP->getMMI().getContext(); if (Options.MCOptions.MCSaveTempLabels) Ctx->setAllowTemporaryLabels(false); diff --git a/llvm/lib/CodeGen/LazyMachineBlockFrequencyInfo.cpp b/llvm/lib/CodeGen/LazyMachineBlockFrequencyInfo.cpp --- a/llvm/lib/CodeGen/LazyMachineBlockFrequencyInfo.cpp +++ b/llvm/lib/CodeGen/LazyMachineBlockFrequencyInfo.cpp @@ -62,20 +62,23 @@ auto &MBPI = getAnalysis(); auto *MLI = getAnalysisIfAvailable(); - auto *MDT = getAnalysisIfAvailable(); + auto *MDTWP = getAnalysisIfAvailable(); LLVM_DEBUG(dbgs() << "Building MachineBlockFrequencyInfo on the fly\n"); LLVM_DEBUG(if (MLI) dbgs() << "LoopInfo is available\n"); if (!MLI) { LLVM_DEBUG(dbgs() << "Building LoopInfo on the fly\n"); // First create a dominator tree. - LLVM_DEBUG(if (MDT) dbgs() << "DominatorTree is available\n"); + LLVM_DEBUG(if (MDTWP) dbgs() << "DominatorTree is available\n"); - if (!MDT) { + MachineDominatorTree *MDT; + if (!MDTWP) { LLVM_DEBUG(dbgs() << "Building DominatorTree on the fly\n"); OwnedMDT = make_unique(); OwnedMDT->getBase().recalculate(*MF); MDT = OwnedMDT.get(); + } else { + MDT = &MDTWP->getMachineDominatorTree(); } // Generate LoopInfo from it. diff --git a/llvm/lib/CodeGen/LiveDebugVariables.cpp b/llvm/lib/CodeGen/LiveDebugVariables.cpp --- a/llvm/lib/CodeGen/LiveDebugVariables.cpp +++ b/llvm/lib/CodeGen/LiveDebugVariables.cpp @@ -77,13 +77,13 @@ INITIALIZE_PASS_BEGIN(LiveDebugVariables, DEBUG_TYPE, "Debug Variable Analysis", false, false) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(LiveIntervals) INITIALIZE_PASS_END(LiveDebugVariables, DEBUG_TYPE, "Debug Variable Analysis", false, false) void LiveDebugVariables::getAnalysisUsage(AnalysisUsage &AU) const { - AU.addRequired(); + AU.addRequired(); AU.addRequiredTransitive(); AU.setPreservesAll(); MachineFunctionPass::getAnalysisUsage(AU); diff --git a/llvm/lib/CodeGen/LiveIntervals.cpp b/llvm/lib/CodeGen/LiveIntervals.cpp --- a/llvm/lib/CodeGen/LiveIntervals.cpp +++ b/llvm/lib/CodeGen/LiveIntervals.cpp @@ -62,7 +62,7 @@ INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals", "Live Interval Analysis", false, false) INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(SlotIndexes) INITIALIZE_PASS_END(LiveIntervals, "liveintervals", "Live Interval Analysis", false, false) @@ -129,7 +129,7 @@ TII = MF->getSubtarget().getInstrInfo(); AA = &getAnalysis().getAAResults(); Indexes = &getAnalysis(); - DomTree = &getAnalysis(); + DomTree = &getAnalysis().getMachineDominatorTree(); if (!LRCalc) LRCalc = new LiveRangeCalc(); diff --git a/llvm/lib/CodeGen/MIRPrintingPass.cpp b/llvm/lib/CodeGen/MIRPrintingPass.cpp --- a/llvm/lib/CodeGen/MIRPrintingPass.cpp +++ b/llvm/lib/CodeGen/MIRPrintingPass.cpp @@ -11,7 +11,9 @@ // //===----------------------------------------------------------------------===// +#include "llvm/CodeGen/MIRPrintingPass.h" #include "llvm/CodeGen/MIRPrinter.h" +#include "llvm/CodeGen/PassManager.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/Passes.h" @@ -20,17 +22,32 @@ using namespace llvm; +PreservedAnalyses MIRPrintingPass::run(Module &M, ModuleAnalysisManager &MAM) { + printMIR(OS, M); + // FIXME: Inefficient. Should only make this adaptor once. Put it in + // the class and construct it the first time. + return createModuleToFunctionPassAdaptor( + createFunctionToMachineFunctionPassAdaptor(*this)) + .run(M, MAM); +} + +PreservedAnalyses MIRPrintingPass::run(MachineFunction &MF, + MachineFunctionAnalysisManager &) { + printMIR(OS, MF); + return PreservedAnalyses::all(); +} + namespace { /// This pass prints out the LLVM IR to an output stream using the MIR /// serialization format. -struct MIRPrintingPass : public MachineFunctionPass { +struct MIRPrintingLegacyPass : public MachineFunctionPass { static char ID; raw_ostream &OS; std::string MachineFunctions; - MIRPrintingPass() : MachineFunctionPass(ID), OS(dbgs()) {} - MIRPrintingPass(raw_ostream &OS) : MachineFunctionPass(ID), OS(OS) {} + MIRPrintingLegacyPass() : MachineFunctionPass(ID), OS(dbgs()) {} + MIRPrintingLegacyPass(raw_ostream &OS) : MachineFunctionPass(ID), OS(OS) {} StringRef getPassName() const override { return "MIR Printing Pass"; } @@ -54,17 +71,18 @@ } }; -char MIRPrintingPass::ID = 0; +char MIRPrintingLegacyPass::ID = 0; } // end anonymous namespace -char &llvm::MIRPrintingPassID = MIRPrintingPass::ID; -INITIALIZE_PASS(MIRPrintingPass, "mir-printer", "MIR Printer", false, false) +char &llvm::MIRPrintingPassID = MIRPrintingLegacyPass::ID; +INITIALIZE_PASS(MIRPrintingLegacyPass, "mir-printer", "MIR Printer", false, + false) namespace llvm { MachineFunctionPass *createPrintMIRPass(raw_ostream &OS) { - return new MIRPrintingPass(OS); + return new MIRPrintingLegacyPass(OS); } } // end namespace llvm diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp --- a/llvm/lib/CodeGen/MachineBasicBlock.cpp +++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp @@ -1072,8 +1072,9 @@ LIS->repairIntervalsInRange(this, getFirstTerminator(), end(), UsedRegs); } - if (MachineDominatorTree *MDT = - P.getAnalysisIfAvailable()) + auto *MDTWP = P.getAnalysisIfAvailable(); + + if (MachineDominatorTree *MDT = MDTWP ? &MDTWP->getMachineDominatorTree() : nullptr) MDT->recordSplitCriticalEdge(this, Succ, NMBB); if (MachineLoopInfo *MLI = P.getAnalysisIfAvailable()) diff --git a/llvm/lib/CodeGen/MachineBlockPlacement.cpp b/llvm/lib/CodeGen/MachineBlockPlacement.cpp --- a/llvm/lib/CodeGen/MachineBlockPlacement.cpp +++ b/llvm/lib/CodeGen/MachineBlockPlacement.cpp @@ -2855,9 +2855,11 @@ BranchFolder BF(/*EnableTailMerge=*/true, /*CommonHoist=*/false, *MBFI, *MBPI, TailMergeSize); - if (BF.OptimizeFunction(MF, TII, MF.getSubtarget().getRegisterInfo(), - getAnalysisIfAvailable(), MLI, - /*AfterBlockPlacement=*/true)) { + if (BF.OptimizeFunction( + MF, TII, MF.getSubtarget().getRegisterInfo(), + &getAnalysisIfAvailable()->getMMI(), + MLI, + /*AfterBlockPlacement=*/true)) { // Redo the layout if tail merging creates/removes/moves blocks. BlockToChain.clear(); ComputedEdges.clear(); diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp --- a/llvm/lib/CodeGen/MachineCSE.cpp +++ b/llvm/lib/CodeGen/MachineCSE.cpp @@ -12,6 +12,8 @@ // //===----------------------------------------------------------------------===// +#include "llvm/CodeGen/MachineCSE.h" + #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/ScopedHashTable.h" #include "llvm/ADT/SmallPtrSet.h" @@ -27,6 +29,7 @@ #include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/Passes.h" +#include "llvm/CodeGen/PassManager.h" #include "llvm/CodeGen/TargetInstrInfo.h" #include "llvm/CodeGen/TargetOpcodes.h" #include "llvm/CodeGen/TargetRegisterInfo.h" @@ -57,7 +60,7 @@ namespace { - class MachineCSE : public MachineFunctionPass { + class MachineCSE { const TargetInstrInfo *TII; const TargetRegisterInfo *TRI; AliasAnalysis *AA; @@ -65,28 +68,18 @@ MachineRegisterInfo *MRI; public: - static char ID; // Pass identification - - MachineCSE() : MachineFunctionPass(ID) { - initializeMachineCSEPass(*PassRegistry::getPassRegistry()); - } - - bool runOnMachineFunction(MachineFunction &MF) override; - - void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.setPreservesCFG(); - MachineFunctionPass::getAnalysisUsage(AU); - AU.addRequired(); - AU.addPreservedID(MachineLoopInfoID); - AU.addRequired(); - AU.addPreserved(); + MachineCSE(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, AliasAnalysis *AA, + MachineDominatorTree *DT, MachineRegisterInfo *MRI) : TII(TII), TRI(TRI), AA(AA), DT(DT), MRI(MRI) { + LookAheadLimit = TII->getMachineCSELookAheadLimit(); } - void releaseMemory() override { + ~MachineCSE() { ScopeMap.clear(); Exps.clear(); } + bool PerformCSE(MachineDomTreeNode *Node); + private: using AllocatorTy = RecyclingAllocator>; @@ -122,20 +115,39 @@ bool ProcessBlock(MachineBasicBlock *MBB); void ExitScopeIfDone(MachineDomTreeNode *Node, DenseMap &OpenChildren); - bool PerformCSE(MachineDomTreeNode *Node); + }; + + class MachineCSELegacyPass : public MachineFunctionPass { + public: + static char ID; // Pass identification + + MachineCSELegacyPass() : MachineFunctionPass(ID) { + initializeMachineCSELegacyPassPass(*PassRegistry::getPassRegistry()); + } + + bool runOnMachineFunction(MachineFunction &MF) override; + + void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.setPreservesCFG(); + MachineFunctionPass::getAnalysisUsage(AU); + AU.addRequired(); + AU.addPreservedID(MachineLoopInfoID); + AU.addRequired(); + AU.addPreserved(); + } }; } // end anonymous namespace -char MachineCSE::ID = 0; +char MachineCSELegacyPass::ID = 0; -char &llvm::MachineCSEID = MachineCSE::ID; +char &llvm::MachineCSEID = MachineCSELegacyPass::ID; -INITIALIZE_PASS_BEGIN(MachineCSE, DEBUG_TYPE, +INITIALIZE_PASS_BEGIN(MachineCSELegacyPass, DEBUG_TYPE, "Machine Common Subexpression Elimination", false, false) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass) -INITIALIZE_PASS_END(MachineCSE, DEBUG_TYPE, +INITIALIZE_PASS_END(MachineCSELegacyPass, DEBUG_TYPE, "Machine Common Subexpression Elimination", false, false) /// The source register of a COPY machine instruction can be propagated to all @@ -746,15 +758,36 @@ return Changed; } -bool MachineCSE::runOnMachineFunction(MachineFunction &MF) { +bool MachineCSELegacyPass::runOnMachineFunction(MachineFunction &MF) { if (skipFunction(MF.getFunction())) return false; - TII = MF.getSubtarget().getInstrInfo(); - TRI = MF.getSubtarget().getRegisterInfo(); - MRI = &MF.getRegInfo(); - AA = &getAnalysis().getAAResults(); - DT = &getAnalysis(); - LookAheadLimit = TII->getMachineCSELookAheadLimit(); - return PerformCSE(DT->getRootNode()); + MachineDominatorTree *DT = &getAnalysis().getMachineDominatorTree(); + + MachineCSE MCSE(MF.getSubtarget().getInstrInfo(), + MF.getSubtarget().getRegisterInfo(), + &getAnalysis().getAAResults(), + DT, + &MF.getRegInfo()); + return MCSE.PerformCSE(DT->getRootNode()); +} + +PreservedAnalyses MachineCSEPass::run(MachineFunction &MF, + MachineFunctionAnalysisManager &AM) { + MachineDominatorTree *DT = &AM.getResult(MF); + const auto &FAM = AM.getResult(MF).getManager(); + MachineCSE MCSE(MF.getSubtarget().getInstrInfo(), + MF.getSubtarget().getRegisterInfo(), + FAM.getCachedResult(*const_cast(&MF.getFunction())), + DT, + &MF.getRegInfo()); + + if (!MCSE.PerformCSE(DT->getRootNode())) + return PreservedAnalyses::all(); + + PreservedAnalyses PA; + PA.preserveSet(); + PA.preserve(); + + return PA; } diff --git a/llvm/lib/CodeGen/MachineCombiner.cpp b/llvm/lib/CodeGen/MachineCombiner.cpp --- a/llvm/lib/CodeGen/MachineCombiner.cpp +++ b/llvm/lib/CodeGen/MachineCombiner.cpp @@ -126,7 +126,7 @@ void MachineCombiner::getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesCFG(); - AU.addPreserved(); + AU.addPreserved(); AU.addRequired(); AU.addPreserved(); AU.addRequired(); diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp --- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp +++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp @@ -59,6 +59,7 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/DebugCounter.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/CodeGen/MachineCopyPropagation.h" #include #include @@ -180,16 +181,11 @@ } }; -class MachineCopyPropagation : public MachineFunctionPass { - const TargetRegisterInfo *TRI; - const TargetInstrInfo *TII; - const MachineRegisterInfo *MRI; - +class MachineCopyPropagationLegacyPass : public MachineFunctionPass { public: static char ID; // Pass identification, replacement for typeid - - MachineCopyPropagation() : MachineFunctionPass(ID) { - initializeMachineCopyPropagationPass(*PassRegistry::getPassRegistry()); + MachineCopyPropagationLegacyPass() : MachineFunctionPass(ID) { + initializeMachineCopyPropagationLegacyPassPass(*PassRegistry::getPassRegistry()); } void getAnalysisUsage(AnalysisUsage &AU) const override { @@ -203,11 +199,24 @@ return MachineFunctionProperties().set( MachineFunctionProperties::Property::NoVRegs); } +}; + +class MachineCopyPropagation { + const TargetRegisterInfo *TRI; + const TargetInstrInfo *TII; + const MachineRegisterInfo *MRI; + +public: + bool Changed; + MachineCopyPropagation(const TargetRegisterInfo *TRI, + const TargetInstrInfo *TII, + const MachineRegisterInfo *MRI) + : TRI(TRI), TII(TII), MRI(MRI), Changed(false) {} + void CopyPropagateBlock(MachineBasicBlock &MBB); private: void ClobberRegister(unsigned Reg); void ReadRegister(unsigned Reg); - void CopyPropagateBlock(MachineBasicBlock &MBB); bool eraseIfRedundant(MachineInstr &Copy, unsigned Src, unsigned Def); void forwardUses(MachineInstr &MI); bool isForwardableRegClassCopy(const MachineInstr &Copy, @@ -218,17 +227,15 @@ SmallSetVector MaybeDeadCopies; CopyTracker Tracker; - - bool Changed; }; } // end anonymous namespace -char MachineCopyPropagation::ID = 0; +char MachineCopyPropagationLegacyPass::ID = 0; -char &llvm::MachineCopyPropagationID = MachineCopyPropagation::ID; +char &llvm::MachineCopyPropagationID = MachineCopyPropagationLegacyPass::ID; -INITIALIZE_PASS(MachineCopyPropagation, DEBUG_TYPE, +INITIALIZE_PASS(MachineCopyPropagationLegacyPass, DEBUG_TYPE, "Machine Copy Propagation Pass", false, false) void MachineCopyPropagation::ReadRegister(unsigned Reg) { @@ -623,18 +630,23 @@ Tracker.clear(); } -bool MachineCopyPropagation::runOnMachineFunction(MachineFunction &MF) { - if (skipFunction(MF.getFunction())) - return false; +MachineCopyPropagation copyPropagate(MachineFunction &MF) { + MachineCopyPropagation info{MF.getSubtarget().getRegisterInfo(), + MF.getSubtarget().getInstrInfo(), + &MF.getRegInfo()}; - Changed = false; + for (MachineBasicBlock &MBB : MF) + info.CopyPropagateBlock(MBB); - TRI = MF.getSubtarget().getRegisterInfo(); - TII = MF.getSubtarget().getInstrInfo(); - MRI = &MF.getRegInfo(); + return info; +} - for (MachineBasicBlock &MBB : MF) - CopyPropagateBlock(MBB); +PreservedAnalyses MachineCopyPropagationPass::run(MachineFunction &MF, MachineFunctionAnalysisManager &AM) { + return copyPropagate(MF).Changed ? PreservedAnalyses::all() : PreservedAnalyses::none(); +} - return Changed; +bool MachineCopyPropagationLegacyPass::runOnMachineFunction(MachineFunction &MF) { + if (skipFunction(MF.getFunction())) + return false; + return copyPropagate(MF).Changed; } diff --git a/llvm/lib/CodeGen/MachineDominanceFrontier.cpp b/llvm/lib/CodeGen/MachineDominanceFrontier.cpp --- a/llvm/lib/CodeGen/MachineDominanceFrontier.cpp +++ b/llvm/lib/CodeGen/MachineDominanceFrontier.cpp @@ -24,7 +24,7 @@ INITIALIZE_PASS_BEGIN(MachineDominanceFrontier, "machine-domfrontier", "Machine Dominance Frontier Construction", true, true) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_END(MachineDominanceFrontier, "machine-domfrontier", "Machine Dominance Frontier Construction", true, true) @@ -38,7 +38,7 @@ bool MachineDominanceFrontier::runOnMachineFunction(MachineFunction &) { releaseMemory(); - Base.analyze(getAnalysis().getBase()); + Base.analyze(getAnalysis().getMachineDominatorTree().getBase()); return false; } @@ -48,6 +48,6 @@ void MachineDominanceFrontier::getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesAll(); - AU.addRequired(); + AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } diff --git a/llvm/lib/CodeGen/MachineDominators.cpp b/llvm/lib/CodeGen/MachineDominators.cpp --- a/llvm/lib/CodeGen/MachineDominators.cpp +++ b/llvm/lib/CodeGen/MachineDominators.cpp @@ -33,33 +33,37 @@ template class DominatorTreeBase; // DomTreeBase } -char MachineDominatorTree::ID = 0; +char MachineDominatorTreeWrapperPass::ID = 0; -INITIALIZE_PASS(MachineDominatorTree, "machinedomtree", +INITIALIZE_PASS(MachineDominatorTreeWrapperPass, "machinedomtree", "MachineDominator Tree Construction", true, true) -char &llvm::MachineDominatorsID = MachineDominatorTree::ID; +char &llvm::MachineDominatorsID = MachineDominatorTreeWrapperPass::ID; -void MachineDominatorTree::getAnalysisUsage(AnalysisUsage &AU) const { +void MachineDominatorTreeWrapperPass::getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesAll(); MachineFunctionPass::getAnalysisUsage(AU); } -bool MachineDominatorTree::runOnMachineFunction(MachineFunction &F) { - CriticalEdgesToSplit.clear(); - NewBBs.clear(); - DT.reset(new DomTreeBase()); - DT->recalculate(F); +bool MachineDominatorTreeWrapperPass::runOnMachineFunction(MachineFunction &F) { + releaseMemory(); + DT.DT.reset(new DomTreeBase()); + DT.DT->recalculate(F); return false; } -MachineDominatorTree::MachineDominatorTree() +MachineDominatorTreeWrapperPass::MachineDominatorTreeWrapperPass() : MachineFunctionPass(ID) { - initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry()); + initializeMachineDominatorTreeWrapperPassPass(*PassRegistry::getPassRegistry()); +} + +void MachineDominatorTreeWrapperPass::releaseMemory() { + DT.releaseMemory(); } void MachineDominatorTree::releaseMemory() { CriticalEdgesToSplit.clear(); + NewBBs.clear(); DT.reset(nullptr); } @@ -81,9 +85,13 @@ } } -void MachineDominatorTree::print(raw_ostream &OS, const Module*) const { - if (DT) - DT->print(OS); +void MachineDominatorTreeWrapperPass::print(raw_ostream &OS, const Module*) const { + if (DT.DT) + DT.DT->print(OS); +} + +void MachineDominatorTreeWrapperPass::verifyAnalysis() const { + DT.verifyAnalysis(); } void MachineDominatorTree::applySplitCriticalEdges() const { @@ -150,3 +158,13 @@ NewBBs.clear(); CriticalEdgesToSplit.clear(); } + +AnalysisKey MachineDominatorTreeAnalysis::Key; + +MachineDominatorTree MachineDominatorTreeAnalysis::run(MachineFunction &F, + MachineFunctionAnalysisManager &AM) { + MachineDominatorTree DT; + DT.DT.reset(new DomTreeBase()); + DT.DT->recalculate(F); + return DT; +} diff --git a/llvm/lib/CodeGen/MachineFunctionPass.cpp b/llvm/lib/CodeGen/MachineFunctionPass.cpp --- a/llvm/lib/CodeGen/MachineFunctionPass.cpp +++ b/llvm/lib/CodeGen/MachineFunctionPass.cpp @@ -41,7 +41,7 @@ if (F.hasAvailableExternallyLinkage()) return false; - MachineModuleInfo &MMI = getAnalysis(); + MachineModuleInfo &MMI = getAnalysis().getMMI(); MachineFunction &MF = MMI.getOrCreateMachineFunction(F); MachineFunctionProperties &MFProps = MF.getProperties(); @@ -101,8 +101,8 @@ } void MachineFunctionPass::getAnalysisUsage(AnalysisUsage &AU) const { - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); // MachineFunctionPass preserves all LLVM IR passes, but there's no // high-level way to express this. Instead, just list a bunch of diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp --- a/llvm/lib/CodeGen/MachineLICM.cpp +++ b/llvm/lib/CodeGen/MachineLICM.cpp @@ -150,10 +150,10 @@ void getAnalysisUsage(AnalysisUsage &AU) const override { AU.addRequired(); - AU.addRequired(); + AU.addRequired(); AU.addRequired(); AU.addPreserved(); - AU.addPreserved(); + AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -276,7 +276,7 @@ INITIALIZE_PASS_BEGIN(MachineLICM, DEBUG_TYPE, "Machine Loop Invariant Code Motion", false, false) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass) INITIALIZE_PASS_END(MachineLICM, DEBUG_TYPE, "Machine Loop Invariant Code Motion", false, false) @@ -284,7 +284,7 @@ INITIALIZE_PASS_BEGIN(EarlyMachineLICM, "early-machinelicm", "Early Machine Loop Invariant Code Motion", false, false) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass) INITIALIZE_PASS_END(EarlyMachineLICM, "early-machinelicm", "Early Machine Loop Invariant Code Motion", false, false) @@ -335,7 +335,7 @@ // Get our Loop information... MLI = &getAnalysis(); - DT = &getAnalysis(); + DT = &getAnalysis().getMachineDominatorTree(); AA = &getAnalysis().getAAResults(); SmallVector Worklist(MLI->begin(), MLI->end()); diff --git a/llvm/lib/CodeGen/MachineLoopInfo.cpp b/llvm/lib/CodeGen/MachineLoopInfo.cpp --- a/llvm/lib/CodeGen/MachineLoopInfo.cpp +++ b/llvm/lib/CodeGen/MachineLoopInfo.cpp @@ -29,7 +29,7 @@ char MachineLoopInfo::ID = 0; INITIALIZE_PASS_BEGIN(MachineLoopInfo, "machine-loops", "Machine Natural Loop Construction", true, true) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_END(MachineLoopInfo, "machine-loops", "Machine Natural Loop Construction", true, true) @@ -37,13 +37,13 @@ bool MachineLoopInfo::runOnMachineFunction(MachineFunction &) { releaseMemory(); - LI.analyze(getAnalysis().getBase()); + LI.analyze(getAnalysis().getMachineDominatorTree().getBase()); return false; } void MachineLoopInfo::getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesAll(); - AU.addRequired(); + AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } diff --git a/llvm/lib/CodeGen/MachineModuleInfo.cpp b/llvm/lib/CodeGen/MachineModuleInfo.cpp --- a/llvm/lib/CodeGen/MachineModuleInfo.cpp +++ b/llvm/lib/CodeGen/MachineModuleInfo.cpp @@ -36,11 +36,6 @@ using namespace llvm; using namespace llvm::dwarf; -// Handle the Pass registration stuff necessary to use DataLayout's. -INITIALIZE_PASS(MachineModuleInfo, "machinemoduleinfo", - "Machine Module Information", false, false) -char MachineModuleInfo::ID = 0; - // Out of line virtual method. MachineModuleInfoImpl::~MachineModuleInfoImpl() = default; @@ -193,27 +188,15 @@ Map->UpdateForRAUWBlock(cast(getValPtr()), cast(V2)); } -MachineModuleInfo::MachineModuleInfo(const LLVMTargetMachine *TM) - : ImmutablePass(ID), TM(*TM), - Context(TM->getMCAsmInfo(), TM->getMCRegisterInfo(), - TM->getObjFileLowering(), nullptr, false) { - initializeMachineModuleInfoPass(*PassRegistry::getPassRegistry()); -} - -MachineModuleInfo::~MachineModuleInfo() = default; - -bool MachineModuleInfo::doInitialization(Module &M) { +void MachineModuleInfo::initialize() { ObjFileMMI = nullptr; CurCallSite = 0; UsesMSVCFloatingPoint = UsesMorestackAddr = false; HasSplitStack = HasNosplitStack = false; AddrLabelSymbols = nullptr; - TheModule = &M; - DbgInfoAvailable = !llvm::empty(M.debug_compile_units()); - return false; } -bool MachineModuleInfo::doFinalization(Module &M) { +void MachineModuleInfo::finalize() { Personalities.clear(); delete AddrLabelSymbols; @@ -223,8 +206,28 @@ delete ObjFileMMI; ObjFileMMI = nullptr; +} - return false; +MachineModuleInfo::MachineModuleInfo(MachineModuleInfo &&MMI) + : TM(std::move(MMI.TM)), Context(MMI.TM.getMCAsmInfo(), MMI.TM.getMCRegisterInfo(), + MMI.TM.getObjFileLowering(), nullptr, false) { + ObjFileMMI = MMI.ObjFileMMI; + CurCallSite = MMI.CurCallSite; + UsesMSVCFloatingPoint = MMI.UsesMSVCFloatingPoint; + UsesMorestackAddr = MMI.UsesMorestackAddr; + HasSplitStack = MMI.HasSplitStack; + HasNosplitStack = MMI.HasNosplitStack; + AddrLabelSymbols = MMI.AddrLabelSymbols; +} + +MachineModuleInfo::MachineModuleInfo(const LLVMTargetMachine *TM) + : TM(*TM), Context(TM->getMCAsmInfo(), TM->getMCRegisterInfo(), + TM->getObjFileLowering(), nullptr, false) { + initialize(); +} + +MachineModuleInfo::~MachineModuleInfo() { + finalize(); } //===- Address of Block Management ----------------------------------------===// @@ -305,12 +308,13 @@ FreeMachineFunction() : FunctionPass(ID) {} void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); } bool runOnFunction(Function &F) override { - MachineModuleInfo &MMI = getAnalysis(); + MachineModuleInfo &MMI = + getAnalysis().getMMI(); MMI.deleteMachineFunctionFor(F); return true; } @@ -327,3 +331,36 @@ FunctionPass *llvm::createFreeMachineFunctionPass() { return new FreeMachineFunction(); } + +MachineModuleInfoWrapperPass::MachineModuleInfoWrapperPass( + const LLVMTargetMachine *TM) + : ImmutablePass(ID), MMI(TM) { + initializeMachineModuleInfoWrapperPassPass(*PassRegistry::getPassRegistry()); +} + +// Handle the Pass registration stuff necessary to use DataLayout's. +INITIALIZE_PASS(MachineModuleInfoWrapperPass, "machinemoduleinfo", + "Machine Module Information", false, false) +char MachineModuleInfoWrapperPass::ID = 0; + +bool MachineModuleInfoWrapperPass::doInitialization(Module &M) { + MMI.initialize(); + MMI.TheModule = &M; + MMI.DbgInfoAvailable = !llvm::empty(M.debug_compile_units()); + return false; +} + +bool MachineModuleInfoWrapperPass::doFinalization(Module &M) { + MMI.finalize(); + return false; +} + +AnalysisKey MachineModuleAnalysis::Key; + +MachineModuleInfo MachineModuleAnalysis::run(Module &M, + ModuleAnalysisManager &) { + MachineModuleInfo MMI(TM); + MMI.TheModule = &M; + MMI.DbgInfoAvailable = !llvm::empty(M.debug_compile_units()); + return MMI; +} diff --git a/llvm/lib/CodeGen/MachineOutliner.cpp b/llvm/lib/CodeGen/MachineOutliner.cpp --- a/llvm/lib/CodeGen/MachineOutliner.cpp +++ b/llvm/lib/CodeGen/MachineOutliner.cpp @@ -846,8 +846,8 @@ StringRef getPassName() const override { return "Machine Outliner"; } void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); AU.setPreservesAll(); ModulePass::getAnalysisUsage(AU); } @@ -1128,7 +1128,7 @@ IRBuilder<> Builder(EntryBB); Builder.CreateRetVoid(); - MachineModuleInfo &MMI = getAnalysis(); + MachineModuleInfo &MMI = getAnalysis().getMMI(); MachineFunction &MF = MMI.getOrCreateMachineFunction(*F); MachineBasicBlock &MBB = *MF.CreateMachineBasicBlock(); const TargetSubtargetInfo &STI = MF.getSubtarget(); @@ -1417,7 +1417,7 @@ if (M.empty()) return false; - MachineModuleInfo &MMI = getAnalysis(); + MachineModuleInfo &MMI = getAnalysis().getMMI(); // If the user passed -enable-machine-outliner=always or // -enable-machine-outliner, the pass will run on all functions in the module. diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp --- a/llvm/lib/CodeGen/MachinePipeliner.cpp +++ b/llvm/lib/CodeGen/MachinePipeliner.cpp @@ -169,7 +169,7 @@ "Modulo Software Pipelining", false, false) INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(LiveIntervals) INITIALIZE_PASS_END(MachinePipeliner, DEBUG_TYPE, "Modulo Software Pipelining", false, false) @@ -196,7 +196,7 @@ MF = &mf; MLI = &getAnalysis(); - MDT = &getAnalysis(); + MDT = &getAnalysis().getMachineDominatorTree(); TII = MF->getSubtarget().getInstrInfo(); RegClassInfo.runOnMachineFunction(*MF); diff --git a/llvm/lib/CodeGen/MachineRegionInfo.cpp b/llvm/lib/CodeGen/MachineRegionInfo.cpp --- a/llvm/lib/CodeGen/MachineRegionInfo.cpp +++ b/llvm/lib/CodeGen/MachineRegionInfo.cpp @@ -83,7 +83,7 @@ bool MachineRegionInfoPass::runOnMachineFunction(MachineFunction &F) { releaseMemory(); - auto DT = &getAnalysis(); + auto DT = &getAnalysis().getMachineDominatorTree(); auto PDT = &getAnalysis(); auto DF = &getAnalysis(); @@ -108,7 +108,7 @@ void MachineRegionInfoPass::getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesAll(); - AU.addRequired(); + AU.addRequired(); AU.addRequired(); AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); @@ -129,7 +129,7 @@ INITIALIZE_PASS_BEGIN(MachineRegionInfoPass, DEBUG_TYPE, "Detect single entry single exit regions", true, true) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTree) INITIALIZE_PASS_DEPENDENCY(MachineDominanceFrontier) INITIALIZE_PASS_END(MachineRegionInfoPass, DEBUG_TYPE, diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -370,7 +370,7 @@ // Initialize the context of the pass. MF = &mf; MLI = &getAnalysis(); - MDT = &getAnalysis(); + MDT = &getAnalysis().getMachineDominatorTree(); PassConfig = &getAnalysis(); AA = &getAnalysis().getAAResults(); diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp --- a/llvm/lib/CodeGen/MachineSink.cpp +++ b/llvm/lib/CodeGen/MachineSink.cpp @@ -117,11 +117,11 @@ AU.setPreservesCFG(); MachineFunctionPass::getAnalysisUsage(AU); AU.addRequired(); - AU.addRequired(); + AU.addRequired(); AU.addRequired(); AU.addRequired(); AU.addRequired(); - AU.addPreserved(); + AU.addPreserved(); AU.addPreserved(); AU.addPreserved(); if (UseBlockFreqInfo) @@ -184,7 +184,7 @@ INITIALIZE_PASS_BEGIN(MachineSinking, DEBUG_TYPE, "Machine code sinking", false, false) INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo) INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass) INITIALIZE_PASS_END(MachineSinking, DEBUG_TYPE, @@ -300,7 +300,7 @@ TII = MF.getSubtarget().getInstrInfo(); TRI = MF.getSubtarget().getRegisterInfo(); MRI = &MF.getRegInfo(); - DT = &getAnalysis(); + DT = &getAnalysis().getMachineDominatorTree(); PDT = &getAnalysis(); LI = &getAnalysis(); MBFI = UseBlockFreqInfo ? &getAnalysis() : nullptr; diff --git a/llvm/lib/CodeGen/PHIElimination.cpp b/llvm/lib/CodeGen/PHIElimination.cpp --- a/llvm/lib/CodeGen/PHIElimination.cpp +++ b/llvm/lib/CodeGen/PHIElimination.cpp @@ -137,7 +137,7 @@ AU.addPreserved(); AU.addPreserved(); AU.addPreserved(); - AU.addPreserved(); + AU.addPreserved(); AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } diff --git a/llvm/lib/CodeGen/PassManager.cpp b/llvm/lib/CodeGen/PassManager.cpp new file mode 100644 --- /dev/null +++ b/llvm/lib/CodeGen/PassManager.cpp @@ -0,0 +1,34 @@ +//===-- PassManager.cpp -------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains the pass management machinery for machine functions. +// +//===----------------------------------------------------------------------===// + +#include "llvm/CodeGen/PassManager.h" + +using namespace llvm; + +namespace llvm { +template class AllAnalysesOn; +template class AnalysisManager; +template class PassManager; +template class InnerAnalysisManagerProxy; +template class OuterAnalysisManagerProxy; + +template <> +bool MachineFunctionAnalysisManagerFunctionProxy::Result::invalidate( + Function &F, const PreservedAnalyses &PA, + FunctionAnalysisManager::Invalidator &Inv) { + // Just assume that all proxies are valid for the time being until we run into trouble. + // Return false to indicate that this result is still a valid proxy. + return false; +} +} // namespace llvm diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp b/llvm/lib/CodeGen/PeepholeOptimizer.cpp --- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp +++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp @@ -172,8 +172,8 @@ AU.addRequired(); AU.addPreserved(); if (Aggressive) { - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); } } @@ -440,7 +440,7 @@ INITIALIZE_PASS_BEGIN(PeepholeOptimizer, DEBUG_TYPE, "Peephole Optimizations", false, false) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo) INITIALIZE_PASS_END(PeepholeOptimizer, DEBUG_TYPE, "Peephole Optimizations", false, false) @@ -1605,7 +1605,7 @@ TII = MF.getSubtarget().getInstrInfo(); TRI = MF.getSubtarget().getRegisterInfo(); MRI = &MF.getRegInfo(); - DT = Aggressive ? &getAnalysis() : nullptr; + DT = Aggressive ? &getAnalysis().getMachineDominatorTree() : nullptr; MLI = &getAnalysis(); bool Changed = false; diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp --- a/llvm/lib/CodeGen/PostRASchedulerList.cpp +++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp @@ -88,8 +88,8 @@ AU.setPreservesCFG(); AU.addRequired(); AU.addRequired(); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); AU.addRequired(); AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp --- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp +++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp @@ -144,7 +144,7 @@ INITIALIZE_PASS_BEGIN(PEI, DEBUG_TYPE, "Prologue/Epilogue Insertion", false, false) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineOptimizationRemarkEmitterPass) INITIALIZE_PASS_END(PEI, DEBUG_TYPE, "Prologue/Epilogue Insertion & Frame Finalization", false, @@ -160,7 +160,7 @@ void PEI::getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesCFG(); AU.addPreserved(); - AU.addPreserved(); + AU.addPreserved(); AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } diff --git a/llvm/lib/CodeGen/RegAllocBasic.cpp b/llvm/lib/CodeGen/RegAllocBasic.cpp --- a/llvm/lib/CodeGen/RegAllocBasic.cpp +++ b/llvm/lib/CodeGen/RegAllocBasic.cpp @@ -134,7 +134,7 @@ INITIALIZE_PASS_DEPENDENCY(RegisterCoalescer) INITIALIZE_PASS_DEPENDENCY(MachineScheduler) INITIALIZE_PASS_DEPENDENCY(LiveStacks) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo) INITIALIZE_PASS_DEPENDENCY(VirtRegMap) INITIALIZE_PASS_DEPENDENCY(LiveRegMatrix) diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp --- a/llvm/lib/CodeGen/RegAllocGreedy.cpp +++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp @@ -568,7 +568,7 @@ INITIALIZE_PASS_DEPENDENCY(RegisterCoalescer) INITIALIZE_PASS_DEPENDENCY(MachineScheduler) INITIALIZE_PASS_DEPENDENCY(LiveStacks) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo) INITIALIZE_PASS_DEPENDENCY(VirtRegMap) INITIALIZE_PASS_DEPENDENCY(LiveRegMatrix) @@ -615,8 +615,8 @@ AU.addPreserved(); AU.addRequired(); AU.addPreserved(); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); AU.addRequired(); AU.addPreserved(); AU.addRequired(); @@ -3231,7 +3231,7 @@ getAnalysis()); Indexes = &getAnalysis(); MBFI = &getAnalysis(); - DomTree = &getAnalysis(); + DomTree = &getAnalysis().getMachineDominatorTree(); ORE = &getAnalysis().getORE(); SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM)); Loops = &getAnalysis(); diff --git a/llvm/lib/CodeGen/RegAllocPBQP.cpp b/llvm/lib/CodeGen/RegAllocPBQP.cpp --- a/llvm/lib/CodeGen/RegAllocPBQP.cpp +++ b/llvm/lib/CodeGen/RegAllocPBQP.cpp @@ -545,8 +545,8 @@ au.addPreserved(); au.addRequired(); au.addPreserved(); - au.addRequired(); - au.addPreserved(); + au.addRequired(); + au.addPreserved(); au.addRequired(); au.addPreserved(); MachineFunctionPass::getAnalysisUsage(au); diff --git a/llvm/lib/CodeGen/ShrinkWrap.cpp b/llvm/lib/CodeGen/ShrinkWrap.cpp --- a/llvm/lib/CodeGen/ShrinkWrap.cpp +++ b/llvm/lib/CodeGen/ShrinkWrap.cpp @@ -186,7 +186,7 @@ /// Initialize the pass for \p MF. void init(MachineFunction &MF) { RCI.runOnMachineFunction(MF); - MDT = &getAnalysis(); + MDT = &getAnalysis().getMachineDominatorTree(); MPDT = &getAnalysis(); Save = nullptr; Restore = nullptr; @@ -223,7 +223,7 @@ void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesAll(); AU.addRequired(); - AU.addRequired(); + AU.addRequired(); AU.addRequired(); AU.addRequired(); AU.addRequired(); @@ -250,7 +250,7 @@ INITIALIZE_PASS_BEGIN(ShrinkWrap, DEBUG_TYPE, "Shrink Wrap Pass", false, false) INITIALIZE_PASS_DEPENDENCY(MachineBlockFrequencyInfo) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTree) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo) INITIALIZE_PASS_DEPENDENCY(MachineOptimizationRemarkEmitterPass) diff --git a/llvm/lib/CodeGen/UnreachableBlockElim.cpp b/llvm/lib/CodeGen/UnreachableBlockElim.cpp --- a/llvm/lib/CodeGen/UnreachableBlockElim.cpp +++ b/llvm/lib/CodeGen/UnreachableBlockElim.cpp @@ -95,7 +95,7 @@ void UnreachableMachineBlockElim::getAnalysisUsage(AnalysisUsage &AU) const { AU.addPreserved(); - AU.addPreserved(); + AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -103,8 +103,9 @@ df_iterator_default_set Reachable; bool ModifiedPHI = false; - MMI = getAnalysisIfAvailable(); - MachineDominatorTree *MDT = getAnalysisIfAvailable(); + MMI = &getAnalysisIfAvailable()->getMMI(); + MachineDominatorTreeWrapperPass *MDTWP = getAnalysisIfAvailable(); + MachineDominatorTree *MDT = MDTWP ? &MDTWP->getMachineDominatorTree() : nullptr; MachineLoopInfo *MLI = getAnalysisIfAvailable(); // Mark all reachable blocks. diff --git a/llvm/lib/CodeGen/XRayInstrumentation.cpp b/llvm/lib/CodeGen/XRayInstrumentation.cpp --- a/llvm/lib/CodeGen/XRayInstrumentation.cpp +++ b/llvm/lib/CodeGen/XRayInstrumentation.cpp @@ -52,7 +52,7 @@ void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); AU.addPreserved(); - AU.addPreserved(); + AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -159,7 +159,8 @@ MICount += MBB.size(); // Get MachineDominatorTree or compute it on the fly if it's unavailable - auto *MDT = getAnalysisIfAvailable(); + auto *MDTWP = getAnalysisIfAvailable(); + auto *MDT = MDTWP ? &MDTWP->getMachineDominatorTree() : nullptr; MachineDominatorTree ComputedMDT; if (!MDT) { ComputedMDT.getBase().recalculate(MF); diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -51,6 +51,7 @@ #include "llvm/Analysis/TargetLibraryInfo.h" #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/Analysis/TypeBasedAliasAnalysis.h" +#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/PreISelIntrinsicLowering.h" #include "llvm/CodeGen/UnreachableBlockElim.h" #include "llvm/IR/Dominators.h" @@ -142,8 +143,8 @@ #include "llvm/Transforms/Scalar/LowerWidenableCondition.h" #include "llvm/Transforms/Scalar/MakeGuardsExplicit.h" #include "llvm/Transforms/Scalar/MemCpyOptimizer.h" -#include "llvm/Transforms/Scalar/MergedLoadStoreMotion.h" #include "llvm/Transforms/Scalar/MergeICmps.h" +#include "llvm/Transforms/Scalar/MergedLoadStoreMotion.h" #include "llvm/Transforms/Scalar/NaryReassociate.h" #include "llvm/Transforms/Scalar/NewGVN.h" #include "llvm/Transforms/Scalar/PartiallyInlineLibCalls.h" diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -312,3 +312,17 @@ }, parseLoopUnswitchOptions) #undef LOOP_PASS_WITH_PARAMS + +#ifndef MACHINE_FUNCTION_ANALYSIS +#define MACHINE_FUNCTION_ANALYSIS(NAME, CREATE_PASS) +#endif +MACHINE_FUNCTION_ANALYSIS("machine-domtree", MachineDominatorTreeAnalysis()) +#undef MACHINE_FUNCTION_ANALYSIS + +#ifndef MACHINE_FUNCTION_PASS +#define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS) +#endif +MACHINE_FUNCTION_PASS("machine-cp", MachineCopyPropagationPass()) +MACHINE_FUNCTION_PASS("expand-isel-pseudos", ExpandISelPseudosPass()) +MACHINE_FUNCTION_PASS("machine-cse", MachineCSEPass()) +#undef MACHINE_FUNCTION_PASS diff --git a/llvm/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp b/llvm/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp --- a/llvm/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp +++ b/llvm/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp @@ -50,7 +50,7 @@ return false; } - MachineDominatorTree *DT = &getAnalysis(); + MachineDominatorTree *DT = &getAnalysis().getMachineDominatorTree(); return VisitNode(DT->getRootNode(), 0); } @@ -134,7 +134,7 @@ void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); - AU.addRequired(); + AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } }; diff --git a/llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp --- a/llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp +++ b/llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp @@ -125,7 +125,7 @@ INITIALIZE_PASS_BEGIN(AArch64ConditionOptimizer, "aarch64-condopt", "AArch64 CondOpt Pass", false, false) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_END(AArch64ConditionOptimizer, "aarch64-condopt", "AArch64 CondOpt Pass", false, false) @@ -134,8 +134,8 @@ } void AArch64ConditionOptimizer::getAnalysisUsage(AnalysisUsage &AU) const { - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -332,7 +332,7 @@ return false; TII = MF.getSubtarget().getInstrInfo(); - DomTree = &getAnalysis(); + DomTree = &getAnalysis().getMachineDominatorTree(); MRI = &MF.getRegInfo(); bool Changed = false; diff --git a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp --- a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp +++ b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp @@ -797,7 +797,7 @@ INITIALIZE_PASS_BEGIN(AArch64ConditionalCompares, "aarch64-ccmp", "AArch64 CCMP Pass", false, false) INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineTraceMetrics) INITIALIZE_PASS_END(AArch64ConditionalCompares, "aarch64-ccmp", "AArch64 CCMP Pass", false, false) @@ -808,8 +808,8 @@ void AArch64ConditionalCompares::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); AU.addRequired(); AU.addPreserved(); AU.addRequired(); @@ -935,7 +935,7 @@ TRI = MF.getSubtarget().getRegisterInfo(); SchedModel = MF.getSubtarget().getSchedModel(); MRI = &MF.getRegInfo(); - DomTree = &getAnalysis(); + DomTree = &getAnalysis().getMachineDominatorTree(); Loops = getAnalysisIfAvailable(); MBPI = &getAnalysis(); Traces = &getAnalysis(); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp --- a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp @@ -29,13 +29,14 @@ // except reserved size is not correctly aligned. const Function &F = MF.getFunction(); - if (auto *Resolver = MF.getMMI().getResolver()) { - if (AMDGPUPerfHintAnalysis *PHA = static_cast( - Resolver->getAnalysisIfAvailable(&AMDGPUPerfHintAnalysisID, true))) { - MemoryBound = PHA->isMemoryBound(&F); - WaveLimiter = PHA->needsWaveLimiter(&F); - } - } + // FIXME. How do we resolve this with the new PM? + // if (auto *Resolver = MF.getMMI().getResolver()) { + // if (AMDGPUPerfHintAnalysis *PHA = static_cast( + // Resolver->getAnalysisIfAvailable(&AMDGPUPerfHintAnalysisID, true))) { + // MemoryBound = PHA->isMemoryBound(&F); + // WaveLimiter = PHA->needsWaveLimiter(&F); + // } + // } CallingConv::ID CC = F.getCallingConv(); if (CC == CallingConv::AMDGPU_KERNEL || CC == CallingConv::SPIR_KERNEL) diff --git a/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp b/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp --- a/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp +++ b/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp @@ -136,7 +136,7 @@ } void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.addRequired(); + AU.addRequired(); AU.addRequired(); AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); @@ -159,8 +159,9 @@ FuncRep = &MF; MLI = &getAnalysis(); LLVM_DEBUG(dbgs() << "LoopInfo:\n"; PrintLoopinfo(*MLI);); - MDT = &getAnalysis(); - LLVM_DEBUG(MDT->print(dbgs(), (const Module *)nullptr);); + MachineDominatorTreeWrapperPass *MDTWP = &getAnalysis(); + MDT = &MDTWP->getMachineDominatorTree(); + LLVM_DEBUG(MDTWP->print(dbgs(), (const Module *)nullptr);); PDT = &getAnalysis(); LLVM_DEBUG(PDT->print(dbgs());); prepare(); @@ -1669,7 +1670,7 @@ INITIALIZE_PASS_BEGIN(AMDGPUCFGStructurizer, "amdgpustructurizer", "AMDGPU CFG Structurizer", false, false) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTree) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo) INITIALIZE_PASS_END(AMDGPUCFGStructurizer, "amdgpustructurizer", diff --git a/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp b/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp --- a/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp +++ b/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp @@ -123,8 +123,8 @@ void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); AU.addRequired(); AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); diff --git a/llvm/lib/Target/AMDGPU/R600Packetizer.cpp b/llvm/lib/Target/AMDGPU/R600Packetizer.cpp --- a/llvm/lib/Target/AMDGPU/R600Packetizer.cpp +++ b/llvm/lib/Target/AMDGPU/R600Packetizer.cpp @@ -40,8 +40,8 @@ void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); AU.addRequired(); AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp --- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp +++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp @@ -120,8 +120,8 @@ StringRef getPassName() const override { return "SI Fix SGPR copies"; } void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); AU.setPreservesCFG(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -131,7 +131,7 @@ INITIALIZE_PASS_BEGIN(SIFixSGPRCopies, DEBUG_TYPE, "SI Fix SGPR copies", false, false) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_END(SIFixSGPRCopies, DEBUG_TYPE, "SI Fix SGPR copies", false, false) @@ -571,7 +571,7 @@ MachineRegisterInfo &MRI = MF.getRegInfo(); const SIRegisterInfo *TRI = ST.getRegisterInfo(); const SIInstrInfo *TII = ST.getInstrInfo(); - MDT = &getAnalysis(); + MDT = &getAnalysis().getMachineDominatorTree(); SmallVector Worklist; diff --git a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp --- a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp @@ -70,7 +70,7 @@ void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); - AU.addRequired(); + AU.addRequired(); AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -397,7 +397,7 @@ INITIALIZE_PASS_BEGIN(SILowerI1Copies, DEBUG_TYPE, "SI Lower i1 Copies", false, false) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTree) INITIALIZE_PASS_END(SILowerI1Copies, DEBUG_TYPE, "SI Lower i1 Copies", false, false) @@ -437,7 +437,7 @@ bool SILowerI1Copies::runOnMachineFunction(MachineFunction &TheMF) { MF = &TheMF; MRI = &MF->getRegInfo(); - DT = &getAnalysis(); + DT = &getAnalysis().getMachineDominatorTree(); PDT = &getAnalysis(); ST = &MF->getSubtarget(); diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -1711,7 +1711,7 @@ MachineInstr &Use, MachineRegisterInfo &MRI, LiveIntervals *LIS) const { - auto &MDT = LIS->getAnalysis(); + auto &MDT = LIS->getAnalysis().getMachineDominatorTree(); SlotIndex UseIdx = LIS->getInstructionIndex(Use); SlotIndex DefIdx; diff --git a/llvm/lib/Target/ARC/ARCBranchFinalize.cpp b/llvm/lib/Target/ARC/ARCBranchFinalize.cpp --- a/llvm/lib/Target/ARC/ARCBranchFinalize.cpp +++ b/llvm/lib/Target/ARC/ARCBranchFinalize.cpp @@ -60,7 +60,7 @@ INITIALIZE_PASS_BEGIN(ARCBranchFinalize, "arc-branch-finalize", "ARC finalize branches", false, false) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_END(ARCBranchFinalize, "arc-branch-finalize", "ARC finalize branches", false, false) diff --git a/llvm/lib/Target/ARC/ARCOptAddrMode.cpp b/llvm/lib/Target/ARC/ARCOptAddrMode.cpp --- a/llvm/lib/Target/ARC/ARCOptAddrMode.cpp +++ b/llvm/lib/Target/ARC/ARCOptAddrMode.cpp @@ -48,8 +48,8 @@ void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); MachineFunctionPass::getAnalysisUsage(AU); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); } bool runOnMachineFunction(MachineFunction &MF) override; @@ -107,7 +107,7 @@ char ARCOptAddrMode::ID = 0; INITIALIZE_PASS_BEGIN(ARCOptAddrMode, OPTADDRMODE_NAME, OPTADDRMODE_DESC, false, false) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_END(ARCOptAddrMode, OPTADDRMODE_NAME, OPTADDRMODE_DESC, false, false) @@ -492,7 +492,7 @@ AST = &MF.getSubtarget(); AII = AST->getInstrInfo(); MRI = &MF.getRegInfo(); - MDT = &getAnalysis(); + MDT = &getAnalysis().getMachineDominatorTree(); bool Changed = false; for (auto &MBB : MF) diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp --- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -190,8 +190,8 @@ } void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -256,7 +256,7 @@ INITIALIZE_PASS_BEGIN(HexagonBitSimplify, "hexagon-bit-simplify", "Hexagon bit simplification", false, false) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_END(HexagonBitSimplify, "hexagon-bit-simplify", "Hexagon bit simplification", false, false) @@ -2766,7 +2766,7 @@ auto &HRI = *HST.getRegisterInfo(); auto &HII = *HST.getInstrInfo(); - MDT = &getAnalysis(); + MDT = &getAnalysis().getMachineDominatorTree(); MachineRegisterInfo &MRI = MF.getRegInfo(); bool Changed; diff --git a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp --- a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp +++ b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp @@ -214,8 +214,8 @@ HexagonConstExtenders() : MachineFunctionPass(ID) {} void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -566,7 +566,7 @@ INITIALIZE_PASS_BEGIN(HexagonConstExtenders, "hexagon-cext-opt", "Hexagon constant-extender optimization", false, false) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_END(HexagonConstExtenders, "hexagon-cext-opt", "Hexagon constant-extender optimization", false, false) @@ -1952,7 +1952,7 @@ HII = MF.getSubtarget().getInstrInfo(); HRI = MF.getSubtarget().getRegisterInfo(); - MDT = &getAnalysis(); + MDT = &getAnalysis().getMachineDominatorTree(); MRI = &MF.getRegInfo(); AssignmentMap IMap; diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp --- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -162,8 +162,8 @@ void getAnalysisUsage(AnalysisUsage &AU) const override { AU.addRequired(); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -1053,7 +1053,7 @@ TRI = ST.getRegisterInfo(); MFN = &MF; MRI = &MF.getRegInfo(); - MDT = &getAnalysis(); + MDT = &getAnalysis().getMachineDominatorTree(); MLI = &getAnalysis(); MBPI = EnableHexagonBP ? &getAnalysis() : nullptr; diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp --- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp +++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp @@ -153,8 +153,8 @@ AU.addRequired(); AU.addPreserved(); AU.addPreserved(); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -250,7 +250,7 @@ INITIALIZE_PASS_BEGIN(HexagonExpandCondsets, "expand-condsets", "Hexagon Expand Condsets", false, false) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(SlotIndexes) INITIALIZE_PASS_DEPENDENCY(LiveIntervals) INITIALIZE_PASS_END(HexagonExpandCondsets, "expand-condsets", @@ -1253,7 +1253,7 @@ HII = static_cast(MF.getSubtarget().getInstrInfo()); TRI = MF.getSubtarget().getRegisterInfo(); - MDT = &getAnalysis(); + MDT = &getAnalysis().getMachineDominatorTree(); LIS = &getAnalysis(); MRI = &MF.getRegInfo(); diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -403,8 +403,9 @@ auto &HRI = *MF.getSubtarget().getRegisterInfo(); - MachineDominatorTree MDT; - MDT.runOnMachineFunction(MF); + MachineDominatorTreeWrapperPass MDTWP; + MDTWP.runOnMachineFunction(MF); + MachineDominatorTree &MDT = MDTWP.getMachineDominatorTree(); MachinePostDominatorTree MPT; MPT.runOnMachineFunction(MF); diff --git a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp --- a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp +++ b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp @@ -511,8 +511,8 @@ } void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -1516,7 +1516,7 @@ HRI = ST.getRegisterInfo(); MFN = &MF; MRI = &MF.getRegInfo(); - MDT = &getAnalysis(); + MDT = &getAnalysis().getMachineDominatorTree(); // Clean up before any further processing, so that dead code does not // get used in a newly generated "insert" instruction. Have a custom @@ -1627,6 +1627,6 @@ INITIALIZE_PASS_BEGIN(HexagonGenInsert, "hexinsert", "Hexagon generate \"insert\" instructions", false, false) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_END(HexagonGenInsert, "hexinsert", "Hexagon generate \"insert\" instructions", false, false) diff --git a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp --- a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp +++ b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp @@ -89,8 +89,8 @@ } void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -126,7 +126,7 @@ INITIALIZE_PASS_BEGIN(HexagonGenPredicate, "hexagon-gen-pred", "Hexagon generate predicate operations", false, false) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_END(HexagonGenPredicate, "hexagon-gen-pred", "Hexagon generate predicate operations", false, false) diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp --- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -117,7 +117,7 @@ StringRef getPassName() const override { return "Hexagon Hardware Loops"; } void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.addRequired(); + AU.addRequired(); AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -365,7 +365,7 @@ INITIALIZE_PASS_BEGIN(HexagonHardwareLoops, "hwloops", "Hexagon Hardware Loops", false, false) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo) INITIALIZE_PASS_END(HexagonHardwareLoops, "hwloops", "Hexagon Hardware Loops", false, false) @@ -383,7 +383,7 @@ MLI = &getAnalysis(); MRI = &MF.getRegInfo(); - MDT = &getAnalysis(); + MDT = &getAnalysis().getMachineDominatorTree(); const HexagonSubtarget &HST = MF.getSubtarget(); TII = HST.getInstrInfo(); TRI = HST.getRegisterInfo(); diff --git a/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp b/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp --- a/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp +++ b/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp @@ -67,7 +67,7 @@ void getAnalysisUsage(AnalysisUsage &AU) const override { MachineFunctionPass::getAnalysisUsage(AU); - AU.addRequired(); + AU.addRequired(); AU.addRequired(); AU.setPreservesAll(); } @@ -117,7 +117,7 @@ INITIALIZE_PASS_BEGIN(HexagonOptAddrMode, "amode-opt", "Optimize addressing mode", false, false) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineDominanceFrontier) INITIALIZE_PASS_END(HexagonOptAddrMode, "amode-opt", "Optimize addressing mode", false, false) @@ -784,7 +784,7 @@ HII = HST.getInstrInfo(); HRI = HST.getRegisterInfo(); const auto &MDF = getAnalysis(); - MDT = &getAnalysis(); + MDT = &getAnalysis().getMachineDominatorTree(); const TargetOperandInfo TOI(*HII); DataFlowGraph G(MF, *HII, *HRI, *MDT, MDF, TOI); diff --git a/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp b/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp --- a/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp +++ b/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp @@ -57,7 +57,7 @@ HexagonRDFOpt() : MachineFunctionPass(ID) {} void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.addRequired(); + AU.addRequired(); AU.addRequired(); AU.setPreservesAll(); MachineFunctionPass::getAnalysisUsage(AU); @@ -103,7 +103,7 @@ INITIALIZE_PASS_BEGIN(HexagonRDFOpt, "hexagon-rdf-opt", "Hexagon RDF optimizations", false, false) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineDominanceFrontier) INITIALIZE_PASS_END(HexagonRDFOpt, "hexagon-rdf-opt", "Hexagon RDF optimizations", false, false) @@ -288,7 +288,7 @@ RDFCount++; } - MDT = &getAnalysis(); + MDT = &getAnalysis().getMachineDominatorTree(); const auto &MDF = getAnalysis(); const auto &HII = *MF.getSubtarget().getInstrInfo(); const auto &HRI = *MF.getSubtarget().getRegisterInfo(); diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -94,9 +94,9 @@ AU.setPreservesCFG(); AU.addRequired(); AU.addRequired(); - AU.addRequired(); + AU.addRequired(); AU.addRequired(); - AU.addPreserved(); + AU.addPreserved(); AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -121,7 +121,7 @@ INITIALIZE_PASS_BEGIN(HexagonPacketizer, "hexagon-packetizer", "Hexagon Packetizer", false, false) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo) INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass) diff --git a/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp b/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp --- a/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp +++ b/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp @@ -84,7 +84,7 @@ bool runOnMachineFunction(MachineFunction &F) override; void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.addRequired(); + AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -199,7 +199,7 @@ return false; // Do a pre-order traversal of the dominator tree. - MachineDominatorTree *MDT = &getAnalysis(); + MachineDominatorTree *MDT = &getAnalysis().getMachineDominatorTree(); bool Changed = false; SmallVector WorkList(1, MBBInfo(MDT->getRootNode())); diff --git a/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp b/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp --- a/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp +++ b/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp @@ -165,7 +165,7 @@ } void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.addRequired(); + AU.addRequired(); AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -195,7 +195,7 @@ INITIALIZE_PASS_BEGIN(PPCBranchCoalescing, DEBUG_TYPE, "Branch Coalescing", false, false) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTree) INITIALIZE_PASS_END(PPCBranchCoalescing, DEBUG_TYPE, "Branch Coalescing", false, false) @@ -214,7 +214,7 @@ } void PPCBranchCoalescing::initialize(MachineFunction &MF) { - MDT = &getAnalysis(); + MDT = &getAnalysis().getMachineDominatorTree(); MPDT = &getAnalysis(); TII = MF.getSubtarget().getInstrInfo(); MRI = &MF.getRegInfo(); diff --git a/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp b/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp --- a/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp +++ b/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp @@ -83,7 +83,7 @@ } void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.addRequired(); + AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -100,7 +100,7 @@ #ifndef NDEBUG INITIALIZE_PASS_BEGIN(PPCCTRLoopsVerify, "ppc-ctr-loops-verify", "PowerPC CTR Loops Verify", false, false) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_END(PPCCTRLoopsVerify, "ppc-ctr-loops-verify", "PowerPC CTR Loops Verify", false, false) @@ -195,7 +195,7 @@ } bool PPCCTRLoopsVerify::runOnMachineFunction(MachineFunction &MF) { - MDT = &getAnalysis(); + MDT = &getAnalysis().getMachineDominatorTree(); // Verify that all bdnz/bdz instructions are dominated by a loop mtctr before // any other instructions that might clobber the ctr register. diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp --- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp +++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp @@ -100,8 +100,8 @@ public: void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -118,7 +118,7 @@ void PPCMIPeephole::initialize(MachineFunction &MFParm) { MF = &MFParm; MRI = &MF->getRegInfo(); - MDT = &getAnalysis(); + MDT = &getAnalysis().getMachineDominatorTree(); TII = MF->getSubtarget().getInstrInfo(); LLVM_DEBUG(dbgs() << "*** PowerPC MI peephole pass ***\n\n"); LLVM_DEBUG(MF->dump()); diff --git a/llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp b/llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp --- a/llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp +++ b/llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp @@ -425,7 +425,7 @@ CRLogicalOpInfo createCRLogicalOpInfo(MachineInstr &MI); void getAnalysisUsage(AnalysisUsage &AU) const override { AU.addRequired(); - AU.addRequired(); + AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } }; @@ -727,7 +727,7 @@ INITIALIZE_PASS_BEGIN(PPCReduceCRLogicals, DEBUG_TYPE, "PowerPC Reduce CR logical Operation", false, false) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_END(PPCReduceCRLogicals, DEBUG_TYPE, "PowerPC Reduce CR logical Operation", false, false) diff --git a/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp b/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp --- a/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp +++ b/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp @@ -374,8 +374,8 @@ AU.addPreserved(); AU.addRequired(); AU.addPreserved(); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } }; @@ -385,7 +385,7 @@ "PowerPC VSX FMA Mutation", false, false) INITIALIZE_PASS_DEPENDENCY(LiveIntervals) INITIALIZE_PASS_DEPENDENCY(SlotIndexes) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_END(PPCVSXFMAMutate, DEBUG_TYPE, "PowerPC VSX FMA Mutation", false, false) diff --git a/llvm/lib/Target/SystemZ/SystemZLDCleanup.cpp b/llvm/lib/Target/SystemZ/SystemZLDCleanup.cpp --- a/llvm/lib/Target/SystemZ/SystemZLDCleanup.cpp +++ b/llvm/lib/Target/SystemZ/SystemZLDCleanup.cpp @@ -58,7 +58,7 @@ void SystemZLDCleanup::getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesCFG(); - AU.addRequired(); + AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -75,7 +75,7 @@ return false; } - MachineDominatorTree *DT = &getAnalysis(); + MachineDominatorTree *DT = &getAnalysis().getMachineDominatorTree(); return VisitNode(DT->getRootNode(), 0); } diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp --- a/llvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp @@ -115,8 +115,8 @@ void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); AU.addRequired(); AU.addPreserved(); AU.addRequired(); @@ -409,7 +409,7 @@ const auto &MLI = getAnalysis(); const auto &WEI = getAnalysis(); - auto &MDT = getAnalysis(); + auto &MDT = getAnalysis().getMachineDominatorTree(); // Liveness is not tracked for VALUE_STACK physreg. MF.getRegInfo().invalidateLiveness(); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp --- a/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp @@ -41,7 +41,7 @@ StringRef getPassName() const override { return "WebAssembly CFG Stackify"; } void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.addRequired(); + AU.addRequired(); AU.addRequired(); AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); @@ -208,7 +208,7 @@ void WebAssemblyCFGStackify::placeBlockMarker(MachineBasicBlock &MBB) { assert(!MBB.isEHPad()); MachineFunction &MF = *MBB.getParent(); - auto &MDT = getAnalysis(); + auto &MDT = getAnalysis().getMachineDominatorTree(); const auto &TII = *MF.getSubtarget().getInstrInfo(); const auto &MFI = *MF.getInfo(); @@ -438,7 +438,7 @@ void WebAssemblyCFGStackify::placeTryMarker(MachineBasicBlock &MBB) { assert(MBB.isEHPad()); MachineFunction &MF = *MBB.getParent(); - auto &MDT = getAnalysis(); + auto &MDT = getAnalysis().getMachineDominatorTree(); const auto &TII = *MF.getSubtarget().getInstrInfo(); const auto &WEI = getAnalysis(); const auto &MFI = *MF.getInfo(); @@ -1158,7 +1158,7 @@ } // Recompute the dominator tree. - getAnalysis().runOnMachineFunction(MF); + getAnalysis().runOnMachineFunction(MF); // Place block markers for newly added branches. SmallVector BrDests; diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyExceptionInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyExceptionInfo.cpp --- a/llvm/lib/Target/WebAssembly/WebAssemblyExceptionInfo.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyExceptionInfo.cpp @@ -26,7 +26,7 @@ INITIALIZE_PASS_BEGIN(WebAssemblyExceptionInfo, DEBUG_TYPE, "WebAssembly Exception Information", true, true) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(MachineDominanceFrontier) INITIALIZE_PASS_END(WebAssemblyExceptionInfo, DEBUG_TYPE, "WebAssembly Exception Information", true, true) @@ -36,7 +36,7 @@ "********** Function: " << MF.getName() << '\n'); releaseMemory(); - auto &MDT = getAnalysis(); + auto &MDT = getAnalysis().getMachineDominatorTree(); auto &MDF = getAnalysis(); recalculate(MDT, MDF); return false; @@ -87,7 +87,7 @@ void WebAssemblyExceptionInfo::getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesAll(); - AU.addRequired(); + AU.addRequired(); AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp --- a/llvm/lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp @@ -56,8 +56,8 @@ AU.setPreservesCFG(); AU.addRequired(); AU.addPreserved(); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); AU.addRequired(); AU.addPreserved(); AU.addPreserved(); @@ -181,7 +181,7 @@ }); MachineRegisterInfo &MRI = MF.getRegInfo(); - auto &MDT = getAnalysis(); + auto &MDT = getAnalysis().getMachineDominatorTree(); const WebAssemblyTargetLowering &TLI = *MF.getSubtarget().getTargetLowering(); const auto &LibInfo = getAnalysis().getTLI(); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp --- a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp @@ -49,13 +49,13 @@ void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); AU.addRequired(); - AU.addRequired(); + AU.addRequired(); AU.addRequired(); AU.addPreserved(); AU.addPreserved(); AU.addPreserved(); AU.addPreservedID(LiveVariablesID); - AU.addPreserved(); + AU.addPreserved(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -776,7 +776,7 @@ const auto *TII = MF.getSubtarget().getInstrInfo(); const auto *TRI = MF.getSubtarget().getRegisterInfo(); AliasAnalysis &AA = getAnalysis().getAAResults(); - auto &MDT = getAnalysis(); + auto &MDT = getAnalysis().getMachineDominatorTree(); auto &LIS = getAnalysis(); // Walk the instructions from the bottom up. Currently we don't look past diff --git a/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp b/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp --- a/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp +++ b/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp @@ -152,7 +152,7 @@ char X86FlagsCopyLoweringPass::ID = 0; void X86FlagsCopyLoweringPass::getAnalysisUsage(AnalysisUsage &AU) const { - AU.addRequired(); + AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -350,7 +350,7 @@ MRI = &MF.getRegInfo(); TII = Subtarget->getInstrInfo(); TRI = Subtarget->getRegisterInfo(); - MDT = &getAnalysis(); + MDT = &getAnalysis().getMachineDominatorTree(); PromoteRC = &X86::GR8RegClass; if (MF.begin() == MF.end()) diff --git a/llvm/lib/Target/X86/X86InsertPrefetch.cpp b/llvm/lib/Target/X86/X86InsertPrefetch.cpp --- a/llvm/lib/Target/X86/X86InsertPrefetch.cpp +++ b/llvm/lib/Target/X86/X86InsertPrefetch.cpp @@ -173,7 +173,7 @@ void X86InsertPrefetch::getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesAll(); - AU.addRequired(); + AU.addRequired(); } bool X86InsertPrefetch::runOnMachineFunction(MachineFunction &MF) { diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -7403,7 +7403,7 @@ return false; } - MachineDominatorTree *DT = &getAnalysis(); + MachineDominatorTree *DT = &getAnalysis().getMachineDominatorTree(); return VisitNode(DT->getRootNode(), 0); } @@ -7493,7 +7493,7 @@ void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); - AU.addRequired(); + AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } }; diff --git a/llvm/lib/Target/X86/X86RetpolineThunks.cpp b/llvm/lib/Target/X86/X86RetpolineThunks.cpp --- a/llvm/lib/Target/X86/X86RetpolineThunks.cpp +++ b/llvm/lib/Target/X86/X86RetpolineThunks.cpp @@ -58,8 +58,8 @@ void getAnalysisUsage(AnalysisUsage &AU) const override { MachineFunctionPass::getAnalysisUsage(AU); - AU.addRequired(); - AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); } private: @@ -97,7 +97,7 @@ TII = STI->getInstrInfo(); Is64Bit = TM->getTargetTriple().getArch() == Triple::x86_64; - MMI = &getAnalysis(); + MMI = &getAnalysis().getMMI(); Module &M = const_cast(*MMI->getModule()); // If this function is not a thunk, check to see if we need to insert diff --git a/llvm/tools/llc/CMakeLists.txt b/llvm/tools/llc/CMakeLists.txt --- a/llvm/tools/llc/CMakeLists.txt +++ b/llvm/tools/llc/CMakeLists.txt @@ -17,6 +17,7 @@ Target TransformUtils Vectorize + Passes ) # Support plugins. diff --git a/llvm/tools/llc/LLVMBuild.txt b/llvm/tools/llc/LLVMBuild.txt --- a/llvm/tools/llc/LLVMBuild.txt +++ b/llvm/tools/llc/LLVMBuild.txt @@ -18,4 +18,4 @@ type = Tool name = llc parent = Tools -required_libraries = AsmParser BitReader IRReader MIRParser TransformUtils Scalar Vectorize all-targets +required_libraries = AsmParser BitReader IRReader MIRParser TransformUtils Scalar Vectorize Passes all-targets diff --git a/llvm/tools/llc/llc.cpp b/llvm/tools/llc/llc.cpp --- a/llvm/tools/llc/llc.cpp +++ b/llvm/tools/llc/llc.cpp @@ -21,6 +21,7 @@ #include "llvm/CodeGen/MIRParser/MIRParser.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/CodeGen/PassManager.h" #include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/IR/AutoUpgrade.h" @@ -36,6 +37,7 @@ #include "llvm/IRReader/IRReader.h" #include "llvm/MC/SubtargetFeature.h" #include "llvm/Pass.h" +#include "llvm/Passes/PassBuilder.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/FileSystem.h" @@ -52,6 +54,12 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Transforms/Utils/Cloning.h" #include + +#include +#include +#include +#include +#include using namespace llvm; // General options for llc. Other pass-specific options are specified @@ -157,6 +165,8 @@ namespace { static ManagedStatic> RunPassNames; +static ManagedStatic> RunNewPassNames; + struct RunPassOption { void operator=(const std::string &Val) const { if (Val.empty()) @@ -167,6 +177,17 @@ RunPassNames->push_back(PassName); } }; + +struct RunNewPassOption { + void operator=(const std::string &Val) const { + if (Val.empty()) + return; + SmallVector PassNames; + StringRef(Val).split(PassNames, ',', -1, false); + for (auto PassName : PassNames) + RunNewPassNames->push_back(PassName); + } +}; } static RunPassOption RunPassOpt; @@ -176,6 +197,15 @@ cl::desc("Run compiler only for specified passes (comma separated list)"), cl::value_desc("pass-name"), cl::ZeroOrMore, cl::location(RunPassOpt)); +static RunNewPassOption RunNewPassOpt; + +static cl::opt> RunNewPass( + "run-new-pass", + cl::desc( + "Run compiler only for specified new passes (comma separated list)"), + cl::value_desc("new-pass-name"), cl::ZeroOrMore, + cl::location(RunNewPassOpt)); + static int compileModule(char **, LLVMContext &); static std::unique_ptr GetOutputStream(const char *TargetName, @@ -370,6 +400,16 @@ return 0; } +static bool addNewPass(ModulePassManager &PM, MachineFunctionPassManager &MFPM, + const char *argv0, StringRef PassName, TargetPassConfig &TPC) { + #define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS) \ + if (PassName == NAME) MFPM.addPass(CREATE_PASS); + #include "../../lib/Passes/PassRegistry.def" + std::string Banner = std::string("After ") + std::string("machine-cp"); + TPC.printAndVerify(Banner); + return false; +} + static bool addPass(PassManagerBase &PM, const char *argv0, StringRef PassName, TargetPassConfig &TPC) { if (PassName == "none") @@ -500,6 +540,36 @@ // Build up all of the passes that we want to do to the module. legacy::PassManager PM; + LLVMTargetMachine &LLVMTM = static_cast(*Target); + + PassInstrumentationCallbacks PIC; + PassBuilder PB(TheTarget->createTargetMachine( + TheTriple.getTriple(), CPUStr, FeaturesStr, Options, getRelocModel(), + getCodeModel(), OLvl)); + AAManager AA = PB.buildDefaultAAPipeline(); + MachineFunctionAnalysisManager MFAM; + FunctionAnalysisManager FAM; + ModuleAnalysisManager MAM; + + PB.registerModuleAnalyses(MAM); + PB.registerFunctionAnalyses(FAM); + MAM.registerPass([&] { return FunctionAnalysisManagerModuleProxy(FAM); }); + FAM.registerPass([&] { return ModuleAnalysisManagerFunctionProxy(MAM); }); + FAM.registerPass([&] { return MachineFunctionAnalysisManagerFunctionProxy(MFAM); }); + FAM.registerPass([&] { return AA; }); + MFAM.registerPass([&] { return FunctionAnalysisManagerMachineFunctionProxy(FAM); }); +#define MACHINE_FUNCTION_ANALYSIS(NAME, CREATE_PASS) \ + MFAM.registerPass([&] { return CREATE_PASS; }); + + MAM.registerPass([&] { return PassInstrumentationAnalysis(&PIC); }); + FAM.registerPass([&] { return PassInstrumentationAnalysis(&PIC); }); + MFAM.registerPass([&] { return PassInstrumentationAnalysis(&PIC); }); + +#include "../../lib/Passes/PassRegistry.def" + + ModulePassManager MPM; + MachineFunctionPassManager MFPM; + // Add an appropriate TargetLibraryInfo pass for the module's triple. TargetLibraryInfoImpl TLII(Triple(M->getTargetTriple())); @@ -508,6 +578,14 @@ TLII.disableAllFunctions(); PM.add(new TargetLibraryInfoWrapperPass(TLII)); + FAM.registerPass([&] { + return TargetLibraryAnalysis(TLII); }); + MAM.registerPass([&] { + return TargetLibraryAnalysis(TLII); }); + + MAM.registerPass([&] { + return MachineModuleAnalysis(&LLVMTM); }); + // Add the target data from the target machine, if it exists, or the module. M->setDataLayout(Target->createDataLayout()); @@ -548,8 +626,10 @@ } const char *argv0 = argv[0]; - LLVMTargetMachine &LLVMTM = static_cast(*Target); - MachineModuleInfo *MMI = new MachineModuleInfo(&LLVMTM); + MachineModuleInfoWrapperPass *MMIWP = + new MachineModuleInfoWrapperPass(&LLVMTM); + + const bool UsingNewPM = !RunNewPassNames->empty(); // Construct a custom pass pipeline that starts after instruction // selection. @@ -569,18 +649,30 @@ TPC.setDisableVerify(NoVerify); PM.add(&TPC); - PM.add(MMI); + PM.add(MMIWP); TPC.printAndVerify(""); for (const std::string &RunPassName : *RunPassNames) { if (addPass(PM, argv0, RunPassName, TPC)) return 1; } + for (const std::string &RunPassName : *RunNewPassNames) { + if (addNewPass(MPM, MFPM, argv0, RunPassName, TPC)) + return 1; + } TPC.setInitialized(); - PM.add(createPrintMIRPass(*OS)); + + if (UsingNewPM) + MPM.addPass(createModuleToFunctionPassAdaptor( + createFunctionToMachineFunctionPassAdaptor(std::move(MFPM)))); + + if (UsingNewPM) + MPM.addPass(MIRPrintingPass(*OS)); + else + PM.add(createPrintMIRPass(*OS)); PM.add(createFreeMachineFunctionPass()); } else if (Target->addPassesToEmitFile(PM, *OS, DwoOut ? &DwoOut->os() : nullptr, - FileType, NoVerify, MMI)) { + FileType, NoVerify, MMIWP)) { WithColor::warning(errs(), argv[0]) << "target does not support generation of this" << " file type!\n"; @@ -588,8 +680,13 @@ } if (MIR) { - assert(MMI && "Forgot to create MMI?"); - if (MIR->parseMachineFunctions(*M, *MMI)) + assert(MMIWP && "Forgot to create MMIWP?"); + if (UsingNewPM) { + if (MIR->parseMachineFunctions( + *M, MAM.getResult(*M))) + return 1; + } else + if (MIR->parseMachineFunctions(*M, MMIWP->getMMI())) return 1; } @@ -608,6 +705,12 @@ Buffer.clear(); } + // Now that we have all of the passes ready, run them. + { + PrettyStackTraceString CrashInfo("Optimizer"); + MPM.run(*M, MAM); + } + PM.run(*M); auto HasError = diff --git a/llvm/tools/llvm-exegesis/lib/Assembler.cpp b/llvm/tools/llvm-exegesis/lib/Assembler.cpp --- a/llvm/tools/llvm-exegesis/lib/Assembler.cpp +++ b/llvm/tools/llvm-exegesis/lib/Assembler.cpp @@ -143,10 +143,10 @@ createModule(Context, TM.createDataLayout()); // TODO: This only works for targets implementing LLVMTargetMachine. const LLVMTargetMachine &LLVMTM = static_cast(TM); - std::unique_ptr MMI = - llvm::make_unique(&LLVMTM); - llvm::MachineFunction &MF = - createVoidVoidPtrMachineFunction(FunctionID, Module.get(), MMI.get()); + std::unique_ptr MMIWP = + llvm::make_unique(&LLVMTM); + llvm::MachineFunction &MF = createVoidVoidPtrMachineFunction( + FunctionID, Module.get(), &MMIWP.get()->getMMI()); // Saving reserved registers for client. return MF.getSubtarget().getRegisterInfo()->getReservedRegs(MF); } @@ -161,10 +161,10 @@ llvm::make_unique(); std::unique_ptr Module = createModule(Context, TM->createDataLayout()); - std::unique_ptr MMI = - llvm::make_unique(TM.get()); - llvm::MachineFunction &MF = - createVoidVoidPtrMachineFunction(FunctionID, Module.get(), MMI.get()); + std::unique_ptr MMIWP = + llvm::make_unique(TM.get()); + llvm::MachineFunction &MF = createVoidVoidPtrMachineFunction( + FunctionID, Module.get(), &MMIWP.get()->getMMI()); // We need to instruct the passes that we're done with SSA and virtual // registers. @@ -195,7 +195,7 @@ fillMachineFunction(MF, LiveIns, Code); // We create the pass manager, run the passes to populate AsmBuffer. - llvm::MCContext &MCContext = MMI->getContext(); + llvm::MCContext &MCContext = MMIWP->getMMI().getContext(); llvm::legacy::PassManager PM; llvm::TargetLibraryInfoImpl TLII(llvm::Triple(Module->getTargetTriple())); @@ -203,7 +203,7 @@ llvm::TargetPassConfig *TPC = TM->createPassConfig(PM); PM.add(TPC); - PM.add(MMI.release()); + PM.add(MMIWP.release()); TPC->printAndVerify("MachineFunctionGenerator::assemble"); // Add target-specific passes. ET.addTargetSpecificPasses(PM); diff --git a/llvm/unittests/MI/LiveIntervalTest.cpp b/llvm/unittests/MI/LiveIntervalTest.cpp --- a/llvm/unittests/MI/LiveIntervalTest.cpp +++ b/llvm/unittests/MI/LiveIntervalTest.cpp @@ -63,10 +63,10 @@ M->setDataLayout(TM.createDataLayout()); - MachineModuleInfo *MMI = new MachineModuleInfo(&TM); - if (MIR->parseMachineFunctions(*M, *MMI)) + MachineModuleInfoWrapperPass *MMIWP = new MachineModuleInfoWrapperPass(&TM); + if (MIR->parseMachineFunctions(*M, MMIWP->getMMI())) return nullptr; - PM.add(MMI); + PM.add(MMIWP); return M; } diff --git a/llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp b/llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp --- a/llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp +++ b/llvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp @@ -165,9 +165,10 @@ ASSERT_TRUE(MF); WebAssemblyExceptionInfo WEI; - MachineDominatorTree MDT; + MachineDominatorTreeWrapperPass MDTWP; + MachineDominatorTree &MDT = MDTWP.getMachineDominatorTree(); MachineDominanceFrontier MDF; - MDT.runOnMachineFunction(*MF); + MDTWP.runOnMachineFunction(*MF); MDF.getBase().analyze(MDT.getBase()); WEI.recalculate(MDT, MDF); @@ -340,9 +341,10 @@ ASSERT_TRUE(MF); WebAssemblyExceptionInfo WEI; - MachineDominatorTree MDT; + MachineDominatorTreeWrapperPass MDTWP; + MachineDominatorTree &MDT = MDTWP.getMachineDominatorTree(); MachineDominanceFrontier MDF; - MDT.runOnMachineFunction(*MF); + MDTWP.runOnMachineFunction(*MF); MDF.getBase().analyze(MDT.getBase()); WEI.recalculate(MDT, MDF);