Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp =================================================================== --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -169,6 +169,9 @@ bool expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl &Instructions); + bool expandLoadStoreWordMMPseudo(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions); + void expandLoadAddressSym(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl &Instructions); @@ -1359,6 +1362,8 @@ case Mips::LoadAddr32Imm: case Mips::LoadAddr32Reg: case Mips::LoadImm64Reg: + case Mips::LW_MM_Pseudo: + case Mips::SW_MM_Pseudo: return true; default: return false; @@ -1383,6 +1388,9 @@ return expandLoadAddressImm(Inst, IDLoc, Instructions); case Mips::LoadAddr32Reg: return expandLoadAddressReg(Inst, IDLoc, Instructions); + case Mips::LW_MM_Pseudo: + case Mips::SW_MM_Pseudo: + return expandLoadStoreWordMMPseudo(Inst, IDLoc, Instructions); } } @@ -1668,6 +1676,50 @@ } } +bool MipsAsmParser:: +expandLoadStoreWordMMPseudo(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions) { + const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); + unsigned Opcode = Inst.getOpcode(); + MCOperand &Op = Inst.getOperand(2); + if (Op.isImm()) { + int MemOffset = Op.getImm(); + MCOperand &BaseReg = Inst.getOperand(1); + if (isIntN(7, MemOffset) && BaseReg.getReg() == Mips::SP) { + MCInst TmpInst; + MCOperand &DstReg = Inst.getOperand(0); + if (Opcode == Mips::LW) + TmpInst.setOpcode(Mips::LWSP_MM); + else + TmpInst.setOpcode(Mips::SWSP_MM); + TmpInst.addOperand(MCOperand::CreateReg(DstReg.getReg())); + TmpInst.addOperand(MCOperand::CreateReg(Mips::SP)); + TmpInst.addOperand(MCOperand::CreateImm(MemOffset)); + Instructions.push_back(TmpInst); + return false; + } else if (MemOffset < -32768 || MemOffset > 32767) { + // Offset can't exceed 16bit value. + expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), true); + return false; + } + } else if (Op.isExpr()) { + const MCExpr *Expr = Op.getExpr(); + if (Expr->getKind() == MCExpr::SymbolRef) { + const MCSymbolRefExpr *SR = + static_cast(Expr); + if (SR->getKind() == MCSymbolRefExpr::VK_None) { + // Expand symbol. + expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false); + return false; + } + } else if (!isEvaluated(Expr)) { + expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false); + return false; + } + } + return false; +} + void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl &Instructions, bool isLoad, bool isImmOpnd) { Index: lib/Target/Mips/Disassembler/MipsDisassembler.cpp =================================================================== --- lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -265,6 +265,11 @@ uint64_t Address, const void *Decoder); +static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, @@ -1187,6 +1192,22 @@ return MCDisassembler::Success; } +static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder) { + unsigned Offset = Insn & 0x1F; + unsigned Reg = fieldFromInstruction(Insn, 5, 5); + + Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); + + Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::CreateReg(Mips::SP)); + Inst.addOperand(MCOperand::CreateImm(Offset << 2)); + + return MCDisassembler::Success; +} + static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, Index: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h +++ lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h @@ -151,6 +151,9 @@ unsigned getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; + unsigned getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; Index: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -677,6 +677,20 @@ } unsigned MipsMCCodeEmitter:: +getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + // Register is encoded in bits 9-5, offset is encoded in bits 4-0. + assert(MI.getOperand(OpNo).isReg() && + MI.getOperand(OpNo).getReg() == Mips::SP && + "Unexpected base register!"); + unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), + Fixups, STI) >> 2; + + return OffBits & 0x1F; +} + +unsigned MipsMCCodeEmitter:: getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { Index: lib/Target/Mips/MicroMipsInstrFormats.td =================================================================== --- lib/Target/Mips/MicroMipsInstrFormats.td +++ lib/Target/Mips/MicroMipsInstrFormats.td @@ -120,6 +120,17 @@ let Inst{3-0} = addr{3-0}; } +class LOAD_STORE_SP_FM_MM16 op> { + bits<5> rt; + bits<5> offset; + + bits<16> Inst; + + let Inst{15-10} = op; + let Inst{9-5} = rt; + let Inst{4-0} = offset; +} + class ADDIUS5_FM_MM16 { bits<5> rd; bits<4> imm; Index: lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- lib/Target/Mips/MicroMipsInstrInfo.td +++ lib/Target/Mips/MicroMipsInstrInfo.td @@ -78,6 +78,21 @@ let EncoderMethod = "getMemEncodingMMImm4Lsl2"; } +def MicroMipsMemSPAsmOperand : AsmOperandClass { + let Name = "MicroMipsMemSP"; + let RenderMethod = "addMemOperands"; + let ParserMethod = "parseMemOperand"; + let PredicateMethod = "isMemWithUimmOffsetSP<7>"; +} + +def mem_mm_sp_imm5_lsl2 : Operand { + let PrintMethod = "printMemOperand"; + let MIOperandInfo = (ops GPR32:$base, simm5:$offset); + let OperandType = "OPERAND_MEMORY"; + let ParserMatchClass = MicroMipsMemSPAsmOperand; + let EncoderMethod = "getMemEncodingMMSPImm5Lsl2"; +} + def mem_mm_12 : Operand { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops GPR32, simm12); @@ -222,6 +237,23 @@ let mayStore = 1; } +class LoadSPMM16 : + MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset), + !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> { + let DecoderMethod = "DecodeMemMMSPImm5Lsl2"; + let canFoldAsLoad = 1; + let mayLoad = 1; +} + +class StoreSPMM16 : + MicroMipsInst16<(outs), (ins RO:$rt, MemOpnd:$offset), + !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> { + let DecoderMethod = "DecodeMemMMSPImm5Lsl2"; + let mayStore = 1; +} + class AddImmUR2 : MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm), !strconcat(opstr, "\t$rd, $rs, $imm"), @@ -430,6 +462,10 @@ LOAD_STORE_FM_MM16<0x2a>; def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW, mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>; +def LWSP_MM : LoadSPMM16<"lw", GPR32Opnd, II_LW, mem_mm_sp_imm5_lsl2>, + LOAD_STORE_SP_FM_MM16<0x12>; +def SWSP_MM : StoreSPMM16<"sw", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>, + LOAD_STORE_SP_FM_MM16<0x32>; def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16; def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16; def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16; @@ -709,5 +745,13 @@ // MicroMips instruction aliases //===----------------------------------------------------------------------===// +class LoadStoreWordMMPseudo : + MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$offset), + !strconcat(instr_asm, "\t$rt, $offset")>; + +def LW_MM_Pseudo : LoadStoreWordMMPseudo<"lw", mem, GPR32Opnd>; +def SW_MM_Pseudo : LoadStoreWordMMPseudo<"sw", mem, GPR32Opnd>; + def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>; } Index: test/MC/Disassembler/Mips/micromips.txt =================================================================== --- test/MC/Disassembler/Mips/micromips.txt +++ test/MC/Disassembler/Mips/micromips.txt @@ -408,3 +408,9 @@ # CHECK: addius5 $7, -2 0x4c 0xfc + +# CHECK: lw $3, 32($sp) +0x48 0x68 + +# CHECK: sw $4, 124($sp) +0xc8 0x9f Index: test/MC/Disassembler/Mips/micromips_le.txt =================================================================== --- test/MC/Disassembler/Mips/micromips_le.txt +++ test/MC/Disassembler/Mips/micromips_le.txt @@ -408,3 +408,9 @@ # CHECK: addius5 $7, -2 0xfc 0x4c + +# CHECK: lw $3, 32($sp) +0x68 0x48 + +# CHECK: sw $4, 124($sp) +0x9f 0xc8 Index: test/MC/Mips/micromips-16-bit-instructions.s =================================================================== --- test/MC/Mips/micromips-16-bit-instructions.s +++ test/MC/Mips/micromips-16-bit-instructions.s @@ -26,6 +26,8 @@ # CHECK-EL: sh16 $4, 8($17) # encoding: [0x14,0xaa] # CHECK-EL: sw16 $4, 4($17) # encoding: [0x11,0xea] # CHECK-EL: sw16 $zero, 4($17) # encoding: [0x11,0xe8] +# CHECK-EL: lw $3, 32($sp) # encoding: [0x68,0x48] +# CHECK-EL: sw $4, 124($sp) # encoding: [0x9f,0xc8] # CHECK-EL: li16 $3, -1 # encoding: [0xff,0xed] # CHECK-EL: li16 $3, 126 # encoding: [0xfe,0xed] # CHECK-EL: addiur1sp $7, 4 # encoding: [0x83,0x6f] @@ -65,6 +67,8 @@ # CHECK-EB: sh16 $4, 8($17) # encoding: [0xaa,0x14] # CHECK-EB: sw16 $4, 4($17) # encoding: [0xea,0x11] # CHECK-EB: sw16 $zero, 4($17) # encoding: [0xe8,0x11] +# CHECK-EB: lw $3, 32($sp) # encoding: [0x48,0x68] +# CHECK-EB: sw $4, 124($sp) # encoding: [0xc8,0x9f] # CHECK-EB: li16 $3, -1 # encoding: [0xed,0xff] # CHECK-EB: li16 $3, 126 # encoding: [0xed,0xfe] # CHECK-EB: addiur1sp $7, 4 # encoding: [0x6f,0x83] @@ -102,6 +106,8 @@ sh16 $4, 8($17) sw16 $4, 4($17) sw16 $0, 4($17) + lw $3, 32($sp) + sw $4, 124($sp) li16 $3, -1 li16 $3, 126 addiur1sp $7, 4