Index: llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -3665,7 +3665,11 @@
   else if (Root.isCImm())
     Immed = Root.getCImm()->getZExtValue();
   else if (Root.isReg()) {
-    MachineInstr *Def = MRI.getVRegDef(Root.getReg());
+    auto ValAndVReg =
+        getConstantVRegValWithLookThrough(Root.getReg(), MRI, true);
+    if (!ValAndVReg)
+      return None;
+    MachineInstr *Def = MRI.getVRegDef(ValAndVReg->VReg);
     if (Def->getOpcode() != TargetOpcode::G_CONSTANT)
       return None;
     MachineOperand &Op1 = Def->getOperand(1);
Index: llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir
@@ -70,3 +70,24 @@
     RET_ReallyLR implicit $w0
 
 ...
+---
+name:            cmp_imm_lookthrough
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1:
+    liveins: $w0
+    ; CHECK-LABEL: name: cmp_imm_lookthrough
+    ; CHECK: liveins: $w0
+    ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
+    ; CHECK: $wzr = SUBSWri [[COPY]], 42, 0, implicit-def $nzcv
+    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
+    ; CHECK: $w0 = COPY [[CSINCWr]]
+    ; CHECK: RET_ReallyLR implicit $w0
+    %0:gpr(s32) = COPY $w0
+    %1:gpr(s64) = G_CONSTANT i64 42
+    %2:gpr(s32) = G_TRUNC %1(s64)
+    %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2
+    $w0 = COPY %5(s32)
+    RET_ReallyLR implicit $w0