diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -1059,5 +1059,84 @@ return diagnoseRegisterClass(YamlMFI.StackPtrOffsetReg); } + auto parseAndCheckArgument = [&](const Optional &A, + const TargetRegisterClass &RC, + ArgDescriptor &Arg) { + // Skip parsing if it's not present. + if (!A) + return false; + + if (A->IsRegister) { + unsigned Reg; + if (parseNamedRegisterReference(PFS, Reg, A->RegisterName.Value, + Error)) { + SourceRange = A->RegisterName.SourceRange; + return true; + } + if (!RC.contains(Reg)) + return diagnoseRegisterClass(A->RegisterName); + Arg = ArgDescriptor::createRegister(Reg); + } else + Arg = ArgDescriptor::createStack(A->StackOffset); + // Check and apply the optional mask. + if (A->Mask) + Arg = ArgDescriptor::createArg(Arg, A->Mask.getValue()); + + return false; + }; + + if (YamlMFI.ArgInfo && + (parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer, + AMDGPU::SReg_128RegClass, + MFI->ArgInfo.PrivateSegmentBuffer) || + parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr, + AMDGPU::SReg_64RegClass, + MFI->ArgInfo.DispatchPtr) || + parseAndCheckArgument(YamlMFI.ArgInfo->QueuePtr, AMDGPU::SReg_64RegClass, + MFI->ArgInfo.QueuePtr) || + parseAndCheckArgument(YamlMFI.ArgInfo->KernargSegmentPtr, + AMDGPU::SReg_64RegClass, + MFI->ArgInfo.KernargSegmentPtr) || + parseAndCheckArgument(YamlMFI.ArgInfo->DispatchID, + AMDGPU::SReg_64RegClass, + MFI->ArgInfo.DispatchID) || + parseAndCheckArgument(YamlMFI.ArgInfo->FlatScratchInit, + AMDGPU::SReg_64RegClass, + MFI->ArgInfo.FlatScratchInit) || + parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentSize, + AMDGPU::SGPR_32RegClass, + MFI->ArgInfo.PrivateSegmentSize) || + parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDX, + AMDGPU::SGPR_32RegClass, + MFI->ArgInfo.WorkGroupIDX) || + parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDY, + AMDGPU::SGPR_32RegClass, + MFI->ArgInfo.WorkGroupIDY) || + parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupIDZ, + AMDGPU::SGPR_32RegClass, + MFI->ArgInfo.WorkGroupIDZ) || + parseAndCheckArgument(YamlMFI.ArgInfo->WorkGroupInfo, + AMDGPU::SGPR_32RegClass, + MFI->ArgInfo.WorkGroupInfo) || + parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentWaveByteOffset, + AMDGPU::SGPR_32RegClass, + MFI->ArgInfo.PrivateSegmentWaveByteOffset) || + parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitArgPtr, + AMDGPU::SReg_64RegClass, + MFI->ArgInfo.ImplicitArgPtr) || + parseAndCheckArgument(YamlMFI.ArgInfo->ImplicitBufferPtr, + AMDGPU::SReg_64RegClass, + MFI->ArgInfo.ImplicitBufferPtr) || + parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDX, + AMDGPU::VGPR_32RegClass, + MFI->ArgInfo.WorkItemIDX) || + parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDY, + AMDGPU::VGPR_32RegClass, + MFI->ArgInfo.WorkItemIDY) || + parseAndCheckArgument(YamlMFI.ArgInfo->WorkItemIDZ, + AMDGPU::VGPR_32RegClass, + MFI->ArgInfo.WorkItemIDZ))) + return true; + return false; } diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h @@ -114,6 +114,117 @@ namespace yaml { +struct SIArgument { + bool IsRegister; + union { + StringValue RegisterName; + unsigned StackOffset; + }; + Optional Mask; + + // Default constructor, which creates a stack argument. + SIArgument() : IsRegister(false), StackOffset(0) {} + SIArgument(const SIArgument &Other) { + IsRegister = Other.IsRegister; + if (IsRegister) + ::new ((void *)std::addressof(RegisterName)) + StringValue(Other.RegisterName); + else + StackOffset = Other.StackOffset; + Mask = Other.Mask; + } + SIArgument &operator=(const SIArgument &Other) { + IsRegister = Other.IsRegister; + if (IsRegister) + ::new ((void *)std::addressof(RegisterName)) + StringValue(Other.RegisterName); + else + StackOffset = Other.StackOffset; + Mask = Other.Mask; + return *this; + } + ~SIArgument() { + if (IsRegister) + RegisterName.~StringValue(); + } + + // Helper to create a register or stack argument. + static inline SIArgument createArgument(bool IsReg) { + if (IsReg) + return SIArgument(IsReg); + return SIArgument(); + } + +private: + // Construct a register argument. + SIArgument(bool) : IsRegister(true), RegisterName() {} +}; + +template <> struct MappingTraits { + static void mapping(IO &YamlIO, SIArgument &A) { + YamlIO.mapRequired("isReg", A.IsRegister); + if (A.IsRegister) { + // When inputting, re-create the register argument with a valid register + // name field. + if (!YamlIO.outputting()) + A = SIArgument::createArgument(A.IsRegister); + YamlIO.mapRequired("reg", A.RegisterName); + } else + YamlIO.mapRequired("offset", A.StackOffset); + YamlIO.mapOptional("mask", A.Mask); + } + static const bool flow = true; +}; + +struct SIArgumentInfo { + Optional PrivateSegmentBuffer; + Optional DispatchPtr; + Optional QueuePtr; + Optional KernargSegmentPtr; + Optional DispatchID; + Optional FlatScratchInit; + Optional PrivateSegmentSize; + + Optional WorkGroupIDX; + Optional WorkGroupIDY; + Optional WorkGroupIDZ; + Optional WorkGroupInfo; + Optional PrivateSegmentWaveByteOffset; + + Optional ImplicitArgPtr; + Optional ImplicitBufferPtr; + + Optional WorkItemIDX; + Optional WorkItemIDY; + Optional WorkItemIDZ; +}; + +template <> struct MappingTraits { + static void mapping(IO &YamlIO, SIArgumentInfo &AI) { + YamlIO.mapOptional("privateSegmentBuffer", AI.PrivateSegmentBuffer); + YamlIO.mapOptional("dispatchPtr", AI.DispatchPtr); + YamlIO.mapOptional("queuePtr", AI.QueuePtr); + YamlIO.mapOptional("kernargSegmentPtr", AI.KernargSegmentPtr); + YamlIO.mapOptional("dispatchID", AI.DispatchID); + YamlIO.mapOptional("flatScratchInit", AI.FlatScratchInit); + YamlIO.mapOptional("privateSegmentSize", AI.PrivateSegmentSize); + + YamlIO.mapOptional("workGroupIDX", AI.WorkGroupIDX); + YamlIO.mapOptional("workGroupIDY", AI.WorkGroupIDY); + YamlIO.mapOptional("workGroupIDZ", AI.WorkGroupIDZ); + YamlIO.mapOptional("workGroupInfo", AI.WorkGroupInfo); + YamlIO.mapOptional("privateSegmentWaveByteOffset", + AI.PrivateSegmentWaveByteOffset); + + YamlIO.mapOptional("implicitArgPtr", AI.ImplicitArgPtr); + YamlIO.mapOptional("implicitBufferPtr", AI.ImplicitBufferPtr); + + YamlIO.mapOptional("workItemIDX", AI.WorkItemIDX); + YamlIO.mapOptional("workItemIDY", AI.WorkItemIDY); + YamlIO.mapOptional("workItemIDZ", AI.WorkItemIDZ); + } +}; + struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo { uint64_t ExplicitKernArgSize = 0; unsigned MaxKernArgAlign = 0; @@ -128,6 +239,8 @@ StringValue FrameOffsetReg = "$fp_reg"; StringValue StackPtrOffsetReg = "$sp_reg"; + Optional ArgInfo; + SIMachineFunctionInfo() = default; SIMachineFunctionInfo(const llvm::SIMachineFunctionInfo &, const TargetRegisterInfo &TRI); @@ -154,6 +267,7 @@ StringValue("$fp_reg")); YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg, StringValue("$sp_reg")); + YamlIO.mapOptional("argumentInfo", MFI.ArgInfo); } }; diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -324,6 +324,57 @@ return Dest; } +static Optional +convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo, + const TargetRegisterInfo &TRI) { + yaml::SIArgumentInfo AI; + + auto convertArg = [&](Optional &A, + const ArgDescriptor &Arg) { + if (!Arg) + return false; + + // Create a register or stack argument. + yaml::SIArgument SA = yaml::SIArgument::createArgument(Arg.isRegister()); + if (Arg.isRegister()) { + raw_string_ostream OS(SA.RegisterName.Value); + OS << printReg(Arg.getRegister(), &TRI); + } else + SA.StackOffset = Arg.getStackOffset(); + // Check and update the optional mask. + if (Arg.isMasked()) + SA.Mask = Arg.getMask(); + + A = SA; + return true; + }; + + bool Any = false; + Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer); + Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr); + Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr); + Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr); + Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID); + Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit); + Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize); + Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX); + Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY); + Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ); + Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo); + Any |= convertArg(AI.PrivateSegmentWaveByteOffset, + ArgInfo.PrivateSegmentWaveByteOffset); + Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr); + Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr); + Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX); + Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY); + Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ); + + if (Any) + return AI; + + return None; +} + yaml::SIMachineFunctionInfo::SIMachineFunctionInfo( const llvm::SIMachineFunctionInfo& MFI, const TargetRegisterInfo &TRI) @@ -337,7 +388,8 @@ ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)), ScratchWaveOffsetReg(regToString(MFI.getScratchWaveOffsetReg(), TRI)), FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)), - StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)) {} + StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)), + ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)) {} void yaml::SIMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) { MappingTraits::mapping(YamlIO, *this); diff --git a/llvm/test/CodeGen/AMDGPU/hazard-hidden-bundle.mir b/llvm/test/CodeGen/AMDGPU/hazard-hidden-bundle.mir --- a/llvm/test/CodeGen/AMDGPU/hazard-hidden-bundle.mir +++ b/llvm/test/CodeGen/AMDGPU/hazard-hidden-bundle.mir @@ -3,6 +3,7 @@ # RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-WavefrontSize32,+WavefrontSize64 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,NOXNACK,GFX10 %s # GCN-LABEL: name: break_smem_clause_simple_load_smrd8_ptr_hidden_bundle +# GCN: bb.0: # GCN: } # XNACK-NEXT: S_NOP # NOXNACK-NOT: S_NOP diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir --- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir @@ -16,6 +16,12 @@ # FULL-NEXT: scratchWaveOffsetReg: '$sgpr12' # FULL-NEXT: frameOffsetReg: '$sgpr12' # FULL-NEXT: stackPtrOffsetReg: '$sgpr13' +# FULL-NEXT: argumentInfo: +# FULL-NEXT: privateSegmentBuffer: { isReg: true, reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } +# FULL-NEXT: kernargSegmentPtr: { isReg: true, reg: '$sgpr4_sgpr5' } +# FULL-NEXT: workGroupIDX: { isReg: true, reg: '$sgpr6' } +# FULL-NEXT: privateSegmentWaveByteOffset: { isReg: true, reg: '$sgpr7' } +# FULL-NEXT: workItemIDX: { isReg: true, reg: '$vgpr0' } # FULL-NEXT: body: # SIMPLE: machineFunctionInfo: @@ -29,6 +35,12 @@ # SIMPLE-NEXT: scratchWaveOffsetReg: '$sgpr12' # SIMPLE-NEXT: frameOffsetReg: '$sgpr12' # SIMPLE-NEXT: stackPtrOffsetReg: '$sgpr13' +# SIMPLE-NEXT: argumentInfo: +# SIMPLE-NEXT: privateSegmentBuffer: { isReg: true, reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } +# SIMPLE-NEXT: kernargSegmentPtr: { isReg: true, reg: '$sgpr4_sgpr5' } +# SIMPLE-NEXT: workGroupIDX: { isReg: true, reg: '$sgpr6' } +# SIMPLE-NEXT: privateSegmentWaveByteOffset: { isReg: true, reg: '$sgpr7' } +# SIMPLE-NEXT: workItemIDX: { isReg: true, reg: '$vgpr0' } # SIMPLE-NEXT: body: name: kernel0 machineFunctionInfo: @@ -43,6 +55,12 @@ scratchWaveOffsetReg: '$sgpr12' frameOffsetReg: '$sgpr12' stackPtrOffsetReg: '$sgpr13' + argumentInfo: + privateSegmentBuffer: { isReg: true, reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } + kernargSegmentPtr: { isReg: true, reg: '$sgpr4_sgpr5' } + workGroupIDX: { isReg: true, reg: '$sgpr6' } + privateSegmentWaveByteOffset: { isReg: true, reg: '$sgpr7' } + workItemIDX: { isReg: true, reg: '$vgpr0' } body: | bb.0: S_ENDPGM 0 @@ -64,8 +82,15 @@ # FULL-NEXT: scratchWaveOffsetReg: '$scratch_wave_offset_reg' # FULL-NEXT: frameOffsetReg: '$fp_reg' # FULL-NEXT: stackPtrOffsetReg: '$sp_reg' +# FULL-NEXT: argumentInfo: +# FULL-NEXT: privateSegmentBuffer: { isReg: true, reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } +# FULL-NEXT: privateSegmentWaveByteOffset: { isReg: true, reg: '$sgpr33' } +# FULL-NEXT: body: # SIMPLE: machineFunctionInfo: +# SIMPLE-NEXT: argumentInfo: +# SIMPLE-NEXT: privateSegmentBuffer: { isReg: true, reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } +# SIMPLE-NEXT: privateSegmentWaveByteOffset: { isReg: true, reg: '$sgpr33' } # SIMPLE-NEXT: body: name: no_mfi @@ -89,8 +114,15 @@ # FULL-NEXT: scratchWaveOffsetReg: '$scratch_wave_offset_reg' # FULL-NEXT: frameOffsetReg: '$fp_reg' # FULL-NEXT: stackPtrOffsetReg: '$sp_reg' +# FULL-NEXT: argumentInfo: +# FULL-NEXT: privateSegmentBuffer: { isReg: true, reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } +# FULL-NEXT: privateSegmentWaveByteOffset: { isReg: true, reg: '$sgpr33' } +# FULL-NEXT: body: # SIMPLE: machineFunctionInfo: +# SIMPLE-NEXT: argumentInfo: +# SIMPLE-NEXT: privateSegmentBuffer: { isReg: true, reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } +# SIMPLE-NEXT: privateSegmentWaveByteOffset: { isReg: true, reg: '$sgpr33' } # SIMPLE-NEXT: body: name: empty_mfi @@ -115,9 +147,16 @@ # FULL-NEXT: scratchWaveOffsetReg: '$scratch_wave_offset_reg' # FULL-NEXT: frameOffsetReg: '$fp_reg' # FULL-NEXT: stackPtrOffsetReg: '$sp_reg' +# FULL-NEXT: argumentInfo: +# FULL-NEXT: privateSegmentBuffer: { isReg: true, reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } +# FULL-NEXT: privateSegmentWaveByteOffset: { isReg: true, reg: '$sgpr33' } +# FULL-NEXT: body: # SIMPLE: machineFunctionInfo: # SIMPLE-NEXT: isEntryFunction: true +# SIMPLE-NEXT: argumentInfo: +# SIMPLE-NEXT: privateSegmentBuffer: { isReg: true, reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } +# SIMPLE-NEXT: privateSegmentWaveByteOffset: { isReg: true, reg: '$sgpr33' } # SIMPLE-NEXT: body: name: empty_mfi_entry_func @@ -149,3 +188,29 @@ S_ENDPGM 0 ... + +--- +# ALL-LABEL: name: fake_stack_arginfo + +# FULL: argumentInfo: +# FULL-NEXT: privateSegmentBuffer: { isReg: true, reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } +# FULL-NEXT: flatScratchInit: { isReg: false, offset: 4 } +# FULL-NEXT: privateSegmentWaveByteOffset: { isReg: true, reg: '$sgpr33' } +# FULL-NEXT: workItemIDY: { isReg: true, reg: '$vgpr0', mask: 65280 } + +# SIMPLE: argumentInfo: +# SIMPLE-NEXT: privateSegmentBuffer: { isReg: true, reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } +# SIMPLE-NEXT: flatScratchInit: { isReg: false, offset: 4 } +# SIMPLE-NEXT: privateSegmentWaveByteOffset: { isReg: true, reg: '$sgpr33' } +# SIMPLE-NEXT: workItemIDY: { isReg: true, reg: '$vgpr0', mask: 65280 } +name: fake_stack_arginfo +machineFunctionInfo: + argumentInfo: + flatScratchInit: { isReg: false, offset: 4 } + workItemIDY: { isReg: true, reg: '$vgpr0' , mask: 0xff00 } + +body: | + bb.0: + S_ENDPGM 0 + +... diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll --- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll +++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll @@ -19,6 +19,12 @@ ; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr101' ; CHECK-NEXT: frameOffsetReg: '$sgpr101' ; CHECK-NEXT: stackPtrOffsetReg: '$sgpr101' +; CHECK-NEXT: argumentInfo: +; CHECK-NEXT: privateSegmentBuffer: { isReg: true, reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } +; CHECK-NEXT: kernargSegmentPtr: { isReg: true, reg: '$sgpr4_sgpr5' } +; CHECK-NEXT: workGroupIDX: { isReg: true, reg: '$sgpr6' } +; CHECK-NEXT: privateSegmentWaveByteOffset: { isReg: true, reg: '$sgpr7' } +; CHECK-NEXT: workItemIDX: { isReg: true, reg: '$vgpr0' } ; CHECK-NEXT: body: define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) { %gep = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %arg0 @@ -39,6 +45,9 @@ ; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr101' ; CHECK-NEXT: frameOffsetReg: '$sgpr101' ; CHECK-NEXT: stackPtrOffsetReg: '$sgpr101' +; CHECK-NEXT: argumentInfo: +; CHECK-NEXT: privateSegmentWaveByteOffset: { isReg: true, reg: '$sgpr3' } +; CHECK-NEXT: implicitBufferPtr: { isReg: true, reg: '$sgpr0_sgpr1' } ; CHECK-NEXT: body: define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) { ret void @@ -57,6 +66,9 @@ ; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr33' ; CHECK-NEXT: frameOffsetReg: '$sgpr5' ; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' +; CHECK-NEXT: argumentInfo: +; CHECK-NEXT: privateSegmentBuffer: { isReg: true, reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } +; CHECK-NEXT: privateSegmentWaveByteOffset: { isReg: true, reg: '$sgpr33' } ; CHECK-NEXT: body: define void @function() { ret void @@ -75,6 +87,9 @@ ; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr33' ; CHECK-NEXT: frameOffsetReg: '$sgpr5' ; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' +; CHECK-NEXT: argumentInfo: +; CHECK-NEXT: privateSegmentBuffer: { isReg: true, reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } +; CHECK-NEXT: privateSegmentWaveByteOffset: { isReg: true, reg: '$sgpr33' } ; CHECK-NEXT: body: define void @function_nsz() #0 { ret void