Index: llvm/lib/CodeGen/MachineVerifier.cpp
===================================================================
--- llvm/lib/CodeGen/MachineVerifier.cpp
+++ llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1611,14 +1611,24 @@
     const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
     // Don't check if it's the last operand in a variadic instruction. See,
     // e.g., LDM_RET in the arm back end.
-    if (MO->isReg() &&
-        !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) {
+    bool IsOptional = (MI->isVariadic() && MONum == MCID.getNumOperands() - 1);
+    if (MO->isReg() && !IsOptional) {
       if (MO->isDef() && !MCOI.isOptionalDef())
         report("Explicit operand marked as def", MO, MONum);
       if (MO->isImplicit())
         report("Explicit operand marked as implicit", MO, MONum);
     }
 
+    // Check that an instruction has register operands only as expected.
+    if (!IsOptional) {
+      if (MCOI.OperandType == MCOI::OPERAND_REGISTER &&
+          (!MO->isReg() && !MO->isFI()))
+        report("Expected a register operand.", MO, MONum);
+      if ((MCOI.OperandType == MCOI::OPERAND_IMMEDIATE ||
+           MCOI.OperandType == MCOI::OPERAND_PCREL) && MO->isReg())
+        report("Expected a non-register operand.", MO, MONum);
+    }
+
     int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
     if (TiedTo != -1) {
       if (!MO->isReg())
Index: llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
@@ -1,5 +1,13 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple=aarch64-unknown-unknown -verify-machineinstrs -run-pass=legalizer %s -o - | FileCheck %s
+
+# XFAIL: *
+# *** Bad machine code: Expected a register operand. ***
+# - function:    snork
+# - basic block: %bb.3 bb10 (0x63497a8)
+# - instruction: RET 0
+# - operand 0:   0
+
 --- |
   target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
 
Index: llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir
===================================================================
--- llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir
+++ llvm/test/CodeGen/Hexagon/expand-condsets-phys-reg.mir
@@ -1,6 +1,13 @@
 # RUN: llc -march=hexagon -run-pass expand-condsets %s -o - | FileCheck %s
 # REQUIRES: asserts
 
+# XFAIL: *
+# *** Bad machine code: Expected a register operand. ***
+# - function:    fred
+# - basic block: %bb.0  (0x6325888)
+# - instruction: %1:predregs = C2_cmplt %0:intregs, 10
+# - operand 2:   10
+
 # The physical register as an operand to C2_mux caused a crash.
 # Check that this compiles successfully and that the mux is expanded.
 
Index: llvm/test/CodeGen/Hexagon/sdr-global.mir
===================================================================
--- llvm/test/CodeGen/Hexagon/sdr-global.mir
+++ llvm/test/CodeGen/Hexagon/sdr-global.mir
@@ -1,5 +1,12 @@
 # RUN: llc -march=hexagon -run-pass hexagon-split-double %s -o - | FileCheck %s
 
+# XFAIL: *
+# *** Bad machine code: Expected a register operand. ***
+# - function:    fred
+# - basic block: %bb.0  (0x6325c88)
+# - instruction: %0:doubleregs = A4_combineir 0, @g0
+# - operand 2:   @g0
+
 # This used to crash because the constant operand was not an immediate.
 # Make sure we can handle such a case.
 
Index: llvm/test/MachineVerifier/verify-regops.mir
===================================================================
--- /dev/null
+++ llvm/test/MachineVerifier/verify-regops.mir
@@ -0,0 +1,37 @@
+# RUN: not llc -march=x86 -o - %s -run-pass=none -verify-machineinstrs \
+# RUN:   2>&1 | FileCheck %s
+# REQUIRES: x86-registered-target
+#
+# Check that MachineVerifier catches corrupt operands where MO->isReg()
+# returns true, but the descriptor says it should be an OPERAND_IMMEDIATE or
+# OPERAND_PCREL. Conversely, if MO->isReg() (and MO->isFI()) returns false,
+# check that not an OPERAND_REGISTER is expected.
+
+# CHECK-LABEL: fun
+
+# CHECK: *** Bad machine code: Expected a register operand. ***
+# CHECK: - instruction: %1:gr32 = XOR32rm -1, %fixed-stack.1, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load 4 from %fixed-stack.1, align 8)
+# CHECK: - operand 1:   -1
+
+# CHECK: *** Bad machine code: Expected a non-register operand. ***
+# CHECK: - instruction: %2:gr32 = OR32ri %1:gr32(tied-def 0), %0:gr32, implicit-def dead $eflags
+# CHECK: - operand 2:   %0:gr32
+
+
+name:            fun
+tracksRegLiveness: true
+fixedStack:
+  - { id: 1, offset: 8, size: 4, alignment: 8, isImmutable: true }
+  - { id: 3, size: 4, alignment: 16, isImmutable: true }
+body:             |
+  bb.0:
+    %0:gr32 = MOV32rm %fixed-stack.3, 1, $noreg, 0, $noreg :: (load 4 from %fixed-stack.3, align 16)
+    ; Was: %1:gr32 = XOR32rm %0, %fixed-stack.1, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load 4 from %fixed-stack.1, align 8)
+    %1:gr32 = XOR32rm -1, %fixed-stack.1, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load 4 from %fixed-stack.1, align 8)
+    ; Was: %2:gr32 = OR32ri %1, -256, implicit-def dead $eflags
+    %2:gr32 = OR32ri %1, %0, implicit-def dead $eflags
+    %3:gr32 = MOV32ri -1
+    $eax = COPY %2
+    $edx = COPY %3
+    RET 0, $eax, $edx
+...