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Differential D63939

[UpdateTestChecks] [ARM] Add support for armv7-apple-darwin
ClosedPublic

Authored by jsji on Jun 28 2019, 10:15 AM.

Details

Reviewers
lebedev.ri
RKSimon
Commits
rG7d78e5cc8115: [UpdateChecks] Add support for armv7-apple-darwin
rL364668: [UpdateChecks] Add support for armv7-apple-darwin
Summary

armv7-apple-darwin was not supported well, the script can't generate checks.

https://reviews.llvm.org/D60601/new/#inline-568671

Also updated one of the testcases needed in https://reviews.llvm.org/D60601.

Diff Detail

Repository
rL LLVM

Event Timeline

jsji created this revision.Jun 28 2019, 10:15 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 28 2019, 10:15 AM
Herald added subscribers: kristof.beyls, javed.absar. · View Herald Transcript
jsji edited the summary of this revision. (Show Details)Jun 28 2019, 10:15 AM
lebedev.ri added inline comments.Jun 28 2019, 10:24 AM
llvm/test/CodeGen/ARM/ldst-f32-2-i32.ll
8 ↗(On Diff #207089)

Does filecheck not bark on this?
I think you want to skip empty lines before body

jsji marked an inline comment as done.Jun 28 2019, 10:27 AM
jsji added inline comments.
llvm/test/CodeGen/ARM/ldst-f32-2-i32.ll
8 ↗(On Diff #207089)

Good catch, will fix it.

jsji updated this revision to Diff 207096.Jun 28 2019, 10:40 AM

Update to remove unintended empty lines before body.

lebedev.ri accepted this revision.Jun 28 2019, 10:55 AM

LG. I trust that you have verified that FileCheck accepts these check lines.

This revision is now accepted and ready to land.Jun 28 2019, 10:55 AM
jsji added a comment.Jun 28 2019, 10:57 AM
In D63939#1562621, @lebedev.ri wrote:

LG. I trust that you have verified that FileCheck accepts these check lines.

Sure. Thanks!

Closed by commit rL364668: [UpdateChecks] Add support for armv7-apple-darwin (authored by jsji). · Explain WhyJun 28 2019, 11:07 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
test/
CodeGen/
ARM/
14 lines
utils/
UpdateTestChecks/
9 lines

Diff 207108

llvm/trunk/test/CodeGen/ARM/ldst-f32-2-i32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=armv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s ; RUN: llc < %s -mtriple=armv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s
; Check if the f32 load / store pair are optimized to i32 load / store. ; Check if the f32 load / store pair are optimized to i32 load / store.
; rdar://8944252 ; rdar://8944252
define void @t(i32 %width, float* nocapture %src, float* nocapture %dst, i32 %index) nounwind { define void @t(i32 %width, float* nocapture %src, float* nocapture %dst, i32 %index) nounwind {
; CHECK-LABEL: t: ; CHECK-LABEL: t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: bxeq lr
; CHECK-NEXT: LBB0_1: @ %bb
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr r9, [r1], r3
; CHECK-NEXT: subs r0, r0, #1
; CHECK-NEXT: str r9, [r2], #4
; CHECK-NEXT: bne LBB0_1
; CHECK-NEXT: @ %bb.2: @ %return
; CHECK-NEXT: bx lr
entry: entry:
%src6 = bitcast float* %src to i8* %src6 = bitcast float* %src to i8*
%0 = icmp eq i32 %width, 0 %0 = icmp eq i32 %width, 0
br i1 %0, label %return, label %bb br i1 %0, label %return, label %bb
bb: bb:
; CHECK: ldr [[REGISTER:(r[0-9]+)]], [{{r[0-9]+}}], {{r[0-9]+}}
; CHECK: str [[REGISTER]], [{{r[0-9]+}}], #4
%j.05 = phi i32 [ %2, %bb ], [ 0, %entry ] %j.05 = phi i32 [ %2, %bb ], [ 0, %entry ]
%tmp = mul i32 %j.05, %index %tmp = mul i32 %j.05, %index
%uglygep = getelementptr i8, i8* %src6, i32 %tmp %uglygep = getelementptr i8, i8* %src6, i32 %tmp
%src_addr.04 = bitcast i8* %uglygep to float* %src_addr.04 = bitcast i8* %uglygep to float*
%dst_addr.03 = getelementptr float, float* %dst, i32 %j.05 %dst_addr.03 = getelementptr float, float* %dst, i32 %j.05
%1 = load float, float* %src_addr.04, align 4 %1 = load float, float* %src_addr.04, align 4
store float %1, float* %dst_addr.03, align 4 store float %1, float* %dst_addr.03, align 4
%2 = add i32 %j.05, 1 %2 = add i32 %j.05, 1
%exitcond = icmp eq i32 %2, %width %exitcond = icmp eq i32 %2, %width
br i1 %exitcond, label %return, label %bb br i1 %exitcond, label %return, label %bb
return: return:
ret void ret void
} }

llvm/trunk/utils/UpdateTestChecks/asm.py

Show First 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
ASM_FUNCTION_AARCH64_DARWIN_RE = re.compile( ASM_FUNCTION_AARCH64_DARWIN_RE = re.compile(
r'^_(?P<func>[^:]+):[ \t]*;[ \t]@(?P=func)\n' r'^_(?P<func>[^:]+):[ \t]*;[ \t]@(?P=func)\n'
r'([ \t]*.cfi_startproc\n[\s]*)?' r'([ \t]*.cfi_startproc\n[\s]*)?'
r'(?P<body>.*?)' r'(?P<body>.*?)'
r'([ \t]*.cfi_endproc\n[\s]*)?' r'([ \t]*.cfi_endproc\n[\s]*)?'
r'^[ \t]*;[ \t]--[ \t]End[ \t]function', r'^[ \t]*;[ \t]--[ \t]End[ \t]function',
flags=(re.M | re.S)) flags=(re.M | re.S))
ASM_FUNCTION_ARM_DARWIN_RE = re.compile(
r'^[ \t]*\.globl[ \t]*_(?P<func>[^ \t])[ \t]*@[ \t]--[ \t]Begin[ \t]function[ \t](?P=func)'
r'(?P<directives>.*?)'
r'^_(?P=func):\n[ \t]*'
r'(?P<body>.*?)'
r'^[ \t]*@[ \t]--[ \t]End[ \t]function',
flags=(re.M | re.S ))
ASM_FUNCTION_ARM_MACHO_RE = re.compile( ASM_FUNCTION_ARM_MACHO_RE = re.compile(
r'^_(?P<func>[^:]+):[ \t]*\n' r'^_(?P<func>[^:]+):[ \t]*\n'
r'([ \t]*.cfi_startproc\n[ \t]*)?' r'([ \t]*.cfi_startproc\n[ \t]*)?'
r'(?P<body>.*?)\n' r'(?P<body>.*?)\n'
r'[ \t]*\.cfi_endproc\n', r'[ \t]*\.cfi_endproc\n',
flags=(re.M | re.S)) flags=(re.M | re.S))
ASM_FUNCTION_ARM_IOS_RE = re.compile( ASM_FUNCTION_ARM_IOS_RE = re.compile(
▲ Show 20 Lines • Show All 181 Lines • ▼ Show 20 Lines target_handlers = {
'aarch64-apple-darwin': (scrub_asm_arm_eabi, ASM_FUNCTION_AARCH64_DARWIN_RE), 'aarch64-apple-darwin': (scrub_asm_arm_eabi, ASM_FUNCTION_AARCH64_DARWIN_RE),
'hexagon': (scrub_asm_hexagon, ASM_FUNCTION_HEXAGON_RE), 'hexagon': (scrub_asm_hexagon, ASM_FUNCTION_HEXAGON_RE),
'r600': (scrub_asm_amdgpu, ASM_FUNCTION_AMDGPU_RE), 'r600': (scrub_asm_amdgpu, ASM_FUNCTION_AMDGPU_RE),
'amdgcn': (scrub_asm_amdgpu, ASM_FUNCTION_AMDGPU_RE), 'amdgcn': (scrub_asm_amdgpu, ASM_FUNCTION_AMDGPU_RE),
'arm': (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_RE), 'arm': (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_RE),
'arm64': (scrub_asm_arm_eabi, ASM_FUNCTION_AARCH64_RE), 'arm64': (scrub_asm_arm_eabi, ASM_FUNCTION_AARCH64_RE),
'arm64-apple-ios': (scrub_asm_arm_eabi, ASM_FUNCTION_AARCH64_DARWIN_RE), 'arm64-apple-ios': (scrub_asm_arm_eabi, ASM_FUNCTION_AARCH64_DARWIN_RE),
'armv7-apple-ios' : (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_IOS_RE), 'armv7-apple-ios' : (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_IOS_RE),
'armv7-apple-darwin': (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_DARWIN_RE),
'thumb': (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_RE), 'thumb': (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_RE),
'thumb-macho': (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_MACHO_RE), 'thumb-macho': (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_MACHO_RE),
'thumbv5-macho': (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_MACHO_RE), 'thumbv5-macho': (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_MACHO_RE),
'thumbv7-apple-ios' : (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_IOS_RE), 'thumbv7-apple-ios' : (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_IOS_RE),
'mips': (scrub_asm_mips, ASM_FUNCTION_MIPS_RE), 'mips': (scrub_asm_mips, ASM_FUNCTION_MIPS_RE),
'ppc32': (scrub_asm_powerpc, ASM_FUNCTION_PPC_RE), 'ppc32': (scrub_asm_powerpc, ASM_FUNCTION_PPC_RE),
'powerpc': (scrub_asm_powerpc, ASM_FUNCTION_PPC_RE), 'powerpc': (scrub_asm_powerpc, ASM_FUNCTION_PPC_RE),
'riscv32': (scrub_asm_riscv, ASM_FUNCTION_RISCV_RE), 'riscv32': (scrub_asm_riscv, ASM_FUNCTION_RISCV_RE),
Show All 27 Lines