Index: llvm/test/CodeGen/PowerPC/varargs.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/varargs.ll
+++ llvm/test/CodeGen/PowerPC/varargs.ll
@@ -1,41 +1,44 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck -check-prefix=P32 %s
 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck -check-prefix=P64 %s
 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck -check-prefix=P64 %s
 
 ; PR8327
 define i8* @test1(i8** %foo) nounwind {
+; P32-LABEL: test1:
+; P32:       # %bb.0:
+; P32-NEXT:    lbz r4, 0(r3)
+; P32-NEXT:    addi r5, r4, 1
+; P32-NEXT:    stb r5, 0(r3)
+; P32-NEXT:    cmpwi r4, 8
+; P32-NEXT:    lwz r5, 4(r3)
+; P32-NEXT:    slwi r4, r4, 2
+; P32-NEXT:    addi r6, r5, 4
+; P32-NEXT:    bc 12, lt, .LBB0_1
+; P32-NEXT:    b .LBB0_2
+; P32-NEXT:  .LBB0_1:
+; P32-NEXT:    addi r6, r5, 0
+; P32-NEXT:  .LBB0_2:
+; P32-NEXT:    stw r6, 4(r3)
+; P32-NEXT:    lwz r3, 8(r3)
+; P32-NEXT:    add r3, r3, r4
+; P32-NEXT:    bc 12, lt, .LBB0_4
+; P32-NEXT:  # %bb.3:
+; P32-NEXT:    ori r3, r5, 0
+; P32-NEXT:    b .LBB0_4
+; P32-NEXT:  .LBB0_4:
+; P32-NEXT:    lwz r3, 0(r3)
+; P32-NEXT:    blr
+;
+; P64-LABEL: test1:
+; P64:       # %bb.0:
+; P64-NEXT:    ld r4, 0(r3)
+; P64-NEXT:    addi r5, r4, 8
+; P64-NEXT:    std r5, 0(r3)
+; P64-NEXT:    ld r3, 0(r4)
+; P64-NEXT:    blr
   %A = va_arg i8** %foo, i8*
   ret i8* %A
 }
 
-; P32-LABEL: test1:
-; P32:  lbz [[REG1:r[0-9]+]], 0(r3)
-; P32:  addi [[REG2:r[0-9]+]], [[REG1]], 1
-;	P32:  stb [[REG2]], 0(r3)
-;	P32:  cmpwi	[[REG1]], 8
-;	P32:  lwz [[REG3:r[0-9]+]], 4(r3)
-;	P32:  slwi [[REG4:r[0-9]+]], [[REG1]], 2
-;	P32:  addi [[REG5:r[0-9]+]], [[REG3]], 4
-;	P32:  bc 12, lt, .LBB0_1
-;	P32:  b .LBB0_2
-; P32:  .LBB0_1:
-; P32:  addi [[REG5]], [[REG3]], 0
-;	P32: .LBB0_2:
-;	P32:  stw [[REG5]], 4(r3)
-;	P32:  lwz [[REG6:r[0-9]+]], 8(r3)
-;	P32:  add [[REG6]], [[REG6]], [[REG4]]
-; P32:  bc 12, lt, .LBB0_4
-;	P32: # %bb.3:
-;	P32:  ori [[REG6]], [[REG2]], 0
-;	P32:  b .LBB0_4
-;	P32: .LBB0_4:
-;	P32:  lwz r3, 0([[REG6]])
-;	P32:  blr
-
-; P64-LABEL: test1:
-; P64: ld [[REG1:r[0-9]+]], 0(r3)
-; P64: addi [[REG2:r[0-9]+]], [[REG1]], 8
-; P64: std [[REG2]], 0(r3)
-; P64: ld r3, 0([[REG1]])
-; P64: blr 
 
Index: llvm/utils/UpdateTestChecks/asm.py
===================================================================
--- llvm/utils/UpdateTestChecks/asm.py
+++ llvm/utils/UpdateTestChecks/asm.py
@@ -308,6 +308,7 @@
       'thumbv7-apple-ios' : (scrub_asm_arm_eabi, ASM_FUNCTION_ARM_IOS_RE),
       'mips': (scrub_asm_mips, ASM_FUNCTION_MIPS_RE),
       'ppc32': (scrub_asm_powerpc, ASM_FUNCTION_PPC_RE),
+      'powerpc': (scrub_asm_powerpc, ASM_FUNCTION_PPC_RE),
       'powerpc64': (scrub_asm_powerpc, ASM_FUNCTION_PPC_RE),
       'powerpc64le': (scrub_asm_powerpc, ASM_FUNCTION_PPC_RE),
       'riscv32': (scrub_asm_riscv, ASM_FUNCTION_RISCV_RE),