diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -96,7 +96,8 @@ Changes to the X86 Target ------------------------- - During this release ... +* Machine model for AMD K10 (10h, Barcelona) CPU was added. It is used to + support instruction scheduling and other instruction cost heuristics. Changes to the AMDGPU Target ----------------------------- diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -487,6 +487,7 @@ include "X86SchedBroadwell.td" include "X86ScheduleSLM.td" include "X86ScheduleZnver1.td" +include "X86ScheduleBarcelona.td" include "X86ScheduleBdVer2.td" include "X86ScheduleBtVer2.td" include "X86SchedSkylakeClient.td" @@ -1145,7 +1146,7 @@ } foreach P = ["amdfam10", "barcelona"] in { - def : Proc; + def : ProcessorModel; } // Bobcat diff --git a/llvm/lib/Target/X86/X86PfmCounters.td b/llvm/lib/Target/X86/X86PfmCounters.td --- a/llvm/lib/Target/X86/X86PfmCounters.td +++ b/llvm/lib/Target/X86/X86PfmCounters.td @@ -163,8 +163,18 @@ def : PfmCountersBinding<"k8-sse3", DefaultAMDPfmCounters>; def : PfmCountersBinding<"opteron-sse3", DefaultAMDPfmCounters>; def : PfmCountersBinding<"athlon64-sse3", DefaultAMDPfmCounters>; -def : PfmCountersBinding<"amdfam10", DefaultAMDPfmCounters>; -def : PfmCountersBinding<"barcelona", DefaultAMDPfmCounters>; + +def BarcelonaPfmCounters : ProcPfmCounters { + let CycleCounter = PfmCounter<"cpu_clk_unhalted">; + let UopsCounter = PfmCounter<"retired_uops">; + let IssueCounters = [ + PfmIssueCounter<"BnFADD", "dispatched_fpu:ops_add + dispatched_fpu:ops_add_pipe_load_ops">, + PfmIssueCounter<"BnFMUL", "dispatched_fpu:ops_multiply + dispatched_fpu:ops_multiply_pipe_load_ops">, + PfmIssueCounter<"BnFMISC", "dispatched_fpu:ops_store + dispatched_fpu:ops_store_pipe_load_ops">, + ]; +} +def : PfmCountersBinding<"amdfam10", BarcelonaPfmCounters>; +def : PfmCountersBinding<"barcelona", BarcelonaPfmCounters>; def BdVer2PfmCounters : ProcPfmCounters { let CycleCounter = PfmCounter<"cpu_clk_unhalted">; diff --git a/llvm/lib/Target/X86/X86ScheduleBarcelona.td b/llvm/lib/Target/X86/X86ScheduleBarcelona.td new file mode 100644 --- /dev/null +++ b/llvm/lib/Target/X86/X86ScheduleBarcelona.td @@ -0,0 +1,764 @@ +//=- X86ScheduleBarcelona.td - X86 Barcelona Scheduling ------*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines the machine model for AMD fam10h (Barcelona) to support +// instruction scheduling and other instruction cost heuristics. +// Based on: +// * Measurements from llvm-exegesis +// * AMD Software Optimization Guide for AMD Family 10h and 12h Processors +// https://support.amd.com/TechDocs/40546.pdf +// * The microarchitecture of Intel, AMD and VIA CPUs, By Agner Fog +// http://www.agner.org/optimize/microarchitecture.pdf +// * https://www.realworldtech.com/barcelona/ +// +//===----------------------------------------------------------------------===// + +def BarcelonaModel : SchedMachineModel { + let IssueWidth = 3; // Up to 3 IPC can be decoded, issued, retired. + let MicroOpBufferSize = 72; // 24 lines of three macro-ops. + let LoopMicroOpBufferSize = -1; // There does not seem to be a loop buffer. + let LoadLatency = 3; // The L1 data cache has a 3-cycle load-to-use latency. + let HighLatency = 10; // between 96.6'th and 96.7'th and percentiles of all + // the instruction latencies llvm-exegesis can measure. + let MispredictPenalty = 12; // Minimum branch misdirection penalty. + + let PostRAScheduler = 1; // Enable Post RegAlloc Scheduler pass. + + // FIXME: Incomplete. This flag is set to allow the scheduler to assign + // a default model to unrecognized opcodes. + let CompleteModel = 0; +} // SchedMachineModel + +let SchedModel = BarcelonaModel in { + + +//===----------------------------------------------------------------------===// +// RCU +//===----------------------------------------------------------------------===// + +// 24 lines of three macro-ops. +def BnRCU : RetireControlUnit<72, 3>; +// FIXME: it isn't that simple actually. +// It's not 72 entries, but more like 24 "entries", each entry tracking +// up to 3 lanes. + + +//===----------------------------------------------------------------------===// +// Functional Clusters +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Integer Cluster +// + +// Integer physical register file has 40 registers of 64-bit. +def BnIntPRF : RegisterFile<40, [GR64, CCR]>; + +// There are total of three integer pipes. +foreach i = 0-2 in { + def BnInt#i : ProcResource<1>; +} + +// The integer scheduler is based on a three-wide queuing system (also known as +// a reservation station) that feeds three integer execution positions or pipes. +// The reservation stations are eight entries deep, for a total queuing system +// of 24 integer macro-ops. +def BnInt : ProcResGroup<[BnInt0, BnInt1, BnInt2]> { + let BufferSize = 24; +} + +// *Each* integer pipe has an ALU unit, *and* an AGU unit. +foreach i = 0-2 in { + def BnALU#i : ProcResource<1>; + def BnAGU#i : ProcResource<1>; // FIXME: so which SchedWrites use AGU? +} + +// Integer pipe 0 contains multiplication unit. +// FIXME: when this unit is ocuppied, BnALU{0,1} units are stalled? +def BnIMUL : ProcResource<1>; + +// Integer pipe 2 contains an unit for ABM instructions (popcnt, lzcnt). +// FIXME: when this unit is ocuppied, BnALU{1,2} units are stalled? +def BnABM : ProcResource<1>; + +// Int pipe grouping. +def BnInt012 : ProcResGroup<[BnInt0, BnInt1, BnInt2]>; + +// ALU unit grouping. +def BnALU012 : ProcResGroup<[BnALU0, BnALU1, BnALU2]>; + +// AGU unit grouping. +// FIXME: so which SchedWrites use AGU? +def BnAGU012 : ProcResGroup<[BnAGU0, BnAGU1, BnAGU2]>; + +//===----------------------------------------------------------------------===// +// Floating-Point Cluster +// + +// FP physical register file has 120 registers of 128-bit. +def BnFpuPRF : RegisterFile<120, [VR64, VR128], [1, 1]>; + +// There are total of three floating-point pipes. +foreach i = 0-2 in { + def BnFPU#i : ProcResource<1>; +} + +// The floating-point scheduler has a dedicated 36-entry scheduler buffer, +// organized as 12 lines of three macro-ops each. +def BnFPU : ProcResGroup<[BnFPU0, BnFPU1, BnFPU2]> { + let BufferSize = 36; +} + +// FPU pipe grouping. +def BnFPU01 : ProcResGroup<[BnFPU0, BnFPU1]>; +def BnFPU12 : ProcResGroup<[BnFPU1, BnFPU2]>; +def BnFPU012 : ProcResGroup<[BnFPU0, BnFPU1, BnFPU2]>; + +// FP pipe 0 contains vector (both integer and fp) addition unit. +def BnFADD : ProcResource<1>; + +// FP pipe 1 contains vector (both integer and fp) multiplication unit. +def BnFMUL : ProcResource<1>; + +// FP pipe 2 contains vector conversion/load/store unit. +def BnFMISC : ProcResource<1>; + +// FPU unit grouping. +// Some instructions can go to either BnFADD or BnFMUL units. +def BnFAddOrMul : ProcResGroup<[BnFADD, BnFMUL]>; +// Some instructions can execute on any FPU unit. +def BnFAny : ProcResGroup<[BnFADD, BnFMUL, BnFMISC]>; + +//===----------------------------------------------------------------------===// +// Load-Store Cluster +// + +// The L1 data cache can support two 128-bit loads or two 64-bit store writes +// per cycle or a mix of those. +def BnLSU : ProcResource<2>; + +// The LSU consists of two queues—LS1 and LS2. + +// LS1 can issue two L1 cache operations (loads or store tag checks) per cycle. +let Super = BnLSU in +def BnLoad : ProcResource<2> { // BnLS1 + let BufferSize = 12; +} + +def BnLoadQueue : LoadQueue; + +// FIXME: it's kinda more complicated than that, LS2 handles loads that +// LS1 failed to handle via L1 cache. + +// Store writes are done exclusively from LS2. 128-bit stores are specially +// handled in that they take two LS2 entries, and the store writes are +// performed as two 64-bit writes. +let Super = BnLSU in +def BnStore : ProcResource<2> { // BnLS2 + let BufferSize = 32; +} + +def BnStoreQueue : StoreQueue; + + + +//===----------------------------------------------------------------------===// +// Basic helper classes. +//===----------------------------------------------------------------------===// + +multiclass BnWriteRes ExePorts, + int Lat, list Res, int UOps> { + def : WriteRes { + let Latency = Lat; + let ResourceCycles = Res; + let NumMicroOps = UOps; + } +} + +multiclass BnWriteResInt ExePorts, int Lat, + list Res, int UOps> { + defm : BnWriteRes; +} + +multiclass BnWriteResFPU ExePorts, int Lat, + list Res, int UOps> { + defm : BnWriteRes; +} + +multiclass __bnWriteResPairInt ExePorts, int Lat, + list Res, int UOps, int LoadLat, + int LoadUOps> { + defm : BnWriteResInt; + + defm : BnWriteResInt; +} + +multiclass __bnWriteResPairFPU ExePorts, int Lat, + list Res, int UOps, int LoadLat, + int LoadUOps> { + defm : BnWriteResFPU; + + defm : BnWriteResFPU; +} + +multiclass BnWriteResIntPair ExePorts, int Lat, + list Res, int UOps, int LoadUOps = 0> { + defm : __bnWriteResPairInt; +} + +multiclass BnWriteResFPUPair ExePorts, int Lat, + list Res, int UOps, int LoadUOps = 0> { + defm : __bnWriteResPairFPU; +} + + +//===----------------------------------------------------------------------===// +// Here be dragons. +//===----------------------------------------------------------------------===// + +// L1 data cache has a 3-cycle load-to-use latency, so ReadAfterLd registers +// needn't be available until 3 cycles after the memory operand. +def : ReadAdvance; + +// Vector loads are 2 cycles (yes, less than scalar loads), so ReadAfterVec*Ld +// registers needn't be available until 2 cycles after the memory operand. +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; // unsupported. + +def : ReadAdvance; // Non-applicable? + +// A folded store needs a cycle on the BnStore for the store data. +defm : BnWriteResInt; // FIXME: latency not from llvm-exegesis + +//////////////////////////////////////////////////////////////////////////////// +// Loads, stores, and moves, not folded with other operations. +//////////////////////////////////////////////////////////////////////////////// + +defm : BnWriteResInt; +defm : BnWriteResInt; // FIXME: latency not from llvm-exegesis, from AMD SOG/Agner. FIXME: split +defm : BnWriteResInt; // FIXME: latency not from llvm-exegesis, from AMD SOG/Agner. +defm : BnWriteResInt; + +// Load/store MXCSR. +defm : BnWriteResInt; // FIXME: latency/uops/rthr not from llvm-exegesis, from AMD SOG/Agner. +defm : BnWriteResInt; // FIXME: latency not from llvm-exegesis, from AMD SOG/Agner. + +// Treat misc copies as a move. +def : InstRW<[WriteMove], (instrs COPY)>; + +//////////////////////////////////////////////////////////////////////////////// +// Idioms that clear a register, like xorps %FPU0, %FPU0. +// These can often bypass execution ports completely. +//////////////////////////////////////////////////////////////////////////////// + +defm : BnWriteRes; // FIXME + +//////////////////////////////////////////////////////////////////////////////// +// Branches don't produce values, so they have no latency, but they still +// consume resources. Indirect branches can fold loads. +//////////////////////////////////////////////////////////////////////////////// + +defm : BnWriteResIntPair; + +//////////////////////////////////////////////////////////////////////////////// +// Special case scheduling classes. +//////////////////////////////////////////////////////////////////////////////// + +defm : BnWriteResInt; // FIXME: could split +defm : BnWriteResInt; +defm : BnWriteResInt; + +// Nops don't have dependencies, so there's no actual latency, but we set this +// to '1' to tell the scheduler that the nop uses an ALU slot for a cycle. +defm : BnWriteResInt; // FIXME + +//////////////////////////////////////////////////////////////////////////////// +// Arithmetic. +//////////////////////////////////////////////////////////////////////////////// + +defm : BnWriteResIntPair; +defm : BnWriteResIntPair; + +defm : BnWriteResInt; +defm : BnWriteResInt; + +defm : BnWriteResInt; // FIXME: XCHG8rr is an outlier FIXME: split XCHG/XADD +defm : BnWriteResIntPair; + +defm : BnWriteResInt; // FIXME: latency not from llvm-exegesis, from AMD SOG. // FIXME: split + +defm : BnWriteResIntPair; +defm : BnWriteResIntPair; +defm : BnWriteResIntPair; // FIXME: consumes 2 resources? +defm : BnWriteResIntPair; // FIXME: consumes 2 resources? +defm : BnWriteResIntPair; +defm : BnWriteResIntPair; // FIXME: more complicated than that? +defm : BnWriteResIntPair; +defm : BnWriteResIntPair; // FIXME: consumes 2 resources? +defm : BnWriteResIntPair; // FIXME: more complicated than that? +defm : BnWriteResIntPair; +defm : X86WriteResUnsupported; // BMI2 MULX + +// FIXME: latency not from llvm-exegesis, from AMD SOG. +defm : BnWriteResIntPair; +defm : BnWriteResIntPair; +defm : BnWriteResIntPair; +defm : BnWriteResIntPair; + +// FIXME: latency not from llvm-exegesis, from AMD SOG. +defm : BnWriteResIntPair; +defm : BnWriteResIntPair; +defm : BnWriteResIntPair; +defm : BnWriteResIntPair; + +defm : X86WriteResPairUnsupported; + +defm : BnWriteResIntPair; // Conditional move. + +// FIXME: latency/uops not from llvm-exegesis, from AMD SOG. +defm : BnWriteResFPU; // x87 conditional move. + +defm : BnWriteResInt; // FIXME: latency is probably wrong, not accounting for the secondary helper instruction. +defm : BnWriteResInt; // FIXME: latency not from llvm-exegesis, from AMD SOG/Agner. + +defm : BnWriteResInt; // FIXME: latency is probably wrong, not accounting for the secondary helper instruction. FIXME: split? + +defm : BnWriteResInt; // FIXME: latency is probably wrong, not accounting for the secondary helper instruction. +defm : BnWriteResInt; // FIXME: latency not from llvm-exegesis, from Agner. +defm : BnWriteResInt; // FIXME: latency not from llvm-exegesis, from Agner. +defm : BnWriteResInt; +defm : BnWriteResInt; // FIXME: latency not from llvm-exegesis, from Agner. FIXME: split +defm : BnWriteResInt; // FIXME: latency not from llvm-exegesis, from Agner. + +// This is for simple LEAs with one or two input operands and no scale. +// FIXME: with scale and/or 3-operand LEA: lat=2 +defm : BnWriteResInt; // FIXME: latency/uops not from llvm-exegesis, from Agner. + +// Bit counts. +defm : BnWriteResIntPair; +defm : BnWriteResIntPair; +defm : BnWriteResIntPair; +defm : BnWriteResIntPair; +defm : X86WriteResPairUnsupported; + +// BMI1 BEXTR, BMI2 BZHI +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Integer shifts and rotates. +//////////////////////////////////////////////////////////////////////////////// + +defm : BnWriteResIntPair; // FIXME: split +defm : BnWriteResIntPair; // FIXME: split +defm : BnWriteResIntPair; // FIXME: split +defm : BnWriteResIntPair; // FIXME: split + +// SHLD/SHRD. +defm : BnWriteResInt; +defm : BnWriteResInt; + +defm : BnWriteResInt; // FIXME: latency not from llvm-exegesis +defm : BnWriteResInt; // FIXME: latency not from llvm-exegesis + +//////////////////////////////////////////////////////////////////////////////// +// Floating point. This covers both scalar and vector operations. +//////////////////////////////////////////////////////////////////////////////// + +defm : BnWriteResFPU; // FIXME: latency not from llvm-exegesis, from AMD SOG/Agner. +defm : BnWriteResFPU; // FIXME: latency not from llvm-exegesis, from AMD SOG/Agner. +defm : BnWriteResFPU; // FIXME: latency not from llvm-exegesis, from AMD SOG/Agner. + +defm : BnWriteResFPU; // FIXME: latency not from llvm-exegesis, from AMD SOG/Agner. +defm : BnWriteResFPU; // FIXME: latency not from llvm-exegesis, from AMD SOG/Agner. +defm : X86WriteResUnsupported; + +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; + +defm : BnWriteResFPU; // FIXME: latency not from llvm-exegesis, from AMD SOG/Agner. +defm : BnWriteResFPU; // FIXME: latency not from llvm-exegesis, from AMD SOG/Agner. +defm : X86WriteResUnsupported; + +defm : BnWriteResFPU; // FIXME: latency not from llvm-exegesis, from AMD SOG/Agner. +defm : BnWriteResFPU; // FIXME: latency not from llvm-exegesis, from AMD SOG/Agner. +defm : X86WriteResUnsupported; + +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; + +defm : X86WriteResUnsupported; +defm : BnWriteResFPU; +defm : X86WriteResUnsupported; + +defm : BnWriteResFPU; // FIXME: latency not from llvm-exegesis, from AMD SOG. + +defm : BnWriteResFPUPair; // FIXME: split +defm : BnWriteResFPUPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : BnWriteResFPUPair; +defm : BnWriteResFPUPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : BnWriteResFPUPair; // split +defm : BnWriteResFPUPair; // split +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : BnWriteResFPUPair; // split +defm : BnWriteResFPUPair; // split +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : BnWriteResFPUPair; // FIXME: latency is probably wrong, not accounting for the secondary helper instruction. + +defm : BnWriteResFPUPair; +defm : BnWriteResFPUPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : BnWriteResFPUPair; +defm : BnWriteResFPUPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : X86WriteResPairUnsupported; + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : BnWriteResFPUPair; +defm : BnWriteResFPUPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : BnWriteResFPUPair; +defm : BnWriteResFPUPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : BnWriteResFPUPair; +defm : BnWriteResFPUPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : BnWriteResFPUPair; +defm : BnWriteResFPUPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : BnWriteResFPUPair; +defm : BnWriteResFPUPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : BnWriteResFPUPair; +defm : BnWriteResFPUPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : BnWriteResFPUPair; // FIXME: latency not from llvm-exegesis, from Agner. +defm : BnWriteResFPUPair; // FIXME: latency not from llvm-exegesis, from AMD SOG/Agner. + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : BnWriteResFPUPair; // FIXME: split +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : BnWriteResFPUPair; // FIXME: split +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Conversions. +//////////////////////////////////////////////////////////////////////////////// + +defm : BnWriteResFPUPair; // FIXME: latency is probably wrong, not accounting for the secondary helper instruction. + +defm : BnWriteResFPUPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : BnWriteResFPUPair; // FIXME: latency is probably wrong, not accounting for the secondary helper instruction. + +defm : BnWriteResFPUPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : BnWriteResFPUPair; // FIXME: Ld is 1 uop *less* + +defm : BnWriteResFPUPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : BnWriteResFPUPair; // FIXME: Ld is 1 uop *less* + +defm : BnWriteResFPUPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : BnWriteResFPUPair; + +defm : BnWriteResFPUPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : BnWriteResFPUPair; // FIXME: Ld is 1 uop *less* + +defm : BnWriteResFPUPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; + +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Vector integer operations. +//////////////////////////////////////////////////////////////////////////////// + +defm : BnWriteResFPU; // FIXME: latency not from llvm-exegesis, from AMD SOG/Agner. +defm : BnWriteResFPU; // FIXME: latency not from llvm-exegesis, from Agner. +defm : X86WriteResUnsupported; + +defm : BnWriteResFPU; // FIXME: latency/uops not from llvm-exegesis, from AMD SOG/Agner. +defm : X86WriteResUnsupported; + +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; + +defm : BnWriteResFPU; // FIXME: latency not from llvm-exegesis, from AMD SOG/Agner. +defm : BnWriteResFPU; // FIXME: latency not from llvm-exegesis, from Agner. +defm : X86WriteResUnsupported; + +defm : BnWriteResFPU; // FIXME: latency not from llvm-exegesis, from AMD SOG/Agner. // FIXME: split +defm : X86WriteResUnsupported; + +defm : X86WriteResUnsupported; +defm : X86WriteResUnsupported; + +defm : BnWriteResFPU; +defm : BnWriteResFPU; +defm : X86WriteResUnsupported; + +defm : BnWriteResFPU; +defm : BnWriteResFPU; // FIXME: latency is probably wrong, not accounting for the secondary helper instruction. + +defm : BnWriteResFPUPair; +defm : BnWriteResFPUPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : BnWriteResFPUPair; +defm : BnWriteResFPUPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : BnWriteResFPUPair; +defm : BnWriteResFPUPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : BnWriteResFPUPair; +defm : BnWriteResFPUPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : BnWriteResFPUPair; +defm : BnWriteResFPUPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : X86WriteResPairUnsupported; + +defm : BnWriteResFPUPair; +defm : BnWriteResFPUPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : BnWriteResFPUPair; +defm : BnWriteResFPUPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Vector insert/extract operations. +//////////////////////////////////////////////////////////////////////////////// + +defm : BnWriteResFPU; +defm : BnWriteResFPU; // FIXME: latency not from llvm-exegesis, from AMD SOG/Agner. + +defm : BnWriteResFPU; // FIXME: latency is probably wrong, not accounting for the secondary helper instruction. +defm : BnWriteResFPU; // FIXME: latency/uops not from llvm-exegesis + +//////////////////////////////////////////////////////////////////////////////// +// SSE42 String instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// MOVMSK Instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : BnWriteResFPU; // FIXME: latency is probably wrong, not accounting for the secondary helper instruction. + +defm : BnWriteResFPU; // FIXME: latency is probably wrong, not accounting for the secondary helper instruction. +defm : X86WriteResUnsupported; +// defm : X86WriteResUnsupported; + +defm : BnWriteResFPU; + +//////////////////////////////////////////////////////////////////////////////// +// AES Instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Horizontal add/sub instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : BnWriteResFPUPair; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// Carry-less multiplication instructions. +//////////////////////////////////////////////////////////////////////////////// + +defm : X86WriteResPairUnsupported; + +//////////////////////////////////////////////////////////////////////////////// +// SSE4A instructions. +//////////////////////////////////////////////////////////////////////////////// + +def BnWriteINSERTQ : SchedWriteRes<[BnFPU01, BnFAddOrMul]> { + let Latency = 3; + let ResourceCycles = [1, 5]; + let NumMicroOps = 3; +} +def : InstRW<[BnWriteINSERTQ], (instrs INSERTQ, INSERTQI)>; + +//////////////////////////////////////////////////////////////////////////////// +// AVX instructions. +//////////////////////////////////////////////////////////////////////////////// + +// FIXME: investigate zero-idioms, one-idioms, dependency-breaking instructions. + +} // SchedModel diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/clear-super-register-1.s b/llvm/test/tools/llvm-mca/X86/Barcelona/clear-super-register-1.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/clear-super-register-1.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/clear-super-register-1.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=100 -resource-pressure=false -timeline -timeline-max-iterations=2 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -iterations=100 -resource-pressure=false -timeline -timeline-max-iterations=2 < %s | FileCheck %s ## Sets register RAX. imulq $5, %rcx, %rax @@ -15,13 +15,13 @@ # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 400 -# CHECK-NEXT: Total Cycles: 803 -# CHECK-NEXT: Total uOps: 400 +# CHECK-NEXT: Total Cycles: 903 +# CHECK-NEXT: Total uOps: 900 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 0.50 -# CHECK-NEXT: IPC: 0.50 -# CHECK-NEXT: Block RThroughput: 3.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 1.00 +# CHECK-NEXT: IPC: 0.44 +# CHECK-NEXT: Block RThroughput: 4.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -32,23 +32,23 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 3 1.00 imulq $5, %rcx, %rax -# CHECK-NEXT: 1 3 1.00 lzcntl %ecx, %eax -# CHECK-NEXT: 1 1 0.33 andq %rcx, %rax -# CHECK-NEXT: 1 3 1.00 bsfq %rax, %rcx +# CHECK-NEXT: 1 4 4.00 imulq $5, %rcx, %rax +# CHECK-NEXT: 1 3 3.00 lzcntl %ecx, %eax +# CHECK-NEXT: 1 2 1.00 andq %rcx, %rax +# CHECK-NEXT: 6 4 3.00 bsfq %rax, %rcx # CHECK: Timeline view: -# CHECK-NEXT: 012345678 -# CHECK-NEXT: Index 0123456789 +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 0 -# CHECK: [0,0] DeeeER . . . imulq $5, %rcx, %rax -# CHECK-NEXT: [0,1] D=eeeER . . . lzcntl %ecx, %eax -# CHECK-NEXT: [0,2] D====eER . . . andq %rcx, %rax -# CHECK-NEXT: [0,3] D=====eeeER . . bsfq %rax, %rcx -# CHECK-NEXT: [1,0] .D=======eeeER . . imulq $5, %rcx, %rax -# CHECK-NEXT: [1,1] .D========eeeER. . lzcntl %ecx, %eax -# CHECK-NEXT: [1,2] .D===========eER . andq %rcx, %rax -# CHECK-NEXT: [1,3] .D============eeeER bsfq %rax, %rcx +# CHECK: [0,0] DeeeeER . . . imulq $5, %rcx, %rax +# CHECK-NEXT: [0,1] DeeeE-R . . . lzcntl %ecx, %eax +# CHECK-NEXT: [0,2] D===eeER . . . andq %rcx, %rax +# CHECK-NEXT: [0,3] .D====eeeeER . . bsfq %rax, %rcx +# CHECK-NEXT: [1,0] . D======eeeeER . imulq $5, %rcx, %rax +# CHECK-NEXT: [1,1] . D======eeeE-R . lzcntl %ecx, %eax +# CHECK-NEXT: [1,2] . D=========eeER . andq %rcx, %rax +# CHECK-NEXT: [1,3] . D==========eeeeER bsfq %rax, %rcx # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -57,7 +57,7 @@ # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] -# CHECK-NEXT: 0. 2 4.5 0.5 0.0 imulq $5, %rcx, %rax -# CHECK-NEXT: 1. 2 5.5 1.5 0.0 lzcntl %ecx, %eax -# CHECK-NEXT: 2. 2 8.5 0.0 0.0 andq %rcx, %rax -# CHECK-NEXT: 3. 2 9.5 0.0 0.0 bsfq %rax, %rcx +# CHECK-NEXT: 0. 2 4.0 0.5 0.0 imulq $5, %rcx, %rax +# CHECK-NEXT: 1. 2 4.0 0.5 1.0 lzcntl %ecx, %eax +# CHECK-NEXT: 2. 2 7.0 0.0 0.0 andq %rcx, %rax +# CHECK-NEXT: 3. 2 8.0 0.0 0.0 bsfq %rax, %rcx diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/clear-super-register-2.s b/llvm/test/tools/llvm-mca/X86/Barcelona/clear-super-register-2.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/clear-super-register-2.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/clear-super-register-2.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=100 -resource-pressure=false -timeline -timeline-max-iterations=3 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -iterations=100 -resource-pressure=false -timeline -timeline-max-iterations=3 < %s | FileCheck %s # movss/movsd explicitly zeroes out the high bits of xmm, # so addps can start immediately, without waiting for sqrtss to finish. @@ -21,13 +21,13 @@ # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 300 -# CHECK-NEXT: Total Cycles: 1403 +# CHECK-NEXT: Total Cycles: 1607 # CHECK-NEXT: Total uOps: 300 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 0.21 -# CHECK-NEXT: IPC: 0.21 -# CHECK-NEXT: Block RThroughput: 14.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.19 +# CHECK-NEXT: IPC: 0.19 +# CHECK-NEXT: Block RThroughput: 16.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -38,23 +38,23 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 14 14.00 sqrtss %xmm0, %xmm0 -# CHECK-NEXT: 1 6 0.50 * movss (%eax), %xmm0 -# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm0 +# CHECK-NEXT: 1 19 16.00 sqrtss %xmm0, %xmm0 +# CHECK-NEXT: 1 2 0.50 * movss (%eax), %xmm0 +# CHECK-NEXT: 1 4 2.00 addps %xmm0, %xmm0 # CHECK: Timeline view: -# CHECK-NEXT: 0123456789 0123456789 -# CHECK-NEXT: Index 0123456789 0123456789 01234 +# CHECK-NEXT: 0123456789 0123456789 01234 +# CHECK-NEXT: Index 0123456789 0123456789 0123456789 -# CHECK: [0,0] DeeeeeeeeeeeeeeER . . . . . . sqrtss %xmm0, %xmm0 -# CHECK-NEXT: [0,1] DeeeeeeE--------R . . . . . . movss (%eax), %xmm0 -# CHECK-NEXT: [0,2] D======eeeE-----R . . . . . . addps %xmm0, %xmm0 -# CHECK-NEXT: [1,0] D==============eeeeeeeeeeeeeeER . . . sqrtss %xmm0, %xmm0 -# CHECK-NEXT: [1,1] .DeeeeeeE---------------------R . . . movss (%eax), %xmm0 -# CHECK-NEXT: [1,2] .D======eeeE------------------R . . . addps %xmm0, %xmm0 -# CHECK-NEXT: [2,0] .D===========================eeeeeeeeeeeeeeER sqrtss %xmm0, %xmm0 -# CHECK-NEXT: [2,1] .DeeeeeeE-----------------------------------R movss (%eax), %xmm0 -# CHECK-NEXT: [2,2] . D======eeeE-------------------------------R addps %xmm0, %xmm0 +# CHECK: [0,0] D=eeeeeeeeeeeeeeeeeeeER . . . . . . . sqrtss %xmm0, %xmm0 +# CHECK-NEXT: [0,1] DeeE------------------R . . . . . . . movss (%eax), %xmm0 +# CHECK-NEXT: [0,2] D==eeeeE--------------R . . . . . . . addps %xmm0, %xmm0 +# CHECK-NEXT: [1,0] .D================eeeeeeeeeeeeeeeeeeeER . . . . sqrtss %xmm0, %xmm0 +# CHECK-NEXT: [1,1] .DeeE---------------------------------R . . . . movss (%eax), %xmm0 +# CHECK-NEXT: [1,2] .D=====eeeeE--------------------------R . . . . addps %xmm0, %xmm0 +# CHECK-NEXT: [2,0] . D===============================eeeeeeeeeeeeeeeeeeeER sqrtss %xmm0, %xmm0 +# CHECK-NEXT: [2,1] . DeeE------------------------------------------------R movss (%eax), %xmm0 +# CHECK-NEXT: [2,2] . D========eeeeE--------------------------------------R addps %xmm0, %xmm0 # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -63,21 +63,21 @@ # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] -# CHECK-NEXT: 0. 3 14.7 8.0 0.0 sqrtss %xmm0, %xmm0 -# CHECK-NEXT: 1. 3 1.0 1.0 21.3 movss (%eax), %xmm0 -# CHECK-NEXT: 2. 3 7.0 0.3 18.0 addps %xmm0, %xmm0 +# CHECK-NEXT: 0. 3 17.0 12.0 0.0 sqrtss %xmm0, %xmm0 +# CHECK-NEXT: 1. 3 1.0 1.0 33.0 movss (%eax), %xmm0 +# CHECK-NEXT: 2. 3 6.0 3.0 26.0 addps %xmm0, %xmm0 # CHECK: [1] Code Region # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 300 -# CHECK-NEXT: Total Cycles: 2103 +# CHECK-NEXT: Total Cycles: 2407 # CHECK-NEXT: Total uOps: 300 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 0.14 -# CHECK-NEXT: IPC: 0.14 -# CHECK-NEXT: Block RThroughput: 21.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.12 +# CHECK-NEXT: IPC: 0.12 +# CHECK-NEXT: Block RThroughput: 24.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -88,23 +88,23 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 21 21.00 sqrtsd %xmm0, %xmm0 -# CHECK-NEXT: 1 6 0.50 * movsd (%eax), %xmm0 -# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm0 +# CHECK-NEXT: 1 27 24.00 sqrtsd %xmm0, %xmm0 +# CHECK-NEXT: 1 2 0.50 * movsd (%eax), %xmm0 +# CHECK-NEXT: 1 4 2.00 addps %xmm0, %xmm0 # CHECK: Timeline view: -# CHECK-NEXT: 0123456789 0123456789 0123456789 -# CHECK-NEXT: Index 0123456789 0123456789 0123456789 012345 +# CHECK-NEXT: 0123456789 0123456789 0123456789 012345678 +# CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456789 -# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeeeER . . . . . . . . . sqrtsd %xmm0, %xmm0 -# CHECK-NEXT: [0,1] DeeeeeeE---------------R . . . . . . . . . movsd (%eax), %xmm0 -# CHECK-NEXT: [0,2] D======eeeE------------R . . . . . . . . . addps %xmm0, %xmm0 -# CHECK-NEXT: [1,0] D=====================eeeeeeeeeeeeeeeeeeeeeER. . . . . sqrtsd %xmm0, %xmm0 -# CHECK-NEXT: [1,1] .DeeeeeeE-----------------------------------R. . . . . movsd (%eax), %xmm0 -# CHECK-NEXT: [1,2] .D======eeeE--------------------------------R. . . . . addps %xmm0, %xmm0 -# CHECK-NEXT: [2,0] .D=========================================eeeeeeeeeeeeeeeeeeeeeER sqrtsd %xmm0, %xmm0 -# CHECK-NEXT: [2,1] .DeeeeeeE--------------------------------------------------------R movsd (%eax), %xmm0 -# CHECK-NEXT: [2,2] . D======eeeE----------------------------------------------------R addps %xmm0, %xmm0 +# CHECK: [0,0] D=eeeeeeeeeeeeeeeeeeeeeeeeeeeER . . . . . . . . . . sqrtsd %xmm0, %xmm0 +# CHECK-NEXT: [0,1] DeeE--------------------------R . . . . . . . . . . movsd (%eax), %xmm0 +# CHECK-NEXT: [0,2] D==eeeeE----------------------R . . . . . . . . . . addps %xmm0, %xmm0 +# CHECK-NEXT: [1,0] .D========================eeeeeeeeeeeeeeeeeeeeeeeeeeeER. . . . . . sqrtsd %xmm0, %xmm0 +# CHECK-NEXT: [1,1] .DeeE-------------------------------------------------R. . . . . . movsd (%eax), %xmm0 +# CHECK-NEXT: [1,2] .D=====eeeeE------------------------------------------R. . . . . . addps %xmm0, %xmm0 +# CHECK-NEXT: [2,0] . D===============================================eeeeeeeeeeeeeeeeeeeeeeeeeeeER sqrtsd %xmm0, %xmm0 +# CHECK-NEXT: [2,1] . DeeE------------------------------------------------------------------------R movsd (%eax), %xmm0 +# CHECK-NEXT: [2,2] . D========eeeeE--------------------------------------------------------------R addps %xmm0, %xmm0 # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -113,6 +113,6 @@ # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] -# CHECK-NEXT: 0. 3 21.7 15.0 0.0 sqrtsd %xmm0, %xmm0 -# CHECK-NEXT: 1. 3 1.0 1.0 35.3 movsd (%eax), %xmm0 -# CHECK-NEXT: 2. 3 7.0 0.3 32.0 addps %xmm0, %xmm0 +# CHECK-NEXT: 0. 3 25.0 20.0 0.0 sqrtsd %xmm0, %xmm0 +# CHECK-NEXT: 1. 3 1.0 1.0 49.0 movsd (%eax), %xmm0 +# CHECK-NEXT: 2. 3 6.0 3.0 42.0 addps %xmm0, %xmm0 diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-cmp.s b/llvm/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-cmp.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-cmp.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-cmp.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s # The CMP instruction doesn't depend on the value of EAX. It can set the flags # without having to read the inputs. @@ -9,13 +9,13 @@ # CHECK: Iterations: 1500 # CHECK-NEXT: Instructions: 3000 -# CHECK-NEXT: Total Cycles: 4503 -# CHECK-NEXT: Total uOps: 4500 +# CHECK-NEXT: Total Cycles: 6003 +# CHECK-NEXT: Total uOps: 3000 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.00 -# CHECK-NEXT: IPC: 0.67 -# CHECK-NEXT: Block RThroughput: 0.8 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.50 +# CHECK-NEXT: IPC: 0.50 +# CHECK-NEXT: Block RThroughput: 3.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -26,38 +26,53 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 1 0.33 cmpl %eax, %eax -# CHECK-NEXT: 2 2 0.67 cmovael %ebx, %eax +# CHECK-NEXT: 1 2 1.00 cmpl %eax, %eax +# CHECK-NEXT: 1 2 2.00 cmovael %ebx, %eax # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - 3.00 3.00 3.00 - - - - - - - 0.67 0.67 0.67 - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - - 1.00 - - cmpl %eax, %eax -# CHECK-NEXT: - - 1.00 1.00 - - - - cmovael %ebx, %eax +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmpl %eax, %eax +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovael %ebx, %eax # CHECK: Timeline view: -# CHECK-NEXT: 01 +# CHECK-NEXT: 01234 # CHECK-NEXT: Index 0123456789 -# CHECK: [0,0] DeER . .. cmpl %eax, %eax -# CHECK-NEXT: [0,1] D=eeER .. cmovael %ebx, %eax -# CHECK-NEXT: [1,0] D===eER .. cmpl %eax, %eax -# CHECK-NEXT: [1,1] .D===eeER .. cmovael %ebx, %eax -# CHECK-NEXT: [2,0] .D=====eER.. cmpl %eax, %eax -# CHECK-NEXT: [2,1] . D=====eeER cmovael %ebx, %eax +# CHECK: [0,0] DeeER. . . cmpl %eax, %eax +# CHECK-NEXT: [0,1] D==eeER . . cmovael %ebx, %eax +# CHECK-NEXT: [1,0] D====eeER . . cmpl %eax, %eax +# CHECK-NEXT: [1,1] .D=====eeER . cmovael %ebx, %eax +# CHECK-NEXT: [2,0] .D=======eeER . cmpl %eax, %eax +# CHECK-NEXT: [2,1] .D=========eeER cmovael %ebx, %eax # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -66,5 +81,5 @@ # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] -# CHECK-NEXT: 0. 3 3.7 0.3 0.0 cmpl %eax, %eax -# CHECK-NEXT: 1. 3 4.0 0.0 0.0 cmovael %ebx, %eax +# CHECK-NEXT: 0. 3 4.7 0.3 0.0 cmpl %eax, %eax +# CHECK-NEXT: 1. 3 6.3 0.0 0.0 cmovael %ebx, %eax diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-pcmpeq.s b/llvm/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-pcmpeq.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-pcmpeq.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-pcmpeq.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s # All of the vector packed compares from this test are dependency breaking # instructions. That means, there is no RAW dependency between any of the @@ -16,13 +16,13 @@ # CHECK: Iterations: 1500 # CHECK-NEXT: Instructions: 10500 -# CHECK-NEXT: Total Cycles: 13503 +# CHECK-NEXT: Total Cycles: 23969 # CHECK-NEXT: Total uOps: 10500 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 0.78 -# CHECK-NEXT: IPC: 0.78 -# CHECK-NEXT: Block RThroughput: 3.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.44 +# CHECK-NEXT: IPC: 0.44 +# CHECK-NEXT: Block RThroughput: 14.5 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -33,63 +33,78 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 3 1.00 pcmpeqb %mm0, %mm0 -# CHECK-NEXT: 1 3 1.00 pcmpeqd %mm0, %mm0 -# CHECK-NEXT: 1 3 1.00 pcmpeqw %mm0, %mm0 -# CHECK-NEXT: 1 1 0.50 pcmpeqb %xmm0, %xmm0 -# CHECK-NEXT: 1 1 0.50 pcmpeqd %xmm0, %xmm0 -# CHECK-NEXT: 1 1 0.50 pcmpeqq %xmm0, %xmm0 -# CHECK-NEXT: 1 1 0.50 pcmpeqw %xmm0, %xmm0 +# CHECK-NEXT: 1 2 1.50 pcmpeqb %mm0, %mm0 +# CHECK-NEXT: 1 2 1.50 pcmpeqd %mm0, %mm0 +# CHECK-NEXT: 1 2 1.50 pcmpeqw %mm0, %mm0 +# CHECK-NEXT: 1 3 2.50 pcmpeqb %xmm0, %xmm0 +# CHECK-NEXT: 1 3 2.50 pcmpeqd %xmm0, %xmm0 +# CHECK-NEXT: 1 3 2.50 pcmpeqq %xmm0, %xmm0 +# CHECK-NEXT: 1 3 2.50 pcmpeqw %xmm0, %xmm0 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - 4.01 - 2.99 - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - - - - 13.03 - 15.97 3.50 3.50 - - - - - - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - 1.00 - - - - pcmpeqb %mm0, %mm0 -# CHECK-NEXT: - - - 1.00 - - - - pcmpeqd %mm0, %mm0 -# CHECK-NEXT: - - - 1.00 - - - - pcmpeqw %mm0, %mm0 -# CHECK-NEXT: - - - 0.01 - 0.99 - - pcmpeqb %xmm0, %xmm0 -# CHECK-NEXT: - - - 0.01 - 0.99 - - pcmpeqd %xmm0, %xmm0 -# CHECK-NEXT: - - - 0.01 - 0.99 - - pcmpeqq %xmm0, %xmm0 -# CHECK-NEXT: - - - 0.99 - 0.01 - - pcmpeqw %xmm0, %xmm0 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - 0.03 - 2.97 0.51 0.49 - - - - - - - - - - - pcmpeqb %mm0, %mm0 +# CHECK-NEXT: - - - - - - - 0.03 - 2.97 0.51 0.49 - - - - - - - - - - - pcmpeqd %mm0, %mm0 +# CHECK-NEXT: - - - - - - - 2.96 - 0.04 0.51 0.49 - - - - - - - - - - - pcmpeqw %mm0, %mm0 +# CHECK-NEXT: - - - - - - - 5.00 - - 0.49 0.51 - - - - - - - - - - - pcmpeqb %xmm0, %xmm0 +# CHECK-NEXT: - - - - - - - 4.88 - 0.12 0.49 0.51 - - - - - - - - - - - pcmpeqd %xmm0, %xmm0 +# CHECK-NEXT: - - - - - - - 0.12 - 4.88 0.49 0.51 - - - - - - - - - - - pcmpeqq %xmm0, %xmm0 +# CHECK-NEXT: - - - - - - - - - 5.00 0.50 0.50 - - - - - - - - - - - pcmpeqw %xmm0, %xmm0 # CHECK: Timeline view: -# CHECK-NEXT: 0123456789 -# CHECK-NEXT: Index 0123456789 0123456789 +# CHECK-NEXT: 0123456789 0123456789 012 +# CHECK-NEXT: Index 0123456789 0123456789 0123456789 -# CHECK: [0,0] DeeeER . . . . . pcmpeqb %mm0, %mm0 -# CHECK-NEXT: [0,1] D===eeeER . . . . . pcmpeqd %mm0, %mm0 -# CHECK-NEXT: [0,2] D======eeeER . . . . pcmpeqw %mm0, %mm0 -# CHECK-NEXT: [0,3] DeE--------R . . . . pcmpeqb %xmm0, %xmm0 -# CHECK-NEXT: [0,4] .DeE-------R . . . . pcmpeqd %xmm0, %xmm0 -# CHECK-NEXT: [0,5] .D=eE------R . . . . pcmpeqq %xmm0, %xmm0 -# CHECK-NEXT: [0,6] .D==eE-----R . . . . pcmpeqw %xmm0, %xmm0 -# CHECK-NEXT: [1,0] .D========eeeER. . . . pcmpeqb %mm0, %mm0 -# CHECK-NEXT: [1,1] . D==========eeeER . . . pcmpeqd %mm0, %mm0 -# CHECK-NEXT: [1,2] . D=============eeeER . . pcmpeqw %mm0, %mm0 -# CHECK-NEXT: [1,3] . D==eE-------------R . . pcmpeqb %xmm0, %xmm0 -# CHECK-NEXT: [1,4] . D===eE------------R . . pcmpeqd %xmm0, %xmm0 -# CHECK-NEXT: [1,5] . D===eE-----------R . . pcmpeqq %xmm0, %xmm0 -# CHECK-NEXT: [1,6] . D====eE----------R . . pcmpeqw %xmm0, %xmm0 -# CHECK-NEXT: [2,0] . D===============eeeER . . pcmpeqb %mm0, %mm0 -# CHECK-NEXT: [2,1] . D==================eeeER . pcmpeqd %mm0, %mm0 -# CHECK-NEXT: [2,2] . D====================eeeER pcmpeqw %mm0, %mm0 -# CHECK-NEXT: [2,3] . D====eE------------------R pcmpeqb %xmm0, %xmm0 -# CHECK-NEXT: [2,4] . D=====eE-----------------R pcmpeqd %xmm0, %xmm0 -# CHECK-NEXT: [2,5] . D======eE----------------R pcmpeqq %xmm0, %xmm0 -# CHECK-NEXT: [2,6] . D======eE---------------R pcmpeqw %xmm0, %xmm0 +# CHECK: [0,0] DeeER. . . . . . . . . . . pcmpeqb %mm0, %mm0 +# CHECK-NEXT: [0,1] D===eeER . . . . . . . . . . pcmpeqd %mm0, %mm0 +# CHECK-NEXT: [0,2] D======eeER . . . . . . . . . pcmpeqw %mm0, %mm0 +# CHECK-NEXT: [0,3] .DeeeE----R . . . . . . . . . pcmpeqb %xmm0, %xmm0 +# CHECK-NEXT: [0,4] .D=====eeeER . . . . . . . . . pcmpeqd %xmm0, %xmm0 +# CHECK-NEXT: [0,5] .D========eeeER. . . . . . . . . pcmpeqq %xmm0, %xmm0 +# CHECK-NEXT: [0,6] . D============eeeER. . . . . . . . pcmpeqw %xmm0, %xmm0 +# CHECK-NEXT: [1,0] . D=========eeE----R. . . . . . . . pcmpeqb %mm0, %mm0 +# CHECK-NEXT: [1,1] . D============eeE-R. . . . . . . . pcmpeqd %mm0, %mm0 +# CHECK-NEXT: [1,2] . D==============eeER . . . . . . . pcmpeqw %mm0, %mm0 +# CHECK-NEXT: [1,3] . D================eeeER. . . . . . . pcmpeqb %xmm0, %xmm0 +# CHECK-NEXT: [1,4] . D====================eeeER . . . . . . pcmpeqd %xmm0, %xmm0 +# CHECK-NEXT: [1,5] . D=======================eeeER . . . . . pcmpeqq %xmm0, %xmm0 +# CHECK-NEXT: [1,6] . D===========================eeeER . . . . pcmpeqw %xmm0, %xmm0 +# CHECK-NEXT: [2,0] . D================eeE------------R . . . . pcmpeqb %mm0, %mm0 +# CHECK-NEXT: [2,1] . D===================eeE--------R . . . . pcmpeqd %mm0, %mm0 +# CHECK-NEXT: [2,2] . D=======================eeE-----R . . . . pcmpeqw %mm0, %mm0 +# CHECK-NEXT: [2,3] . D==============================eeeER . . . pcmpeqb %xmm0, %xmm0 +# CHECK-NEXT: [2,4] . .D=================================eeeER. . . pcmpeqd %xmm0, %xmm0 +# CHECK-NEXT: [2,5] . .D=====================================eeeER . . pcmpeqq %xmm0, %xmm0 +# CHECK-NEXT: [2,6] . .D=========================================eeeER pcmpeqw %xmm0, %xmm0 # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -98,10 +113,10 @@ # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] -# CHECK-NEXT: 0. 3 8.7 0.3 0.0 pcmpeqb %mm0, %mm0 -# CHECK-NEXT: 1. 3 11.3 0.0 0.0 pcmpeqd %mm0, %mm0 -# CHECK-NEXT: 2. 3 14.0 0.0 0.0 pcmpeqw %mm0, %mm0 -# CHECK-NEXT: 3. 3 3.0 0.3 13.0 pcmpeqb %xmm0, %xmm0 -# CHECK-NEXT: 4. 3 3.7 0.0 12.0 pcmpeqd %xmm0, %xmm0 -# CHECK-NEXT: 5. 3 4.3 0.0 11.0 pcmpeqq %xmm0, %xmm0 -# CHECK-NEXT: 6. 3 5.0 0.0 10.0 pcmpeqw %xmm0, %xmm0 +# CHECK-NEXT: 0. 3 9.3 1.7 5.3 pcmpeqb %mm0, %mm0 +# CHECK-NEXT: 1. 3 12.3 1.3 3.0 pcmpeqd %mm0, %mm0 +# CHECK-NEXT: 2. 3 15.3 1.3 1.7 pcmpeqw %mm0, %mm0 +# CHECK-NEXT: 3. 3 16.3 1.3 1.3 pcmpeqb %xmm0, %xmm0 +# CHECK-NEXT: 4. 3 20.3 1.3 0.0 pcmpeqd %xmm0, %xmm0 +# CHECK-NEXT: 5. 3 23.7 0.7 0.0 pcmpeqq %xmm0, %xmm0 +# CHECK-NEXT: 6. 3 27.7 1.3 0.0 pcmpeqw %xmm0, %xmm0 diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-pcmpgt.s b/llvm/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-pcmpgt.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-pcmpgt.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-pcmpgt.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s # All of the vector packed compares from this test are zero idioms. These zero # idioms are all detected and removed by the register renamer. That means, no @@ -17,13 +17,13 @@ # CHECK: Iterations: 1500 # CHECK-NEXT: Instructions: 10500 -# CHECK-NEXT: Total Cycles: 13503 +# CHECK-NEXT: Total Cycles: 23969 # CHECK-NEXT: Total uOps: 10500 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 0.78 -# CHECK-NEXT: IPC: 0.78 -# CHECK-NEXT: Block RThroughput: 3.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.44 +# CHECK-NEXT: IPC: 0.44 +# CHECK-NEXT: Block RThroughput: 14.5 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -34,63 +34,78 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 3 1.00 pcmpgtb %mm0, %mm0 -# CHECK-NEXT: 1 3 1.00 pcmpgtd %mm0, %mm0 -# CHECK-NEXT: 1 3 1.00 pcmpgtw %mm0, %mm0 -# CHECK-NEXT: 1 0 0.25 pcmpgtb %xmm0, %xmm0 -# CHECK-NEXT: 1 0 0.25 pcmpgtd %xmm0, %xmm0 -# CHECK-NEXT: 1 0 0.25 pcmpgtq %xmm0, %xmm0 -# CHECK-NEXT: 1 0 0.25 pcmpgtw %xmm0, %xmm0 +# CHECK-NEXT: 1 2 1.50 pcmpgtb %mm0, %mm0 +# CHECK-NEXT: 1 2 1.50 pcmpgtd %mm0, %mm0 +# CHECK-NEXT: 1 2 1.50 pcmpgtw %mm0, %mm0 +# CHECK-NEXT: 1 3 2.50 pcmpgtb %xmm0, %xmm0 +# CHECK-NEXT: 1 3 2.50 pcmpgtd %xmm0, %xmm0 +# CHECK-NEXT: 1 3 2.50 pcmpgtq %xmm0, %xmm0 +# CHECK-NEXT: 1 3 2.50 pcmpgtw %xmm0, %xmm0 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - 3.00 - - - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - - - - 13.03 - 15.97 3.50 3.50 - - - - - - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - 1.00 - - - - pcmpgtb %mm0, %mm0 -# CHECK-NEXT: - - - 1.00 - - - - pcmpgtd %mm0, %mm0 -# CHECK-NEXT: - - - 1.00 - - - - pcmpgtw %mm0, %mm0 -# CHECK-NEXT: - - - - - - - - pcmpgtb %xmm0, %xmm0 -# CHECK-NEXT: - - - - - - - - pcmpgtd %xmm0, %xmm0 -# CHECK-NEXT: - - - - - - - - pcmpgtq %xmm0, %xmm0 -# CHECK-NEXT: - - - - - - - - pcmpgtw %xmm0, %xmm0 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - 0.03 - 2.97 0.51 0.49 - - - - - - - - - - - pcmpgtb %mm0, %mm0 +# CHECK-NEXT: - - - - - - - 0.03 - 2.97 0.51 0.49 - - - - - - - - - - - pcmpgtd %mm0, %mm0 +# CHECK-NEXT: - - - - - - - 2.96 - 0.04 0.51 0.49 - - - - - - - - - - - pcmpgtw %mm0, %mm0 +# CHECK-NEXT: - - - - - - - 5.00 - - 0.49 0.51 - - - - - - - - - - - pcmpgtb %xmm0, %xmm0 +# CHECK-NEXT: - - - - - - - 4.88 - 0.12 0.49 0.51 - - - - - - - - - - - pcmpgtd %xmm0, %xmm0 +# CHECK-NEXT: - - - - - - - 0.12 - 4.88 0.49 0.51 - - - - - - - - - - - pcmpgtq %xmm0, %xmm0 +# CHECK-NEXT: - - - - - - - - - 5.00 0.50 0.50 - - - - - - - - - - - pcmpgtw %xmm0, %xmm0 # CHECK: Timeline view: -# CHECK-NEXT: 0123456789 -# CHECK-NEXT: Index 0123456789 0123456789 +# CHECK-NEXT: 0123456789 0123456789 012 +# CHECK-NEXT: Index 0123456789 0123456789 0123456789 -# CHECK: [0,0] DeeeER . . . . . pcmpgtb %mm0, %mm0 -# CHECK-NEXT: [0,1] D===eeeER . . . . . pcmpgtd %mm0, %mm0 -# CHECK-NEXT: [0,2] D======eeeER . . . . pcmpgtw %mm0, %mm0 -# CHECK-NEXT: [0,3] D----------R . . . . pcmpgtb %xmm0, %xmm0 -# CHECK-NEXT: [0,4] .D---------R . . . . pcmpgtd %xmm0, %xmm0 -# CHECK-NEXT: [0,5] .D---------R . . . . pcmpgtq %xmm0, %xmm0 -# CHECK-NEXT: [0,6] .D---------R . . . . pcmpgtw %xmm0, %xmm0 -# CHECK-NEXT: [1,0] .D========eeeER. . . . pcmpgtb %mm0, %mm0 -# CHECK-NEXT: [1,1] . D==========eeeER . . . pcmpgtd %mm0, %mm0 -# CHECK-NEXT: [1,2] . D=============eeeER . . pcmpgtw %mm0, %mm0 -# CHECK-NEXT: [1,3] . D-----------------R . . pcmpgtb %xmm0, %xmm0 -# CHECK-NEXT: [1,4] . D-----------------R . . pcmpgtd %xmm0, %xmm0 -# CHECK-NEXT: [1,5] . D----------------R . . pcmpgtq %xmm0, %xmm0 -# CHECK-NEXT: [1,6] . D----------------R . . pcmpgtw %xmm0, %xmm0 -# CHECK-NEXT: [2,0] . D===============eeeER . . pcmpgtb %mm0, %mm0 -# CHECK-NEXT: [2,1] . D==================eeeER . pcmpgtd %mm0, %mm0 -# CHECK-NEXT: [2,2] . D====================eeeER pcmpgtw %mm0, %mm0 -# CHECK-NEXT: [2,3] . D------------------------R pcmpgtb %xmm0, %xmm0 -# CHECK-NEXT: [2,4] . D------------------------R pcmpgtd %xmm0, %xmm0 -# CHECK-NEXT: [2,5] . D------------------------R pcmpgtq %xmm0, %xmm0 -# CHECK-NEXT: [2,6] . D-----------------------R pcmpgtw %xmm0, %xmm0 +# CHECK: [0,0] DeeER. . . . . . . . . . . pcmpgtb %mm0, %mm0 +# CHECK-NEXT: [0,1] D===eeER . . . . . . . . . . pcmpgtd %mm0, %mm0 +# CHECK-NEXT: [0,2] D======eeER . . . . . . . . . pcmpgtw %mm0, %mm0 +# CHECK-NEXT: [0,3] .DeeeE----R . . . . . . . . . pcmpgtb %xmm0, %xmm0 +# CHECK-NEXT: [0,4] .D=====eeeER . . . . . . . . . pcmpgtd %xmm0, %xmm0 +# CHECK-NEXT: [0,5] .D========eeeER. . . . . . . . . pcmpgtq %xmm0, %xmm0 +# CHECK-NEXT: [0,6] . D============eeeER. . . . . . . . pcmpgtw %xmm0, %xmm0 +# CHECK-NEXT: [1,0] . D=========eeE----R. . . . . . . . pcmpgtb %mm0, %mm0 +# CHECK-NEXT: [1,1] . D============eeE-R. . . . . . . . pcmpgtd %mm0, %mm0 +# CHECK-NEXT: [1,2] . D==============eeER . . . . . . . pcmpgtw %mm0, %mm0 +# CHECK-NEXT: [1,3] . D================eeeER. . . . . . . pcmpgtb %xmm0, %xmm0 +# CHECK-NEXT: [1,4] . D====================eeeER . . . . . . pcmpgtd %xmm0, %xmm0 +# CHECK-NEXT: [1,5] . D=======================eeeER . . . . . pcmpgtq %xmm0, %xmm0 +# CHECK-NEXT: [1,6] . D===========================eeeER . . . . pcmpgtw %xmm0, %xmm0 +# CHECK-NEXT: [2,0] . D================eeE------------R . . . . pcmpgtb %mm0, %mm0 +# CHECK-NEXT: [2,1] . D===================eeE--------R . . . . pcmpgtd %mm0, %mm0 +# CHECK-NEXT: [2,2] . D=======================eeE-----R . . . . pcmpgtw %mm0, %mm0 +# CHECK-NEXT: [2,3] . D==============================eeeER . . . pcmpgtb %xmm0, %xmm0 +# CHECK-NEXT: [2,4] . .D=================================eeeER. . . pcmpgtd %xmm0, %xmm0 +# CHECK-NEXT: [2,5] . .D=====================================eeeER . . pcmpgtq %xmm0, %xmm0 +# CHECK-NEXT: [2,6] . .D=========================================eeeER pcmpgtw %xmm0, %xmm0 # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -99,10 +114,10 @@ # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] -# CHECK-NEXT: 0. 3 8.7 0.3 0.0 pcmpgtb %mm0, %mm0 -# CHECK-NEXT: 1. 3 11.3 0.0 0.0 pcmpgtd %mm0, %mm0 -# CHECK-NEXT: 2. 3 14.0 0.0 0.0 pcmpgtw %mm0, %mm0 -# CHECK-NEXT: 3. 3 0.0 0.0 17.0 pcmpgtb %xmm0, %xmm0 -# CHECK-NEXT: 4. 3 0.0 0.0 16.7 pcmpgtd %xmm0, %xmm0 -# CHECK-NEXT: 5. 3 0.0 0.0 16.3 pcmpgtq %xmm0, %xmm0 -# CHECK-NEXT: 6. 3 0.0 0.0 16.0 pcmpgtw %xmm0, %xmm0 +# CHECK-NEXT: 0. 3 9.3 1.7 5.3 pcmpgtb %mm0, %mm0 +# CHECK-NEXT: 1. 3 12.3 1.3 3.0 pcmpgtd %mm0, %mm0 +# CHECK-NEXT: 2. 3 15.3 1.3 1.7 pcmpgtw %mm0, %mm0 +# CHECK-NEXT: 3. 3 16.3 1.3 1.3 pcmpgtb %xmm0, %xmm0 +# CHECK-NEXT: 4. 3 20.3 1.3 0.0 pcmpgtd %xmm0, %xmm0 +# CHECK-NEXT: 5. 3 23.7 0.7 0.0 pcmpgtq %xmm0, %xmm0 +# CHECK-NEXT: 6. 3 27.7 1.3 0.0 pcmpgtw %xmm0, %xmm0 diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-sbb-1.s b/llvm/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-sbb-1.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-sbb-1.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-sbb-1.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s # Although both SBB are dependency breaking instructions, there is still an # implicit dependency on EFLAGS which limits the ILP. So, the hardware backend @@ -11,12 +11,12 @@ # CHECK: Iterations: 1500 # CHECK-NEXT: Instructions: 3000 # CHECK-NEXT: Total Cycles: 6003 -# CHECK-NEXT: Total uOps: 6000 +# CHECK-NEXT: Total uOps: 3000 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.00 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.50 # CHECK-NEXT: IPC: 0.50 -# CHECK-NEXT: Block RThroughput: 1.0 +# CHECK-NEXT: Block RThroughput: 2.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -27,27 +27,42 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 2 2 0.67 sbbl %edx, %edx -# CHECK-NEXT: 2 2 0.67 sbbl %eax, %eax +# CHECK-NEXT: 1 2 1.00 sbbl %edx, %edx +# CHECK-NEXT: 1 2 1.00 sbbl %eax, %eax # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - 1.33 1.33 - 1.33 - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - 0.67 0.67 - 0.67 - - sbbl %edx, %edx -# CHECK-NEXT: - - 0.67 0.67 - 0.67 - - sbbl %eax, %eax +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sbbl %edx, %edx +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sbbl %eax, %eax # CHECK: Timeline view: # CHECK-NEXT: 01234 @@ -55,10 +70,10 @@ # CHECK: [0,0] DeeER. . . sbbl %edx, %edx # CHECK-NEXT: [0,1] D==eeER . . sbbl %eax, %eax -# CHECK-NEXT: [1,0] .D===eeER . . sbbl %edx, %edx +# CHECK-NEXT: [1,0] D====eeER . . sbbl %edx, %edx # CHECK-NEXT: [1,1] .D=====eeER . sbbl %eax, %eax -# CHECK-NEXT: [2,0] . D======eeER . sbbl %edx, %edx -# CHECK-NEXT: [2,1] . D========eeER sbbl %eax, %eax +# CHECK-NEXT: [2,0] .D=======eeER . sbbl %edx, %edx +# CHECK-NEXT: [2,1] .D=========eeER sbbl %eax, %eax # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -67,5 +82,5 @@ # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] -# CHECK-NEXT: 0. 3 4.0 0.3 0.0 sbbl %edx, %edx -# CHECK-NEXT: 1. 3 6.0 0.0 0.0 sbbl %eax, %eax +# CHECK-NEXT: 0. 3 4.7 0.3 0.0 sbbl %edx, %edx +# CHECK-NEXT: 1. 3 6.3 0.0 0.0 sbbl %eax, %eax diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-sbb-2.s b/llvm/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-sbb-2.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-sbb-2.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/dependency-breaking-sbb-2.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s # The SBB does not depend on the value of register EAX. That means, it doesn't # have to wait for the IMUL to write-back on EAX. However, it still depends on @@ -12,12 +12,12 @@ # CHECK: Iterations: 1500 # CHECK-NEXT: Instructions: 4500 # CHECK-NEXT: Total Cycles: 7503 -# CHECK-NEXT: Total uOps: 6000 +# CHECK-NEXT: Total uOps: 4500 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 0.80 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.60 # CHECK-NEXT: IPC: 0.60 -# CHECK-NEXT: Block RThroughput: 1.0 +# CHECK-NEXT: Block RThroughput: 2.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -28,42 +28,57 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 3 1.00 imull %edx, %eax -# CHECK-NEXT: 1 1 0.33 addl %edx, %edx -# CHECK-NEXT: 2 2 0.67 sbbl %eax, %eax +# CHECK-NEXT: 1 3 2.00 imull %edx, %eax +# CHECK-NEXT: 1 2 1.00 addl %edx, %edx +# CHECK-NEXT: 1 2 1.00 sbbl %eax, %eax # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - 1.33 1.33 - 1.33 - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - 2.00 1.00 1.00 1.00 - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - 1.00 - - - - imull %edx, %eax -# CHECK-NEXT: - - 0.33 0.33 - 0.34 - - addl %edx, %edx -# CHECK-NEXT: - - 1.00 - - 1.00 - - sbbl %eax, %eax +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 1.00 - - - - - - - - imull %edx, %eax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - - - 1.00 - - - - - - addl %edx, %edx +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - - 1.00 - - - - - - - sbbl %eax, %eax # CHECK: Timeline view: # CHECK-NEXT: 01234567 # CHECK-NEXT: Index 0123456789 # CHECK: [0,0] DeeeER . . . imull %edx, %eax -# CHECK-NEXT: [0,1] DeE--R . . . addl %edx, %edx +# CHECK-NEXT: [0,1] DeeE-R . . . addl %edx, %edx # CHECK-NEXT: [0,2] D===eeER . . . sbbl %eax, %eax # CHECK-NEXT: [1,0] .D====eeeER . . imull %edx, %eax -# CHECK-NEXT: [1,1] .DeE------R . . addl %edx, %edx +# CHECK-NEXT: [1,1] .D=eeE----R . . addl %edx, %edx # CHECK-NEXT: [1,2] .D=======eeER . . sbbl %eax, %eax # CHECK-NEXT: [2,0] . D========eeeER . imull %edx, %eax -# CHECK-NEXT: [2,1] . DeE----------R . addl %edx, %edx +# CHECK-NEXT: [2,1] . D==eeE-------R . addl %edx, %edx # CHECK-NEXT: [2,2] . D===========eeER sbbl %eax, %eax # CHECK: Average Wait times (based on the timeline view): @@ -74,5 +89,5 @@ # CHECK: [0] [1] [2] [3] # CHECK-NEXT: 0. 3 5.0 0.3 0.0 imull %edx, %eax -# CHECK-NEXT: 1. 3 1.0 0.3 6.0 addl %edx, %edx +# CHECK-NEXT: 1. 3 2.0 0.3 4.0 addl %edx, %edx # CHECK-NEXT: 2. 3 8.0 0.0 0.0 sbbl %eax, %eax diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/int-to-fpu-forwarding-1.s b/llvm/test/tools/llvm-mca/X86/Barcelona/int-to-fpu-forwarding-1.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/int-to-fpu-forwarding-1.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/int-to-fpu-forwarding-1.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=500 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -iterations=500 < %s | FileCheck %s # LLVM-MCA-BEGIN pinsrb $0, %eax, %xmm0 @@ -25,13 +25,13 @@ # CHECK: Iterations: 500 # CHECK-NEXT: Instructions: 1000 -# CHECK-NEXT: Total Cycles: 2003 +# CHECK-NEXT: Total Cycles: 3003 # CHECK-NEXT: Total uOps: 2000 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.00 -# CHECK-NEXT: IPC: 0.50 -# CHECK-NEXT: Block RThroughput: 2.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.67 +# CHECK-NEXT: IPC: 0.33 +# CHECK-NEXT: Block RThroughput: 6.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -42,39 +42,54 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 2 2 1.00 pinsrb $0, %eax, %xmm0 -# CHECK-NEXT: 2 2 1.00 pinsrb $1, %eax, %xmm0 +# CHECK-NEXT: 2 3 3.00 pinsrb $0, %eax, %xmm0 +# CHECK-NEXT: 2 3 3.00 pinsrb $1, %eax, %xmm0 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - 2.00 - 2.00 - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - - - - 6.00 - 6.00 1.00 1.00 - - - - - - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - 1.00 - 1.00 - - pinsrb $0, %eax, %xmm0 -# CHECK-NEXT: - - - 1.00 - 1.00 - - pinsrb $1, %eax, %xmm0 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - - - 6.00 - 1.00 - - - - - - - - - - - pinsrb $0, %eax, %xmm0 +# CHECK-NEXT: - - - - - - - 6.00 - - 1.00 - - - - - - - - - - - - pinsrb $1, %eax, %xmm0 # CHECK: [1] Code Region # CHECK: Iterations: 500 # CHECK-NEXT: Instructions: 1000 -# CHECK-NEXT: Total Cycles: 2003 +# CHECK-NEXT: Total Cycles: 3003 # CHECK-NEXT: Total uOps: 2000 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.00 -# CHECK-NEXT: IPC: 0.50 -# CHECK-NEXT: Block RThroughput: 2.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.67 +# CHECK-NEXT: IPC: 0.33 +# CHECK-NEXT: Block RThroughput: 6.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -85,39 +100,54 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 2 2 1.00 pinsrw $0, %eax, %xmm0 -# CHECK-NEXT: 2 2 1.00 pinsrw $1, %eax, %xmm0 +# CHECK-NEXT: 2 3 3.00 pinsrw $0, %eax, %xmm0 +# CHECK-NEXT: 2 3 3.00 pinsrw $1, %eax, %xmm0 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - 2.00 - 2.00 - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - - - - 6.00 - 6.00 1.00 1.00 - - - - - - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - 1.00 - 1.00 - - pinsrw $0, %eax, %xmm0 -# CHECK-NEXT: - - - 1.00 - 1.00 - - pinsrw $1, %eax, %xmm0 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - - - 6.00 - 1.00 - - - - - - - - - - - pinsrw $0, %eax, %xmm0 +# CHECK-NEXT: - - - - - - - 6.00 - - 1.00 - - - - - - - - - - - - pinsrw $1, %eax, %xmm0 # CHECK: [2] Code Region # CHECK: Iterations: 500 # CHECK-NEXT: Instructions: 1000 -# CHECK-NEXT: Total Cycles: 2003 +# CHECK-NEXT: Total Cycles: 3003 # CHECK-NEXT: Total uOps: 2000 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.00 -# CHECK-NEXT: IPC: 0.50 -# CHECK-NEXT: Block RThroughput: 2.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.67 +# CHECK-NEXT: IPC: 0.33 +# CHECK-NEXT: Block RThroughput: 6.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -128,39 +158,54 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 2 2 1.00 pinsrd $0, %eax, %xmm0 -# CHECK-NEXT: 2 2 1.00 pinsrd $1, %eax, %xmm0 +# CHECK-NEXT: 2 3 3.00 pinsrd $0, %eax, %xmm0 +# CHECK-NEXT: 2 3 3.00 pinsrd $1, %eax, %xmm0 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - 2.00 - 2.00 - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - - - - 6.00 - 6.00 1.00 1.00 - - - - - - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - 1.00 - 1.00 - - pinsrd $0, %eax, %xmm0 -# CHECK-NEXT: - - - 1.00 - 1.00 - - pinsrd $1, %eax, %xmm0 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - - - 6.00 - 1.00 - - - - - - - - - - - pinsrd $0, %eax, %xmm0 +# CHECK-NEXT: - - - - - - - 6.00 - - 1.00 - - - - - - - - - - - - pinsrd $1, %eax, %xmm0 # CHECK: [3] Code Region # CHECK: Iterations: 500 # CHECK-NEXT: Instructions: 1000 -# CHECK-NEXT: Total Cycles: 2003 +# CHECK-NEXT: Total Cycles: 3003 # CHECK-NEXT: Total uOps: 2000 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.00 -# CHECK-NEXT: IPC: 0.50 -# CHECK-NEXT: Block RThroughput: 2.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.67 +# CHECK-NEXT: IPC: 0.33 +# CHECK-NEXT: Block RThroughput: 6.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -171,24 +216,39 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 2 2 1.00 pinsrq $0, %rax, %xmm0 -# CHECK-NEXT: 2 2 1.00 pinsrq $1, %rax, %xmm0 +# CHECK-NEXT: 2 3 3.00 pinsrq $0, %rax, %xmm0 +# CHECK-NEXT: 2 3 3.00 pinsrq $1, %rax, %xmm0 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - 2.00 - 2.00 - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - - - - 6.00 - 6.00 1.00 1.00 - - - - - - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - 1.00 - 1.00 - - pinsrq $0, %rax, %xmm0 -# CHECK-NEXT: - - - 1.00 - 1.00 - - pinsrq $1, %rax, %xmm0 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - - - 6.00 - 1.00 - - - - - - - - - - - pinsrq $0, %rax, %xmm0 +# CHECK-NEXT: - - - - - - - 6.00 - - 1.00 - - - - - - - - - - - - pinsrq $1, %rax, %xmm0 diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/int-to-fpu-forwarding-2.s b/llvm/test/tools/llvm-mca/X86/Barcelona/int-to-fpu-forwarding-2.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/int-to-fpu-forwarding-2.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/int-to-fpu-forwarding-2.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=500 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -iterations=500 < %s | FileCheck %s # LLVM-MCA-BEGIN cvtsi2ss %ecx, %xmm0 @@ -21,13 +21,13 @@ # CHECK: Iterations: 500 # CHECK-NEXT: Instructions: 500 -# CHECK-NEXT: Total Cycles: 2503 +# CHECK-NEXT: Total Cycles: 1503 # CHECK-NEXT: Total uOps: 1500 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 0.60 -# CHECK-NEXT: IPC: 0.20 -# CHECK-NEXT: Block RThroughput: 2.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 1.00 +# CHECK-NEXT: IPC: 0.33 +# CHECK-NEXT: Block RThroughput: 3.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -38,37 +38,52 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 3 5 2.00 cvtsi2ss %ecx, %xmm0 +# CHECK-NEXT: 3 3 3.00 cvtsi2ss %ecx, %xmm0 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - 1.00 - 2.00 - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - - - - - 3.00 - - - 1.00 - - - - - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - 1.00 - 2.00 - - cvtsi2ss %ecx, %xmm0 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - - 3.00 - - - 1.00 - - - - - - - - - - cvtsi2ss %ecx, %xmm0 # CHECK: [1] Code Region # CHECK: Iterations: 500 # CHECK-NEXT: Instructions: 500 -# CHECK-NEXT: Total Cycles: 2003 -# CHECK-NEXT: Total uOps: 1000 +# CHECK-NEXT: Total Cycles: 1503 +# CHECK-NEXT: Total uOps: 1500 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 0.50 -# CHECK-NEXT: IPC: 0.25 -# CHECK-NEXT: Block RThroughput: 1.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 1.00 +# CHECK-NEXT: IPC: 0.33 +# CHECK-NEXT: Block RThroughput: 3.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -79,37 +94,52 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 2 4 1.00 cvtsi2sd %ecx, %xmm0 +# CHECK-NEXT: 3 3 3.00 cvtsi2sd %ecx, %xmm0 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - 1.00 - 1.00 - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - - - - - 3.00 - - - 1.00 - - - - - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtsi2sd %ecx, %xmm0 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - - 3.00 - - - 1.00 - - - - - - - - - - cvtsi2sd %ecx, %xmm0 # CHECK: [2] Code Region # CHECK: Iterations: 500 # CHECK-NEXT: Instructions: 500 -# CHECK-NEXT: Total Cycles: 503 -# CHECK-NEXT: Total uOps: 500 +# CHECK-NEXT: Total Cycles: 1504 +# CHECK-NEXT: Total uOps: 1000 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 0.99 -# CHECK-NEXT: IPC: 0.99 -# CHECK-NEXT: Block RThroughput: 1.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.66 +# CHECK-NEXT: IPC: 0.33 +# CHECK-NEXT: Block RThroughput: 3.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -120,37 +150,52 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 1 1.00 movd %ecx, %xmm0 +# CHECK-NEXT: 2 6 3.00 movd %ecx, %xmm0 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - - - 1.00 - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - - - - 2.99 3.01 3.01 0.33 0.33 0.33 - - - - - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - - 1.00 - - movd %ecx, %xmm0 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - 2.99 3.01 3.01 0.33 0.33 0.33 - - - - - - - - - - movd %ecx, %xmm0 # CHECK: [3] Code Region # CHECK: Iterations: 500 # CHECK-NEXT: Instructions: 500 -# CHECK-NEXT: Total Cycles: 503 -# CHECK-NEXT: Total uOps: 500 +# CHECK-NEXT: Total Cycles: 1504 +# CHECK-NEXT: Total uOps: 1000 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 0.99 -# CHECK-NEXT: IPC: 0.99 -# CHECK-NEXT: Block RThroughput: 1.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.66 +# CHECK-NEXT: IPC: 0.33 +# CHECK-NEXT: Block RThroughput: 3.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -161,22 +206,37 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 1 1.00 movq %rcx, %xmm0 +# CHECK-NEXT: 2 6 3.00 movq %rcx, %xmm0 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - - - 1.00 - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - - - - 2.99 3.01 3.01 0.33 0.33 0.33 - - - - - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - - 1.00 - - movq %rcx, %xmm0 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - 2.99 3.01 3.01 0.33 0.33 0.33 - - - - - - - - - - movq %rcx, %xmm0 diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/int-to-fpu-forwarding-3.s b/llvm/test/tools/llvm-mca/X86/Barcelona/int-to-fpu-forwarding-3.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/int-to-fpu-forwarding-3.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/int-to-fpu-forwarding-3.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -iterations=500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s add %eax, %eax pinsrw $0, %eax, %xmm0 @@ -7,13 +7,13 @@ # CHECK: Iterations: 500 # CHECK-NEXT: Instructions: 1500 -# CHECK-NEXT: Total Cycles: 2004 +# CHECK-NEXT: Total Cycles: 3005 # CHECK-NEXT: Total uOps: 2500 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.25 -# CHECK-NEXT: IPC: 0.75 -# CHECK-NEXT: Block RThroughput: 2.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.83 +# CHECK-NEXT: IPC: 0.50 +# CHECK-NEXT: Block RThroughput: 6.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -24,43 +24,58 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 1 0.33 addl %eax, %eax -# CHECK-NEXT: 2 2 1.00 pinsrw $0, %eax, %xmm0 -# CHECK-NEXT: 2 2 1.00 pinsrw $1, %eax, %xmm0 +# CHECK-NEXT: 1 2 1.00 addl %eax, %eax +# CHECK-NEXT: 2 3 3.00 pinsrw $0, %eax, %xmm0 +# CHECK-NEXT: 2 3 3.00 pinsrw $1, %eax, %xmm0 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - 0.98 2.01 - 2.01 - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - 1.00 1.00 1.00 6.00 - 6.00 1.00 1.00 - - 0.33 0.33 0.33 - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - 0.98 0.01 - 0.01 - - addl %eax, %eax -# CHECK-NEXT: - - - 1.00 - 1.00 - - pinsrw $0, %eax, %xmm0 -# CHECK-NEXT: - - - 1.00 - 1.00 - - pinsrw $1, %eax, %xmm0 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - addl %eax, %eax +# CHECK-NEXT: - - - - - - - - - 6.00 - 1.00 - - - - - - - - - - - pinsrw $0, %eax, %xmm0 +# CHECK-NEXT: - - - - - - - 6.00 - - 1.00 - - - - - - - - - - - - pinsrw $1, %eax, %xmm0 # CHECK: Timeline view: -# CHECK-NEXT: 012345 -# CHECK-NEXT: Index 0123456789 +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 012 -# CHECK: [0,0] DeER . . . addl %eax, %eax -# CHECK-NEXT: [0,1] D=eeER . . pinsrw $0, %eax, %xmm0 -# CHECK-NEXT: [0,2] .D==eeER . . pinsrw $1, %eax, %xmm0 -# CHECK-NEXT: [1,0] .DeE---R . . addl %eax, %eax -# CHECK-NEXT: [1,1] . D===eeER. . pinsrw $0, %eax, %xmm0 -# CHECK-NEXT: [1,2] . D=====eeER . pinsrw $1, %eax, %xmm0 -# CHECK-NEXT: [2,0] . DeE-----R . addl %eax, %eax -# CHECK-NEXT: [2,1] . D======eeER . pinsrw $0, %eax, %xmm0 -# CHECK-NEXT: [2,2] . D=======eeER pinsrw $1, %eax, %xmm0 +# CHECK: [0,0] DeeER. . . . . addl %eax, %eax +# CHECK-NEXT: [0,1] D==eeeER . . . . pinsrw $0, %eax, %xmm0 +# CHECK-NEXT: [0,2] .D====eeeER . . . pinsrw $1, %eax, %xmm0 +# CHECK-NEXT: [1,0] .D=eeE----R . . . addl %eax, %eax +# CHECK-NEXT: [1,1] . D======eeeER . . . pinsrw $0, %eax, %xmm0 +# CHECK-NEXT: [1,2] . D========eeeER . . pinsrw $1, %eax, %xmm0 +# CHECK-NEXT: [2,0] . D=eeE--------R . . addl %eax, %eax +# CHECK-NEXT: [2,1] . D==========eeeER. . pinsrw $0, %eax, %xmm0 +# CHECK-NEXT: [2,2] . D============eeeER pinsrw $1, %eax, %xmm0 # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -69,6 +84,6 @@ # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] -# CHECK-NEXT: 0. 3 1.0 0.7 2.7 addl %eax, %eax -# CHECK-NEXT: 1. 3 4.3 0.0 0.0 pinsrw $0, %eax, %xmm0 -# CHECK-NEXT: 2. 3 5.7 0.0 0.0 pinsrw $1, %eax, %xmm0 +# CHECK-NEXT: 0. 3 1.7 0.3 4.0 addl %eax, %eax +# CHECK-NEXT: 1. 3 7.0 0.0 0.0 pinsrw $0, %eax, %xmm0 +# CHECK-NEXT: 2. 3 9.0 0.0 0.0 pinsrw $1, %eax, %xmm0 diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/load-store-throughput.s b/llvm/test/tools/llvm-mca/X86/Barcelona/load-store-throughput.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/load-store-throughput.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/load-store-throughput.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -scheduler-stats -dispatch-stats -iterations=100 -timeline -timeline-max-iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -scheduler-stats -dispatch-stats -iterations=100 -timeline -timeline-max-iterations=1 < %s | FileCheck %s # LLVM-MCA-BEGIN movb %spl, (%rax) @@ -47,12 +47,12 @@ # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 400 -# CHECK-NEXT: Total Cycles: 208 +# CHECK-NEXT: Total Cycles: 605 # CHECK-NEXT: Total uOps: 400 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.92 -# CHECK-NEXT: IPC: 1.92 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.66 +# CHECK-NEXT: IPC: 0.66 # CHECK-NEXT: Block RThroughput: 2.0 # CHECK: Instruction Info: @@ -64,30 +64,31 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 1 1.00 * movb %spl, (%rax) -# CHECK-NEXT: 1 5 0.50 * movb (%rcx), %bpl -# CHECK-NEXT: 1 5 0.50 * movb (%rdx), %sil -# CHECK-NEXT: 1 1 1.00 * movb %dil, (%rbx) +# CHECK-NEXT: 1 3 0.50 * movb %spl, (%rax) +# CHECK-NEXT: 1 4 0.50 * movb (%rcx), %bpl +# CHECK-NEXT: 1 4 0.50 * movb (%rdx), %sil +# CHECK-NEXT: 1 3 0.50 * movb %dil, (%rbx) # CHECK: Dynamic Dispatch Stall Cycles: # CHECK-NEXT: RAT - Register unavailable: 0 # CHECK-NEXT: RCU - Retire tokens unavailable: 0 -# CHECK-NEXT: SCHEDQ - Scheduler full: 147 (70.7%) +# CHECK-NEXT: SCHEDQ - Scheduler full: 511 (84.5%) # CHECK-NEXT: LQ - Load queue full: 0 # CHECK-NEXT: SQ - Store queue full: 0 # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK-NEXT: [# dispatched], [# cycles] -# CHECK-NEXT: 0, 34 (16.3%) -# CHECK-NEXT: 2, 148 (71.2%) -# CHECK-NEXT: 4, 26 (12.5%) +# CHECK-NEXT: 0, 244 (40.3%) +# CHECK-NEXT: 1, 341 (56.4%) +# CHECK-NEXT: 2, 1 (0.2%) +# CHECK-NEXT: 3, 19 (3.1%) # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: # CHECK-NEXT: [# issued], [# cycles] -# CHECK-NEXT: 0, 3 (1.4%) -# CHECK-NEXT: 1, 10 (4.8%) -# CHECK-NEXT: 2, 195 (93.8%) +# CHECK-NEXT: 0, 221 (36.5%) +# CHECK-NEXT: 1, 368 (60.8%) +# CHECK-NEXT: 2, 16 (2.6%) # CHECK: Scheduler's queue usage: # CHECK-NEXT: [1] Resource name. @@ -96,36 +97,55 @@ # CHECK-NEXT: [4] Total number of buffer entries. # CHECK: [1] [2] [3] [4] -# CHECK-NEXT: SBPortAny 45 54 54 +# CHECK-NEXT: BnFPU 0 0 36 +# CHECK-NEXT: BnInt 22 24 24 +# CHECK-NEXT: BnLoad 1 9 12 +# CHECK-NEXT: BnStore 22 25 32 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - - 2.00 - 2.00 2.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - 1.33 1.33 1.34 - - - - - - - - - - 1.33 1.33 1.34 2.00 2.00 1.00 1.00 1.00 1.00 # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - 1.00 - - 1.00 movb %spl, (%rax) -# CHECK-NEXT: - - - - - - 1.00 - movb (%rcx), %bpl -# CHECK-NEXT: - - - - - - 0.95 0.05 movb (%rdx), %sil -# CHECK-NEXT: - - - - 1.00 - 0.05 0.95 movb %dil, (%rbx) +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - 0.34 0.33 0.33 - - - - - - - - - - 0.34 0.33 0.33 0.02 0.98 - - - 1.00 movb %spl, (%rax) +# CHECK-NEXT: - 0.34 0.33 0.33 - - - - - - - - - - 0.34 0.33 0.33 0.08 0.92 - 1.00 - - movb (%rcx), %bpl +# CHECK-NEXT: - 0.33 0.32 0.35 - - - - - - - - - - 0.33 0.32 0.35 0.90 0.10 1.00 - - - movb (%rdx), %sil +# CHECK-NEXT: - 0.32 0.35 0.33 - - - - - - - - - - 0.32 0.35 0.33 1.00 - - - 1.00 - movb %dil, (%rbx) # CHECK: Timeline view: +# CHECK-NEXT: 0 # CHECK-NEXT: Index 0123456789 -# CHECK: [0,0] DeER . . movb %spl, (%rax) -# CHECK-NEXT: [0,1] DeeeeeER . movb (%rcx), %bpl -# CHECK-NEXT: [0,2] D=eeeeeER. movb (%rdx), %sil -# CHECK-NEXT: [0,3] D======eER movb %dil, (%rbx) +# CHECK: [0,0] DeeeER . movb %spl, (%rax) +# CHECK-NEXT: [0,1] DeeeeER . movb (%rcx), %bpl +# CHECK-NEXT: [0,2] D=eeeeER . movb (%rdx), %sil +# CHECK-NEXT: [0,3] .D====eeeER movb %dil, (%rbx) # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -137,18 +157,18 @@ # CHECK-NEXT: 0. 1 1.0 1.0 0.0 movb %spl, (%rax) # CHECK-NEXT: 1. 1 1.0 1.0 0.0 movb (%rcx), %bpl # CHECK-NEXT: 2. 1 2.0 2.0 0.0 movb (%rdx), %sil -# CHECK-NEXT: 3. 1 7.0 0.0 0.0 movb %dil, (%rbx) +# CHECK-NEXT: 3. 1 5.0 0.0 0.0 movb %dil, (%rbx) # CHECK: [1] Code Region # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 400 -# CHECK-NEXT: Total Cycles: 208 +# CHECK-NEXT: Total Cycles: 605 # CHECK-NEXT: Total uOps: 400 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.92 -# CHECK-NEXT: IPC: 1.92 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.66 +# CHECK-NEXT: IPC: 0.66 # CHECK-NEXT: Block RThroughput: 2.0 # CHECK: Instruction Info: @@ -160,30 +180,31 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 1 1.00 * movw %sp, (%rax) -# CHECK-NEXT: 1 5 0.50 * movw (%rcx), %bp -# CHECK-NEXT: 1 5 0.50 * movw (%rdx), %si -# CHECK-NEXT: 1 1 1.00 * movw %di, (%rbx) +# CHECK-NEXT: 1 3 0.50 * movw %sp, (%rax) +# CHECK-NEXT: 1 4 0.50 * movw (%rcx), %bp +# CHECK-NEXT: 1 4 0.50 * movw (%rdx), %si +# CHECK-NEXT: 1 3 0.50 * movw %di, (%rbx) # CHECK: Dynamic Dispatch Stall Cycles: # CHECK-NEXT: RAT - Register unavailable: 0 # CHECK-NEXT: RCU - Retire tokens unavailable: 0 -# CHECK-NEXT: SCHEDQ - Scheduler full: 147 (70.7%) +# CHECK-NEXT: SCHEDQ - Scheduler full: 511 (84.5%) # CHECK-NEXT: LQ - Load queue full: 0 # CHECK-NEXT: SQ - Store queue full: 0 # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK-NEXT: [# dispatched], [# cycles] -# CHECK-NEXT: 0, 34 (16.3%) -# CHECK-NEXT: 2, 148 (71.2%) -# CHECK-NEXT: 4, 26 (12.5%) +# CHECK-NEXT: 0, 244 (40.3%) +# CHECK-NEXT: 1, 341 (56.4%) +# CHECK-NEXT: 2, 1 (0.2%) +# CHECK-NEXT: 3, 19 (3.1%) # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: # CHECK-NEXT: [# issued], [# cycles] -# CHECK-NEXT: 0, 3 (1.4%) -# CHECK-NEXT: 1, 10 (4.8%) -# CHECK-NEXT: 2, 195 (93.8%) +# CHECK-NEXT: 0, 221 (36.5%) +# CHECK-NEXT: 1, 368 (60.8%) +# CHECK-NEXT: 2, 16 (2.6%) # CHECK: Scheduler's queue usage: # CHECK-NEXT: [1] Resource name. @@ -192,36 +213,55 @@ # CHECK-NEXT: [4] Total number of buffer entries. # CHECK: [1] [2] [3] [4] -# CHECK-NEXT: SBPortAny 45 54 54 +# CHECK-NEXT: BnFPU 0 0 36 +# CHECK-NEXT: BnInt 22 24 24 +# CHECK-NEXT: BnLoad 1 9 12 +# CHECK-NEXT: BnStore 22 25 32 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - - 2.00 - 2.00 2.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - 1.33 1.33 1.34 - - - - - - - - - - 1.33 1.33 1.34 2.00 2.00 1.00 1.00 1.00 1.00 # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - 1.00 - - 1.00 movw %sp, (%rax) -# CHECK-NEXT: - - - - - - 1.00 - movw (%rcx), %bp -# CHECK-NEXT: - - - - - - 0.95 0.05 movw (%rdx), %si -# CHECK-NEXT: - - - - 1.00 - 0.05 0.95 movw %di, (%rbx) +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - 0.34 0.33 0.33 - - - - - - - - - - 0.34 0.33 0.33 0.02 0.98 - - - 1.00 movw %sp, (%rax) +# CHECK-NEXT: - 0.34 0.33 0.33 - - - - - - - - - - 0.34 0.33 0.33 0.08 0.92 - 1.00 - - movw (%rcx), %bp +# CHECK-NEXT: - 0.33 0.32 0.35 - - - - - - - - - - 0.33 0.32 0.35 0.90 0.10 1.00 - - - movw (%rdx), %si +# CHECK-NEXT: - 0.32 0.35 0.33 - - - - - - - - - - 0.32 0.35 0.33 1.00 - - - 1.00 - movw %di, (%rbx) # CHECK: Timeline view: +# CHECK-NEXT: 0 # CHECK-NEXT: Index 0123456789 -# CHECK: [0,0] DeER . . movw %sp, (%rax) -# CHECK-NEXT: [0,1] DeeeeeER . movw (%rcx), %bp -# CHECK-NEXT: [0,2] D=eeeeeER. movw (%rdx), %si -# CHECK-NEXT: [0,3] D======eER movw %di, (%rbx) +# CHECK: [0,0] DeeeER . movw %sp, (%rax) +# CHECK-NEXT: [0,1] DeeeeER . movw (%rcx), %bp +# CHECK-NEXT: [0,2] D=eeeeER . movw (%rdx), %si +# CHECK-NEXT: [0,3] .D====eeeER movw %di, (%rbx) # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -233,18 +273,18 @@ # CHECK-NEXT: 0. 1 1.0 1.0 0.0 movw %sp, (%rax) # CHECK-NEXT: 1. 1 1.0 1.0 0.0 movw (%rcx), %bp # CHECK-NEXT: 2. 1 2.0 2.0 0.0 movw (%rdx), %si -# CHECK-NEXT: 3. 1 7.0 0.0 0.0 movw %di, (%rbx) +# CHECK-NEXT: 3. 1 5.0 0.0 0.0 movw %di, (%rbx) # CHECK: [2] Code Region # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 400 -# CHECK-NEXT: Total Cycles: 208 +# CHECK-NEXT: Total Cycles: 605 # CHECK-NEXT: Total uOps: 400 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.92 -# CHECK-NEXT: IPC: 1.92 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.66 +# CHECK-NEXT: IPC: 0.66 # CHECK-NEXT: Block RThroughput: 2.0 # CHECK: Instruction Info: @@ -256,30 +296,31 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 1 1.00 * movl %esp, (%rax) -# CHECK-NEXT: 1 5 0.50 * movl (%rcx), %ebp -# CHECK-NEXT: 1 5 0.50 * movl (%rdx), %esi -# CHECK-NEXT: 1 1 1.00 * movl %edi, (%rbx) +# CHECK-NEXT: 1 3 0.50 * movl %esp, (%rax) +# CHECK-NEXT: 1 4 0.50 * movl (%rcx), %ebp +# CHECK-NEXT: 1 4 0.50 * movl (%rdx), %esi +# CHECK-NEXT: 1 3 0.50 * movl %edi, (%rbx) # CHECK: Dynamic Dispatch Stall Cycles: # CHECK-NEXT: RAT - Register unavailable: 0 # CHECK-NEXT: RCU - Retire tokens unavailable: 0 -# CHECK-NEXT: SCHEDQ - Scheduler full: 147 (70.7%) +# CHECK-NEXT: SCHEDQ - Scheduler full: 511 (84.5%) # CHECK-NEXT: LQ - Load queue full: 0 # CHECK-NEXT: SQ - Store queue full: 0 # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK-NEXT: [# dispatched], [# cycles] -# CHECK-NEXT: 0, 34 (16.3%) -# CHECK-NEXT: 2, 148 (71.2%) -# CHECK-NEXT: 4, 26 (12.5%) +# CHECK-NEXT: 0, 244 (40.3%) +# CHECK-NEXT: 1, 341 (56.4%) +# CHECK-NEXT: 2, 1 (0.2%) +# CHECK-NEXT: 3, 19 (3.1%) # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: # CHECK-NEXT: [# issued], [# cycles] -# CHECK-NEXT: 0, 3 (1.4%) -# CHECK-NEXT: 1, 10 (4.8%) -# CHECK-NEXT: 2, 195 (93.8%) +# CHECK-NEXT: 0, 221 (36.5%) +# CHECK-NEXT: 1, 368 (60.8%) +# CHECK-NEXT: 2, 16 (2.6%) # CHECK: Scheduler's queue usage: # CHECK-NEXT: [1] Resource name. @@ -288,36 +329,55 @@ # CHECK-NEXT: [4] Total number of buffer entries. # CHECK: [1] [2] [3] [4] -# CHECK-NEXT: SBPortAny 45 54 54 +# CHECK-NEXT: BnFPU 0 0 36 +# CHECK-NEXT: BnInt 22 24 24 +# CHECK-NEXT: BnLoad 1 9 12 +# CHECK-NEXT: BnStore 22 25 32 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - - 2.00 - 2.00 2.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - 1.33 1.33 1.34 - - - - - - - - - - 1.33 1.33 1.34 2.00 2.00 1.00 1.00 1.00 1.00 # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - 1.00 - - 1.00 movl %esp, (%rax) -# CHECK-NEXT: - - - - - - 1.00 - movl (%rcx), %ebp -# CHECK-NEXT: - - - - - - 0.95 0.05 movl (%rdx), %esi -# CHECK-NEXT: - - - - 1.00 - 0.05 0.95 movl %edi, (%rbx) +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - 0.34 0.33 0.33 - - - - - - - - - - 0.34 0.33 0.33 0.02 0.98 - - - 1.00 movl %esp, (%rax) +# CHECK-NEXT: - 0.34 0.33 0.33 - - - - - - - - - - 0.34 0.33 0.33 0.08 0.92 - 1.00 - - movl (%rcx), %ebp +# CHECK-NEXT: - 0.33 0.32 0.35 - - - - - - - - - - 0.33 0.32 0.35 0.90 0.10 1.00 - - - movl (%rdx), %esi +# CHECK-NEXT: - 0.32 0.35 0.33 - - - - - - - - - - 0.32 0.35 0.33 1.00 - - - 1.00 - movl %edi, (%rbx) # CHECK: Timeline view: +# CHECK-NEXT: 0 # CHECK-NEXT: Index 0123456789 -# CHECK: [0,0] DeER . . movl %esp, (%rax) -# CHECK-NEXT: [0,1] DeeeeeER . movl (%rcx), %ebp -# CHECK-NEXT: [0,2] D=eeeeeER. movl (%rdx), %esi -# CHECK-NEXT: [0,3] D======eER movl %edi, (%rbx) +# CHECK: [0,0] DeeeER . movl %esp, (%rax) +# CHECK-NEXT: [0,1] DeeeeER . movl (%rcx), %ebp +# CHECK-NEXT: [0,2] D=eeeeER . movl (%rdx), %esi +# CHECK-NEXT: [0,3] .D====eeeER movl %edi, (%rbx) # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -329,18 +389,18 @@ # CHECK-NEXT: 0. 1 1.0 1.0 0.0 movl %esp, (%rax) # CHECK-NEXT: 1. 1 1.0 1.0 0.0 movl (%rcx), %ebp # CHECK-NEXT: 2. 1 2.0 2.0 0.0 movl (%rdx), %esi -# CHECK-NEXT: 3. 1 7.0 0.0 0.0 movl %edi, (%rbx) +# CHECK-NEXT: 3. 1 5.0 0.0 0.0 movl %edi, (%rbx) # CHECK: [3] Code Region # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 400 -# CHECK-NEXT: Total Cycles: 208 +# CHECK-NEXT: Total Cycles: 605 # CHECK-NEXT: Total uOps: 400 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.92 -# CHECK-NEXT: IPC: 1.92 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.66 +# CHECK-NEXT: IPC: 0.66 # CHECK-NEXT: Block RThroughput: 2.0 # CHECK: Instruction Info: @@ -352,30 +412,31 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 1 1.00 * movq %rsp, (%rax) -# CHECK-NEXT: 1 5 0.50 * movq (%rcx), %rbp -# CHECK-NEXT: 1 5 0.50 * movq (%rdx), %rsi -# CHECK-NEXT: 1 1 1.00 * movq %rdi, (%rbx) +# CHECK-NEXT: 1 3 0.50 * movq %rsp, (%rax) +# CHECK-NEXT: 1 4 0.50 * movq (%rcx), %rbp +# CHECK-NEXT: 1 4 0.50 * movq (%rdx), %rsi +# CHECK-NEXT: 1 3 0.50 * movq %rdi, (%rbx) # CHECK: Dynamic Dispatch Stall Cycles: # CHECK-NEXT: RAT - Register unavailable: 0 # CHECK-NEXT: RCU - Retire tokens unavailable: 0 -# CHECK-NEXT: SCHEDQ - Scheduler full: 147 (70.7%) +# CHECK-NEXT: SCHEDQ - Scheduler full: 511 (84.5%) # CHECK-NEXT: LQ - Load queue full: 0 # CHECK-NEXT: SQ - Store queue full: 0 # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK-NEXT: [# dispatched], [# cycles] -# CHECK-NEXT: 0, 34 (16.3%) -# CHECK-NEXT: 2, 148 (71.2%) -# CHECK-NEXT: 4, 26 (12.5%) +# CHECK-NEXT: 0, 244 (40.3%) +# CHECK-NEXT: 1, 341 (56.4%) +# CHECK-NEXT: 2, 1 (0.2%) +# CHECK-NEXT: 3, 19 (3.1%) # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: # CHECK-NEXT: [# issued], [# cycles] -# CHECK-NEXT: 0, 3 (1.4%) -# CHECK-NEXT: 1, 10 (4.8%) -# CHECK-NEXT: 2, 195 (93.8%) +# CHECK-NEXT: 0, 221 (36.5%) +# CHECK-NEXT: 1, 368 (60.8%) +# CHECK-NEXT: 2, 16 (2.6%) # CHECK: Scheduler's queue usage: # CHECK-NEXT: [1] Resource name. @@ -384,36 +445,55 @@ # CHECK-NEXT: [4] Total number of buffer entries. # CHECK: [1] [2] [3] [4] -# CHECK-NEXT: SBPortAny 45 54 54 +# CHECK-NEXT: BnFPU 0 0 36 +# CHECK-NEXT: BnInt 22 24 24 +# CHECK-NEXT: BnLoad 1 9 12 +# CHECK-NEXT: BnStore 22 25 32 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - - 2.00 - 2.00 2.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - 1.33 1.33 1.34 - - - - - - - - - - 1.33 1.33 1.34 2.00 2.00 1.00 1.00 1.00 1.00 # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - 1.00 - - 1.00 movq %rsp, (%rax) -# CHECK-NEXT: - - - - - - 1.00 - movq (%rcx), %rbp -# CHECK-NEXT: - - - - - - 0.95 0.05 movq (%rdx), %rsi -# CHECK-NEXT: - - - - 1.00 - 0.05 0.95 movq %rdi, (%rbx) +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - 0.34 0.33 0.33 - - - - - - - - - - 0.34 0.33 0.33 0.02 0.98 - - - 1.00 movq %rsp, (%rax) +# CHECK-NEXT: - 0.34 0.33 0.33 - - - - - - - - - - 0.34 0.33 0.33 0.08 0.92 - 1.00 - - movq (%rcx), %rbp +# CHECK-NEXT: - 0.33 0.32 0.35 - - - - - - - - - - 0.33 0.32 0.35 0.90 0.10 1.00 - - - movq (%rdx), %rsi +# CHECK-NEXT: - 0.32 0.35 0.33 - - - - - - - - - - 0.32 0.35 0.33 1.00 - - - 1.00 - movq %rdi, (%rbx) # CHECK: Timeline view: +# CHECK-NEXT: 0 # CHECK-NEXT: Index 0123456789 -# CHECK: [0,0] DeER . . movq %rsp, (%rax) -# CHECK-NEXT: [0,1] DeeeeeER . movq (%rcx), %rbp -# CHECK-NEXT: [0,2] D=eeeeeER. movq (%rdx), %rsi -# CHECK-NEXT: [0,3] D======eER movq %rdi, (%rbx) +# CHECK: [0,0] DeeeER . movq %rsp, (%rax) +# CHECK-NEXT: [0,1] DeeeeER . movq (%rcx), %rbp +# CHECK-NEXT: [0,2] D=eeeeER . movq (%rdx), %rsi +# CHECK-NEXT: [0,3] .D====eeeER movq %rdi, (%rbx) # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -425,18 +505,18 @@ # CHECK-NEXT: 0. 1 1.0 1.0 0.0 movq %rsp, (%rax) # CHECK-NEXT: 1. 1 1.0 1.0 0.0 movq (%rcx), %rbp # CHECK-NEXT: 2. 1 2.0 2.0 0.0 movq (%rdx), %rsi -# CHECK-NEXT: 3. 1 7.0 0.0 0.0 movq %rdi, (%rbx) +# CHECK-NEXT: 3. 1 5.0 0.0 0.0 movq %rdi, (%rbx) # CHECK: [4] Code Region # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 400 -# CHECK-NEXT: Total Cycles: 208 +# CHECK-NEXT: Total Cycles: 405 # CHECK-NEXT: Total uOps: 400 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.92 -# CHECK-NEXT: IPC: 1.92 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.99 +# CHECK-NEXT: IPC: 0.99 # CHECK-NEXT: Block RThroughput: 2.0 # CHECK: Instruction Info: @@ -448,30 +528,30 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 1 1.00 * U movd %mm0, (%rax) -# CHECK-NEXT: 1 5 0.50 * movd (%rcx), %mm1 -# CHECK-NEXT: 1 5 0.50 * movd (%rdx), %mm2 -# CHECK-NEXT: 1 1 1.00 * U movd %mm3, (%rbx) +# CHECK-NEXT: 1 2 1.00 * U movd %mm0, (%rax) +# CHECK-NEXT: 1 3 0.50 * movd (%rcx), %mm1 +# CHECK-NEXT: 1 3 0.50 * movd (%rdx), %mm2 +# CHECK-NEXT: 1 2 1.00 * U movd %mm3, (%rbx) # CHECK: Dynamic Dispatch Stall Cycles: # CHECK-NEXT: RAT - Register unavailable: 0 # CHECK-NEXT: RCU - Retire tokens unavailable: 0 -# CHECK-NEXT: SCHEDQ - Scheduler full: 147 (70.7%) +# CHECK-NEXT: SCHEDQ - Scheduler full: 0 # CHECK-NEXT: LQ - Load queue full: 0 -# CHECK-NEXT: SQ - Store queue full: 0 +# CHECK-NEXT: SQ - Store queue full: 232 (57.3%) # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK-NEXT: [# dispatched], [# cycles] -# CHECK-NEXT: 0, 34 (16.3%) -# CHECK-NEXT: 2, 148 (71.2%) -# CHECK-NEXT: 4, 26 (12.5%) +# CHECK-NEXT: 0, 219 (54.1%) +# CHECK-NEXT: 1, 79 (19.5%) +# CHECK-NEXT: 3, 107 (26.4%) # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: # CHECK-NEXT: [# issued], [# cycles] -# CHECK-NEXT: 0, 3 (1.4%) -# CHECK-NEXT: 1, 10 (4.8%) -# CHECK-NEXT: 2, 195 (93.8%) +# CHECK-NEXT: 0, 112 (27.7%) +# CHECK-NEXT: 1, 186 (45.9%) +# CHECK-NEXT: 2, 107 (26.4%) # CHECK: Scheduler's queue usage: # CHECK-NEXT: [1] Resource name. @@ -480,36 +560,54 @@ # CHECK-NEXT: [4] Total number of buffer entries. # CHECK: [1] [2] [3] [4] -# CHECK-NEXT: SBPortAny 45 54 54 +# CHECK-NEXT: BnFPU 27 33 36 +# CHECK-NEXT: BnInt 0 0 24 +# CHECK-NEXT: BnLoad 2 7 12 +# CHECK-NEXT: BnStore 28 32 32 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - - 2.00 - 2.00 2.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - - - - 0.97 2.06 0.97 0.97 0.97 2.06 - - - - 2.00 2.00 1.00 1.00 1.00 1.00 # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - 1.00 - - 1.00 movd %mm0, (%rax) -# CHECK-NEXT: - - - - - - 1.00 - movd (%rcx), %mm1 -# CHECK-NEXT: - - - - - - 0.95 0.05 movd (%rdx), %mm2 -# CHECK-NEXT: - - - - 1.00 - 0.05 0.95 movd %mm3, (%rbx) +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 0.07 0.93 - - - 1.00 movd %mm0, (%rax) +# CHECK-NEXT: - - - - - - - 0.10 0.03 0.87 0.09 0.88 0.03 - - - - 0.09 0.91 - 1.00 - - movd (%rcx), %mm1 +# CHECK-NEXT: - - - - - - - 0.87 0.03 0.10 0.88 0.09 0.03 - - - - 0.84 0.16 1.00 - - - movd (%rdx), %mm2 +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 1.00 - - - 1.00 - movd %mm3, (%rbx) # CHECK: Timeline view: -# CHECK-NEXT: Index 0123456789 +# CHECK-NEXT: Index 012345678 -# CHECK: [0,0] DeER . . movd %mm0, (%rax) -# CHECK-NEXT: [0,1] DeeeeeER . movd (%rcx), %mm1 -# CHECK-NEXT: [0,2] D=eeeeeER. movd (%rdx), %mm2 -# CHECK-NEXT: [0,3] D======eER movd %mm3, (%rbx) +# CHECK: [0,0] DeeER. . movd %mm0, (%rax) +# CHECK-NEXT: [0,1] DeeeER . movd (%rcx), %mm1 +# CHECK-NEXT: [0,2] D=eeeER . movd (%rdx), %mm2 +# CHECK-NEXT: [0,3] .D===eeER movd %mm3, (%rbx) # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -521,19 +619,19 @@ # CHECK-NEXT: 0. 1 1.0 1.0 0.0 movd %mm0, (%rax) # CHECK-NEXT: 1. 1 1.0 1.0 0.0 movd (%rcx), %mm1 # CHECK-NEXT: 2. 1 2.0 2.0 0.0 movd (%rdx), %mm2 -# CHECK-NEXT: 3. 1 7.0 0.0 0.0 movd %mm3, (%rbx) +# CHECK-NEXT: 3. 1 4.0 0.0 0.0 movd %mm3, (%rbx) # CHECK: [5] Code Region # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 400 -# CHECK-NEXT: Total Cycles: 209 -# CHECK-NEXT: Total uOps: 400 +# CHECK-NEXT: Total Cycles: 404 +# CHECK-NEXT: Total uOps: 600 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.91 -# CHECK-NEXT: IPC: 1.91 -# CHECK-NEXT: Block RThroughput: 2.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 1.49 +# CHECK-NEXT: IPC: 0.99 +# CHECK-NEXT: Block RThroughput: 3.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -544,30 +642,32 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 1 1.00 * movaps %xmm0, (%rax) -# CHECK-NEXT: 1 6 0.50 * movaps (%rcx), %xmm1 -# CHECK-NEXT: 1 6 0.50 * movaps (%rdx), %xmm2 -# CHECK-NEXT: 1 1 1.00 * movaps %xmm3, (%rbx) +# CHECK-NEXT: 2 2 1.00 * movaps %xmm0, (%rax) +# CHECK-NEXT: 1 2 0.50 * movaps (%rcx), %xmm1 +# CHECK-NEXT: 1 2 0.50 * movaps (%rdx), %xmm2 +# CHECK-NEXT: 2 2 1.00 * movaps %xmm3, (%rbx) # CHECK: Dynamic Dispatch Stall Cycles: # CHECK-NEXT: RAT - Register unavailable: 0 -# CHECK-NEXT: RCU - Retire tokens unavailable: 0 -# CHECK-NEXT: SCHEDQ - Scheduler full: 147 (70.3%) +# CHECK-NEXT: RCU - Retire tokens unavailable: 156 (38.6%) +# CHECK-NEXT: SCHEDQ - Scheduler full: 0 # CHECK-NEXT: LQ - Load queue full: 0 # CHECK-NEXT: SQ - Store queue full: 0 # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK-NEXT: [# dispatched], [# cycles] -# CHECK-NEXT: 0, 35 (16.7%) -# CHECK-NEXT: 2, 148 (70.8%) -# CHECK-NEXT: 4, 26 (12.4%) +# CHECK-NEXT: 0, 126 (31.2%) +# CHECK-NEXT: 1, 78 (19.3%) +# CHECK-NEXT: 2, 78 (19.3%) +# CHECK-NEXT: 3, 122 (30.2%) # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: # CHECK-NEXT: [# issued], [# cycles] -# CHECK-NEXT: 0, 3 (1.4%) -# CHECK-NEXT: 1, 12 (5.7%) -# CHECK-NEXT: 2, 194 (92.8%) +# CHECK-NEXT: 0, 104 (25.7%) +# CHECK-NEXT: 1, 100 (24.8%) +# CHECK-NEXT: 2, 100 (24.8%) +# CHECK-NEXT: 3, 100 (24.8%) # CHECK: Scheduler's queue usage: # CHECK-NEXT: [1] Resource name. @@ -576,37 +676,54 @@ # CHECK-NEXT: [4] Total number of buffer entries. # CHECK: [1] [2] [3] [4] -# CHECK-NEXT: SBPortAny 45 54 54 +# CHECK-NEXT: BnFPU 20 24 36 +# CHECK-NEXT: BnInt 0 0 24 +# CHECK-NEXT: BnLoad 1 3 12 +# CHECK-NEXT: BnStore 20 24 32 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - - 2.00 - 2.00 2.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - - - - 1.00 2.00 1.00 0.99 1.00 2.01 - - - - 3.00 3.00 1.00 1.00 2.00 2.00 # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - 1.00 - - 1.00 movaps %xmm0, (%rax) -# CHECK-NEXT: - - - - - - 1.00 - movaps (%rcx), %xmm1 -# CHECK-NEXT: - - - - - - 0.94 0.06 movaps (%rdx), %xmm2 -# CHECK-NEXT: - - - - 1.00 - 0.06 0.94 movaps %xmm3, (%rbx) +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 1.20 0.80 - - - 2.00 movaps %xmm0, (%rax) +# CHECK-NEXT: - - - - - - - - - 1.00 0.98 0.01 0.01 - - - - 0.40 0.60 - 1.00 - - movaps (%rcx), %xmm1 +# CHECK-NEXT: - - - - - - - 1.00 - - 0.01 0.99 - - - - - 0.40 0.60 1.00 - - - movaps (%rdx), %xmm2 +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 1.00 1.00 - - 2.00 - movaps %xmm3, (%rbx) # CHECK: Timeline view: -# CHECK-NEXT: 0 -# CHECK-NEXT: Index 0123456789 +# CHECK-NEXT: Index 01234567 -# CHECK: [0,0] DeER . . movaps %xmm0, (%rax) -# CHECK-NEXT: [0,1] DeeeeeeER . movaps (%rcx), %xmm1 -# CHECK-NEXT: [0,2] D=eeeeeeER. movaps (%rdx), %xmm2 -# CHECK-NEXT: [0,3] D=======eER movaps %xmm3, (%rbx) +# CHECK: [0,0] DeeER. . movaps %xmm0, (%rax) +# CHECK-NEXT: [0,1] DeeER. . movaps (%rcx), %xmm1 +# CHECK-NEXT: [0,2] .DeeER . movaps (%rdx), %xmm2 +# CHECK-NEXT: [0,3] .D==eeER movaps %xmm3, (%rbx) # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -617,5 +734,5 @@ # CHECK: [0] [1] [2] [3] # CHECK-NEXT: 0. 1 1.0 1.0 0.0 movaps %xmm0, (%rax) # CHECK-NEXT: 1. 1 1.0 1.0 0.0 movaps (%rcx), %xmm1 -# CHECK-NEXT: 2. 1 2.0 2.0 0.0 movaps (%rdx), %xmm2 -# CHECK-NEXT: 3. 1 8.0 0.0 0.0 movaps %xmm3, (%rbx) +# CHECK-NEXT: 2. 1 1.0 1.0 0.0 movaps (%rdx), %xmm2 +# CHECK-NEXT: 3. 1 3.0 0.0 0.0 movaps %xmm3, (%rbx) diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/load-throughput.s b/llvm/test/tools/llvm-mca/X86/Barcelona/load-throughput.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/load-throughput.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/load-throughput.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -scheduler-stats -dispatch-stats -iterations=100 -timeline -timeline-max-iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -scheduler-stats -dispatch-stats -iterations=100 -timeline -timeline-max-iterations=1 < %s | FileCheck %s # LLVM-MCA-BEGIN movb (%rax), %spl @@ -47,12 +47,12 @@ # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 400 -# CHECK-NEXT: Total Cycles: 207 +# CHECK-NEXT: Total Cycles: 206 # CHECK-NEXT: Total uOps: 400 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.93 -# CHECK-NEXT: IPC: 1.93 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 1.94 +# CHECK-NEXT: IPC: 1.94 # CHECK-NEXT: Block RThroughput: 2.0 # CHECK: Instruction Info: @@ -64,29 +64,29 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 5 0.50 * movb (%rax), %spl -# CHECK-NEXT: 1 5 0.50 * movb (%rcx), %bpl -# CHECK-NEXT: 1 5 0.50 * movb (%rdx), %sil -# CHECK-NEXT: 1 5 0.50 * movb (%rbx), %dil +# CHECK-NEXT: 1 4 0.50 * movb (%rax), %spl +# CHECK-NEXT: 1 4 0.50 * movb (%rcx), %bpl +# CHECK-NEXT: 1 4 0.50 * movb (%rdx), %sil +# CHECK-NEXT: 1 4 0.50 * movb (%rbx), %dil # CHECK: Dynamic Dispatch Stall Cycles: # CHECK-NEXT: RAT - Register unavailable: 0 # CHECK-NEXT: RCU - Retire tokens unavailable: 0 -# CHECK-NEXT: SCHEDQ - Scheduler full: 147 (71.0%) -# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SCHEDQ - Scheduler full: 0 +# CHECK-NEXT: LQ - Load queue full: 194 (94.2%) # CHECK-NEXT: SQ - Store queue full: 0 # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK-NEXT: [# dispatched], [# cycles] -# CHECK-NEXT: 0, 33 (15.9%) -# CHECK-NEXT: 2, 148 (71.5%) -# CHECK-NEXT: 4, 26 (12.6%) +# CHECK-NEXT: 0, 8 (3.9%) +# CHECK-NEXT: 2, 194 (94.2%) +# CHECK-NEXT: 3, 4 (1.9%) # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: # CHECK-NEXT: [# issued], [# cycles] -# CHECK-NEXT: 0, 7 (3.4%) -# CHECK-NEXT: 2, 200 (96.6%) +# CHECK-NEXT: 0, 6 (2.9%) +# CHECK-NEXT: 2, 200 (97.1%) # CHECK: Scheduler's queue usage: # CHECK-NEXT: [1] Resource name. @@ -95,36 +95,54 @@ # CHECK-NEXT: [4] Total number of buffer entries. # CHECK: [1] [2] [3] [4] -# CHECK-NEXT: SBPortAny 45 54 54 +# CHECK-NEXT: BnFPU 0 0 36 +# CHECK-NEXT: BnInt 3 6 24 +# CHECK-NEXT: BnLoad 11 12 12 +# CHECK-NEXT: BnStore 0 0 32 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - - - - 2.00 2.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - 1.33 1.33 1.34 - - - - - - - - - - 1.33 1.33 1.34 2.00 2.00 2.00 2.00 - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - - - - 1.00 movb (%rax), %spl -# CHECK-NEXT: - - - - - - 1.00 - movb (%rcx), %bpl -# CHECK-NEXT: - - - - - - - 1.00 movb (%rdx), %sil -# CHECK-NEXT: - - - - - - 1.00 - movb (%rbx), %dil +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - 0.33 0.33 0.34 - - - - - - - - - - 0.33 0.33 0.34 - 1.00 - 1.00 - - movb (%rax), %spl +# CHECK-NEXT: - 0.33 0.34 0.33 - - - - - - - - - - 0.33 0.34 0.33 1.00 - 1.00 - - - movb (%rcx), %bpl +# CHECK-NEXT: - 0.34 0.33 0.33 - - - - - - - - - - 0.34 0.33 0.33 - 1.00 - 1.00 - - movb (%rdx), %sil +# CHECK-NEXT: - 0.33 0.33 0.34 - - - - - - - - - - 0.33 0.33 0.34 1.00 - 1.00 - - - movb (%rbx), %dil # CHECK: Timeline view: -# CHECK-NEXT: Index 012345678 +# CHECK-NEXT: Index 01234567 -# CHECK: [0,0] DeeeeeER. movb (%rax), %spl -# CHECK-NEXT: [0,1] DeeeeeER. movb (%rcx), %bpl -# CHECK-NEXT: [0,2] D=eeeeeER movb (%rdx), %sil -# CHECK-NEXT: [0,3] D=eeeeeER movb (%rbx), %dil +# CHECK: [0,0] DeeeeER. movb (%rax), %spl +# CHECK-NEXT: [0,1] DeeeeER. movb (%rcx), %bpl +# CHECK-NEXT: [0,2] D=eeeeER movb (%rdx), %sil +# CHECK-NEXT: [0,3] .DeeeeER movb (%rbx), %dil # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -136,18 +154,18 @@ # CHECK-NEXT: 0. 1 1.0 1.0 0.0 movb (%rax), %spl # CHECK-NEXT: 1. 1 1.0 1.0 0.0 movb (%rcx), %bpl # CHECK-NEXT: 2. 1 2.0 2.0 0.0 movb (%rdx), %sil -# CHECK-NEXT: 3. 1 2.0 2.0 0.0 movb (%rbx), %dil +# CHECK-NEXT: 3. 1 1.0 1.0 0.0 movb (%rbx), %dil # CHECK: [1] Code Region # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 400 -# CHECK-NEXT: Total Cycles: 207 +# CHECK-NEXT: Total Cycles: 206 # CHECK-NEXT: Total uOps: 400 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.93 -# CHECK-NEXT: IPC: 1.93 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 1.94 +# CHECK-NEXT: IPC: 1.94 # CHECK-NEXT: Block RThroughput: 2.0 # CHECK: Instruction Info: @@ -159,29 +177,29 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 5 0.50 * movw (%rax), %sp -# CHECK-NEXT: 1 5 0.50 * movw (%rcx), %bp -# CHECK-NEXT: 1 5 0.50 * movw (%rdx), %si -# CHECK-NEXT: 1 5 0.50 * movw (%rbx), %di +# CHECK-NEXT: 1 4 0.50 * movw (%rax), %sp +# CHECK-NEXT: 1 4 0.50 * movw (%rcx), %bp +# CHECK-NEXT: 1 4 0.50 * movw (%rdx), %si +# CHECK-NEXT: 1 4 0.50 * movw (%rbx), %di # CHECK: Dynamic Dispatch Stall Cycles: # CHECK-NEXT: RAT - Register unavailable: 0 # CHECK-NEXT: RCU - Retire tokens unavailable: 0 -# CHECK-NEXT: SCHEDQ - Scheduler full: 147 (71.0%) -# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SCHEDQ - Scheduler full: 0 +# CHECK-NEXT: LQ - Load queue full: 194 (94.2%) # CHECK-NEXT: SQ - Store queue full: 0 # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK-NEXT: [# dispatched], [# cycles] -# CHECK-NEXT: 0, 33 (15.9%) -# CHECK-NEXT: 2, 148 (71.5%) -# CHECK-NEXT: 4, 26 (12.6%) +# CHECK-NEXT: 0, 8 (3.9%) +# CHECK-NEXT: 2, 194 (94.2%) +# CHECK-NEXT: 3, 4 (1.9%) # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: # CHECK-NEXT: [# issued], [# cycles] -# CHECK-NEXT: 0, 7 (3.4%) -# CHECK-NEXT: 2, 200 (96.6%) +# CHECK-NEXT: 0, 6 (2.9%) +# CHECK-NEXT: 2, 200 (97.1%) # CHECK: Scheduler's queue usage: # CHECK-NEXT: [1] Resource name. @@ -190,36 +208,54 @@ # CHECK-NEXT: [4] Total number of buffer entries. # CHECK: [1] [2] [3] [4] -# CHECK-NEXT: SBPortAny 45 54 54 +# CHECK-NEXT: BnFPU 0 0 36 +# CHECK-NEXT: BnInt 3 6 24 +# CHECK-NEXT: BnLoad 11 12 12 +# CHECK-NEXT: BnStore 0 0 32 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - - - - 2.00 2.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - 1.33 1.33 1.34 - - - - - - - - - - 1.33 1.33 1.34 2.00 2.00 2.00 2.00 - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - - - - 1.00 movw (%rax), %sp -# CHECK-NEXT: - - - - - - 1.00 - movw (%rcx), %bp -# CHECK-NEXT: - - - - - - - 1.00 movw (%rdx), %si -# CHECK-NEXT: - - - - - - 1.00 - movw (%rbx), %di +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - 0.33 0.33 0.34 - - - - - - - - - - 0.33 0.33 0.34 - 1.00 - 1.00 - - movw (%rax), %sp +# CHECK-NEXT: - 0.33 0.34 0.33 - - - - - - - - - - 0.33 0.34 0.33 1.00 - 1.00 - - - movw (%rcx), %bp +# CHECK-NEXT: - 0.34 0.33 0.33 - - - - - - - - - - 0.34 0.33 0.33 - 1.00 - 1.00 - - movw (%rdx), %si +# CHECK-NEXT: - 0.33 0.33 0.34 - - - - - - - - - - 0.33 0.33 0.34 1.00 - 1.00 - - - movw (%rbx), %di # CHECK: Timeline view: -# CHECK-NEXT: Index 012345678 +# CHECK-NEXT: Index 01234567 -# CHECK: [0,0] DeeeeeER. movw (%rax), %sp -# CHECK-NEXT: [0,1] DeeeeeER. movw (%rcx), %bp -# CHECK-NEXT: [0,2] D=eeeeeER movw (%rdx), %si -# CHECK-NEXT: [0,3] D=eeeeeER movw (%rbx), %di +# CHECK: [0,0] DeeeeER. movw (%rax), %sp +# CHECK-NEXT: [0,1] DeeeeER. movw (%rcx), %bp +# CHECK-NEXT: [0,2] D=eeeeER movw (%rdx), %si +# CHECK-NEXT: [0,3] .DeeeeER movw (%rbx), %di # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -231,18 +267,18 @@ # CHECK-NEXT: 0. 1 1.0 1.0 0.0 movw (%rax), %sp # CHECK-NEXT: 1. 1 1.0 1.0 0.0 movw (%rcx), %bp # CHECK-NEXT: 2. 1 2.0 2.0 0.0 movw (%rdx), %si -# CHECK-NEXT: 3. 1 2.0 2.0 0.0 movw (%rbx), %di +# CHECK-NEXT: 3. 1 1.0 1.0 0.0 movw (%rbx), %di # CHECK: [2] Code Region # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 400 -# CHECK-NEXT: Total Cycles: 207 +# CHECK-NEXT: Total Cycles: 206 # CHECK-NEXT: Total uOps: 400 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.93 -# CHECK-NEXT: IPC: 1.93 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 1.94 +# CHECK-NEXT: IPC: 1.94 # CHECK-NEXT: Block RThroughput: 2.0 # CHECK: Instruction Info: @@ -254,29 +290,29 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 5 0.50 * movl (%rax), %esp -# CHECK-NEXT: 1 5 0.50 * movl (%rcx), %ebp -# CHECK-NEXT: 1 5 0.50 * movl (%rdx), %esi -# CHECK-NEXT: 1 5 0.50 * movl (%rbx), %edi +# CHECK-NEXT: 1 4 0.50 * movl (%rax), %esp +# CHECK-NEXT: 1 4 0.50 * movl (%rcx), %ebp +# CHECK-NEXT: 1 4 0.50 * movl (%rdx), %esi +# CHECK-NEXT: 1 4 0.50 * movl (%rbx), %edi # CHECK: Dynamic Dispatch Stall Cycles: # CHECK-NEXT: RAT - Register unavailable: 0 # CHECK-NEXT: RCU - Retire tokens unavailable: 0 -# CHECK-NEXT: SCHEDQ - Scheduler full: 147 (71.0%) -# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SCHEDQ - Scheduler full: 0 +# CHECK-NEXT: LQ - Load queue full: 194 (94.2%) # CHECK-NEXT: SQ - Store queue full: 0 # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK-NEXT: [# dispatched], [# cycles] -# CHECK-NEXT: 0, 33 (15.9%) -# CHECK-NEXT: 2, 148 (71.5%) -# CHECK-NEXT: 4, 26 (12.6%) +# CHECK-NEXT: 0, 8 (3.9%) +# CHECK-NEXT: 2, 194 (94.2%) +# CHECK-NEXT: 3, 4 (1.9%) # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: # CHECK-NEXT: [# issued], [# cycles] -# CHECK-NEXT: 0, 7 (3.4%) -# CHECK-NEXT: 2, 200 (96.6%) +# CHECK-NEXT: 0, 6 (2.9%) +# CHECK-NEXT: 2, 200 (97.1%) # CHECK: Scheduler's queue usage: # CHECK-NEXT: [1] Resource name. @@ -285,36 +321,54 @@ # CHECK-NEXT: [4] Total number of buffer entries. # CHECK: [1] [2] [3] [4] -# CHECK-NEXT: SBPortAny 45 54 54 +# CHECK-NEXT: BnFPU 0 0 36 +# CHECK-NEXT: BnInt 3 6 24 +# CHECK-NEXT: BnLoad 11 12 12 +# CHECK-NEXT: BnStore 0 0 32 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - - - - 2.00 2.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - 1.33 1.33 1.34 - - - - - - - - - - 1.33 1.33 1.34 2.00 2.00 2.00 2.00 - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - - - - 1.00 movl (%rax), %esp -# CHECK-NEXT: - - - - - - 1.00 - movl (%rcx), %ebp -# CHECK-NEXT: - - - - - - - 1.00 movl (%rdx), %esi -# CHECK-NEXT: - - - - - - 1.00 - movl (%rbx), %edi +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - 0.33 0.33 0.34 - - - - - - - - - - 0.33 0.33 0.34 - 1.00 - 1.00 - - movl (%rax), %esp +# CHECK-NEXT: - 0.33 0.34 0.33 - - - - - - - - - - 0.33 0.34 0.33 1.00 - 1.00 - - - movl (%rcx), %ebp +# CHECK-NEXT: - 0.34 0.33 0.33 - - - - - - - - - - 0.34 0.33 0.33 - 1.00 - 1.00 - - movl (%rdx), %esi +# CHECK-NEXT: - 0.33 0.33 0.34 - - - - - - - - - - 0.33 0.33 0.34 1.00 - 1.00 - - - movl (%rbx), %edi # CHECK: Timeline view: -# CHECK-NEXT: Index 012345678 +# CHECK-NEXT: Index 01234567 -# CHECK: [0,0] DeeeeeER. movl (%rax), %esp -# CHECK-NEXT: [0,1] DeeeeeER. movl (%rcx), %ebp -# CHECK-NEXT: [0,2] D=eeeeeER movl (%rdx), %esi -# CHECK-NEXT: [0,3] D=eeeeeER movl (%rbx), %edi +# CHECK: [0,0] DeeeeER. movl (%rax), %esp +# CHECK-NEXT: [0,1] DeeeeER. movl (%rcx), %ebp +# CHECK-NEXT: [0,2] D=eeeeER movl (%rdx), %esi +# CHECK-NEXT: [0,3] .DeeeeER movl (%rbx), %edi # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -326,18 +380,18 @@ # CHECK-NEXT: 0. 1 1.0 1.0 0.0 movl (%rax), %esp # CHECK-NEXT: 1. 1 1.0 1.0 0.0 movl (%rcx), %ebp # CHECK-NEXT: 2. 1 2.0 2.0 0.0 movl (%rdx), %esi -# CHECK-NEXT: 3. 1 2.0 2.0 0.0 movl (%rbx), %edi +# CHECK-NEXT: 3. 1 1.0 1.0 0.0 movl (%rbx), %edi # CHECK: [3] Code Region # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 400 -# CHECK-NEXT: Total Cycles: 207 +# CHECK-NEXT: Total Cycles: 206 # CHECK-NEXT: Total uOps: 400 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.93 -# CHECK-NEXT: IPC: 1.93 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 1.94 +# CHECK-NEXT: IPC: 1.94 # CHECK-NEXT: Block RThroughput: 2.0 # CHECK: Instruction Info: @@ -349,29 +403,29 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 5 0.50 * movq (%rax), %rsp -# CHECK-NEXT: 1 5 0.50 * movq (%rcx), %rbp -# CHECK-NEXT: 1 5 0.50 * movq (%rdx), %rsi -# CHECK-NEXT: 1 5 0.50 * movq (%rbx), %rdi +# CHECK-NEXT: 1 4 0.50 * movq (%rax), %rsp +# CHECK-NEXT: 1 4 0.50 * movq (%rcx), %rbp +# CHECK-NEXT: 1 4 0.50 * movq (%rdx), %rsi +# CHECK-NEXT: 1 4 0.50 * movq (%rbx), %rdi # CHECK: Dynamic Dispatch Stall Cycles: # CHECK-NEXT: RAT - Register unavailable: 0 # CHECK-NEXT: RCU - Retire tokens unavailable: 0 -# CHECK-NEXT: SCHEDQ - Scheduler full: 147 (71.0%) -# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SCHEDQ - Scheduler full: 0 +# CHECK-NEXT: LQ - Load queue full: 194 (94.2%) # CHECK-NEXT: SQ - Store queue full: 0 # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK-NEXT: [# dispatched], [# cycles] -# CHECK-NEXT: 0, 33 (15.9%) -# CHECK-NEXT: 2, 148 (71.5%) -# CHECK-NEXT: 4, 26 (12.6%) +# CHECK-NEXT: 0, 8 (3.9%) +# CHECK-NEXT: 2, 194 (94.2%) +# CHECK-NEXT: 3, 4 (1.9%) # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: # CHECK-NEXT: [# issued], [# cycles] -# CHECK-NEXT: 0, 7 (3.4%) -# CHECK-NEXT: 2, 200 (96.6%) +# CHECK-NEXT: 0, 6 (2.9%) +# CHECK-NEXT: 2, 200 (97.1%) # CHECK: Scheduler's queue usage: # CHECK-NEXT: [1] Resource name. @@ -380,36 +434,54 @@ # CHECK-NEXT: [4] Total number of buffer entries. # CHECK: [1] [2] [3] [4] -# CHECK-NEXT: SBPortAny 45 54 54 +# CHECK-NEXT: BnFPU 0 0 36 +# CHECK-NEXT: BnInt 3 6 24 +# CHECK-NEXT: BnLoad 11 12 12 +# CHECK-NEXT: BnStore 0 0 32 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - - - - 2.00 2.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - 1.33 1.33 1.34 - - - - - - - - - - 1.33 1.33 1.34 2.00 2.00 2.00 2.00 - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - - - - 1.00 movq (%rax), %rsp -# CHECK-NEXT: - - - - - - 1.00 - movq (%rcx), %rbp -# CHECK-NEXT: - - - - - - - 1.00 movq (%rdx), %rsi -# CHECK-NEXT: - - - - - - 1.00 - movq (%rbx), %rdi +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - 0.33 0.33 0.34 - - - - - - - - - - 0.33 0.33 0.34 - 1.00 - 1.00 - - movq (%rax), %rsp +# CHECK-NEXT: - 0.33 0.34 0.33 - - - - - - - - - - 0.33 0.34 0.33 1.00 - 1.00 - - - movq (%rcx), %rbp +# CHECK-NEXT: - 0.34 0.33 0.33 - - - - - - - - - - 0.34 0.33 0.33 - 1.00 - 1.00 - - movq (%rdx), %rsi +# CHECK-NEXT: - 0.33 0.33 0.34 - - - - - - - - - - 0.33 0.33 0.34 1.00 - 1.00 - - - movq (%rbx), %rdi # CHECK: Timeline view: -# CHECK-NEXT: Index 012345678 +# CHECK-NEXT: Index 01234567 -# CHECK: [0,0] DeeeeeER. movq (%rax), %rsp -# CHECK-NEXT: [0,1] DeeeeeER. movq (%rcx), %rbp -# CHECK-NEXT: [0,2] D=eeeeeER movq (%rdx), %rsi -# CHECK-NEXT: [0,3] D=eeeeeER movq (%rbx), %rdi +# CHECK: [0,0] DeeeeER. movq (%rax), %rsp +# CHECK-NEXT: [0,1] DeeeeER. movq (%rcx), %rbp +# CHECK-NEXT: [0,2] D=eeeeER movq (%rdx), %rsi +# CHECK-NEXT: [0,3] .DeeeeER movq (%rbx), %rdi # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -421,18 +493,18 @@ # CHECK-NEXT: 0. 1 1.0 1.0 0.0 movq (%rax), %rsp # CHECK-NEXT: 1. 1 1.0 1.0 0.0 movq (%rcx), %rbp # CHECK-NEXT: 2. 1 2.0 2.0 0.0 movq (%rdx), %rsi -# CHECK-NEXT: 3. 1 2.0 2.0 0.0 movq (%rbx), %rdi +# CHECK-NEXT: 3. 1 1.0 1.0 0.0 movq (%rbx), %rdi # CHECK: [4] Code Region # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 400 -# CHECK-NEXT: Total Cycles: 207 +# CHECK-NEXT: Total Cycles: 205 # CHECK-NEXT: Total uOps: 400 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.93 -# CHECK-NEXT: IPC: 1.93 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 1.95 +# CHECK-NEXT: IPC: 1.95 # CHECK-NEXT: Block RThroughput: 2.0 # CHECK: Instruction Info: @@ -444,29 +516,29 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 5 0.50 * movd (%rax), %mm0 -# CHECK-NEXT: 1 5 0.50 * movd (%rcx), %mm1 -# CHECK-NEXT: 1 5 0.50 * movd (%rdx), %mm2 -# CHECK-NEXT: 1 5 0.50 * movd (%rbx), %mm3 +# CHECK-NEXT: 1 3 0.50 * movd (%rax), %mm0 +# CHECK-NEXT: 1 3 0.50 * movd (%rcx), %mm1 +# CHECK-NEXT: 1 3 0.50 * movd (%rdx), %mm2 +# CHECK-NEXT: 1 3 0.50 * movd (%rbx), %mm3 # CHECK: Dynamic Dispatch Stall Cycles: # CHECK-NEXT: RAT - Register unavailable: 0 # CHECK-NEXT: RCU - Retire tokens unavailable: 0 -# CHECK-NEXT: SCHEDQ - Scheduler full: 147 (71.0%) -# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SCHEDQ - Scheduler full: 0 +# CHECK-NEXT: LQ - Load queue full: 193 (94.1%) # CHECK-NEXT: SQ - Store queue full: 0 # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK-NEXT: [# dispatched], [# cycles] -# CHECK-NEXT: 0, 33 (15.9%) -# CHECK-NEXT: 2, 148 (71.5%) -# CHECK-NEXT: 4, 26 (12.6%) +# CHECK-NEXT: 0, 7 (3.4%) +# CHECK-NEXT: 2, 194 (94.6%) +# CHECK-NEXT: 3, 4 (2.0%) # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: # CHECK-NEXT: [# issued], [# cycles] -# CHECK-NEXT: 0, 7 (3.4%) -# CHECK-NEXT: 2, 200 (96.6%) +# CHECK-NEXT: 0, 5 (2.4%) +# CHECK-NEXT: 2, 200 (97.6%) # CHECK: Scheduler's queue usage: # CHECK-NEXT: [1] Resource name. @@ -475,36 +547,54 @@ # CHECK-NEXT: [4] Total number of buffer entries. # CHECK: [1] [2] [3] [4] -# CHECK-NEXT: SBPortAny 45 54 54 +# CHECK-NEXT: BnFPU 5 6 36 +# CHECK-NEXT: BnInt 0 0 24 +# CHECK-NEXT: BnLoad 11 12 12 +# CHECK-NEXT: BnStore 0 0 32 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - - - - 2.00 2.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - - - - 1.33 1.33 1.34 1.33 1.33 1.34 - - - - 2.00 2.00 2.00 2.00 - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - - - - 1.00 movd (%rax), %mm0 -# CHECK-NEXT: - - - - - - 1.00 - movd (%rcx), %mm1 -# CHECK-NEXT: - - - - - - - 1.00 movd (%rdx), %mm2 -# CHECK-NEXT: - - - - - - 1.00 - movd (%rbx), %mm3 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - 0.33 0.33 0.34 0.33 0.33 0.34 - - - - - 1.00 - 1.00 - - movd (%rax), %mm0 +# CHECK-NEXT: - - - - - - - 0.33 0.34 0.33 0.33 0.34 0.33 - - - - 1.00 - 1.00 - - - movd (%rcx), %mm1 +# CHECK-NEXT: - - - - - - - 0.34 0.33 0.33 0.34 0.33 0.33 - - - - - 1.00 - 1.00 - - movd (%rdx), %mm2 +# CHECK-NEXT: - - - - - - - 0.33 0.33 0.34 0.33 0.33 0.34 - - - - 1.00 - 1.00 - - - movd (%rbx), %mm3 # CHECK: Timeline view: -# CHECK-NEXT: Index 012345678 +# CHECK-NEXT: Index 0123456 -# CHECK: [0,0] DeeeeeER. movd (%rax), %mm0 -# CHECK-NEXT: [0,1] DeeeeeER. movd (%rcx), %mm1 -# CHECK-NEXT: [0,2] D=eeeeeER movd (%rdx), %mm2 -# CHECK-NEXT: [0,3] D=eeeeeER movd (%rbx), %mm3 +# CHECK: [0,0] DeeeER. movd (%rax), %mm0 +# CHECK-NEXT: [0,1] DeeeER. movd (%rcx), %mm1 +# CHECK-NEXT: [0,2] D=eeeER movd (%rdx), %mm2 +# CHECK-NEXT: [0,3] .DeeeER movd (%rbx), %mm3 # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -516,18 +606,18 @@ # CHECK-NEXT: 0. 1 1.0 1.0 0.0 movd (%rax), %mm0 # CHECK-NEXT: 1. 1 1.0 1.0 0.0 movd (%rcx), %mm1 # CHECK-NEXT: 2. 1 2.0 2.0 0.0 movd (%rdx), %mm2 -# CHECK-NEXT: 3. 1 2.0 2.0 0.0 movd (%rbx), %mm3 +# CHECK-NEXT: 3. 1 1.0 1.0 0.0 movd (%rbx), %mm3 # CHECK: [5] Code Region # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 400 -# CHECK-NEXT: Total Cycles: 208 +# CHECK-NEXT: Total Cycles: 204 # CHECK-NEXT: Total uOps: 400 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.92 -# CHECK-NEXT: IPC: 1.92 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 1.96 +# CHECK-NEXT: IPC: 1.96 # CHECK-NEXT: Block RThroughput: 2.0 # CHECK: Instruction Info: @@ -539,29 +629,29 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 6 0.50 * movaps (%rax), %xmm0 -# CHECK-NEXT: 1 6 0.50 * movaps (%rcx), %xmm1 -# CHECK-NEXT: 1 6 0.50 * movaps (%rdx), %xmm2 -# CHECK-NEXT: 1 6 0.50 * movaps (%rbx), %xmm3 +# CHECK-NEXT: 1 2 0.50 * movaps (%rax), %xmm0 +# CHECK-NEXT: 1 2 0.50 * movaps (%rcx), %xmm1 +# CHECK-NEXT: 1 2 0.50 * movaps (%rdx), %xmm2 +# CHECK-NEXT: 1 2 0.50 * movaps (%rbx), %xmm3 # CHECK: Dynamic Dispatch Stall Cycles: # CHECK-NEXT: RAT - Register unavailable: 0 # CHECK-NEXT: RCU - Retire tokens unavailable: 0 -# CHECK-NEXT: SCHEDQ - Scheduler full: 147 (70.7%) -# CHECK-NEXT: LQ - Load queue full: 0 +# CHECK-NEXT: SCHEDQ - Scheduler full: 0 +# CHECK-NEXT: LQ - Load queue full: 190 (93.1%) # CHECK-NEXT: SQ - Store queue full: 0 # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK-NEXT: [# dispatched], [# cycles] -# CHECK-NEXT: 0, 34 (16.3%) -# CHECK-NEXT: 2, 148 (71.2%) -# CHECK-NEXT: 4, 26 (12.5%) +# CHECK-NEXT: 0, 7 (3.4%) +# CHECK-NEXT: 2, 191 (93.6%) +# CHECK-NEXT: 3, 6 (2.9%) # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: # CHECK-NEXT: [# issued], [# cycles] -# CHECK-NEXT: 0, 8 (3.8%) -# CHECK-NEXT: 2, 200 (96.2%) +# CHECK-NEXT: 0, 4 (2.0%) +# CHECK-NEXT: 2, 200 (98.0%) # CHECK: Scheduler's queue usage: # CHECK-NEXT: [1] Resource name. @@ -570,36 +660,54 @@ # CHECK-NEXT: [4] Total number of buffer entries. # CHECK: [1] [2] [3] [4] -# CHECK-NEXT: SBPortAny 45 54 54 +# CHECK-NEXT: BnFPU 7 8 36 +# CHECK-NEXT: BnInt 0 0 24 +# CHECK-NEXT: BnLoad 11 12 12 +# CHECK-NEXT: BnStore 0 0 32 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - - - - 2.00 2.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - - - - 1.33 1.33 1.34 1.33 1.33 1.34 - - - - 2.00 2.00 2.00 2.00 - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - - - - 1.00 movaps (%rax), %xmm0 -# CHECK-NEXT: - - - - - - 1.00 - movaps (%rcx), %xmm1 -# CHECK-NEXT: - - - - - - - 1.00 movaps (%rdx), %xmm2 -# CHECK-NEXT: - - - - - - 1.00 - movaps (%rbx), %xmm3 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - 0.33 0.33 0.34 0.33 0.33 0.34 - - - - - 1.00 - 1.00 - - movaps (%rax), %xmm0 +# CHECK-NEXT: - - - - - - - 0.33 0.34 0.33 0.33 0.34 0.33 - - - - 1.00 - 1.00 - - - movaps (%rcx), %xmm1 +# CHECK-NEXT: - - - - - - - 0.34 0.33 0.33 0.34 0.33 0.33 - - - - - 1.00 - 1.00 - - movaps (%rdx), %xmm2 +# CHECK-NEXT: - - - - - - - 0.33 0.33 0.34 0.33 0.33 0.34 - - - - 1.00 - 1.00 - - - movaps (%rbx), %xmm3 # CHECK: Timeline view: -# CHECK-NEXT: Index 0123456789 +# CHECK-NEXT: Index 012345 -# CHECK: [0,0] DeeeeeeER. movaps (%rax), %xmm0 -# CHECK-NEXT: [0,1] DeeeeeeER. movaps (%rcx), %xmm1 -# CHECK-NEXT: [0,2] D=eeeeeeER movaps (%rdx), %xmm2 -# CHECK-NEXT: [0,3] D=eeeeeeER movaps (%rbx), %xmm3 +# CHECK: [0,0] DeeER. movaps (%rax), %xmm0 +# CHECK-NEXT: [0,1] DeeER. movaps (%rcx), %xmm1 +# CHECK-NEXT: [0,2] D=eeER movaps (%rdx), %xmm2 +# CHECK-NEXT: [0,3] .DeeER movaps (%rbx), %xmm3 # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -611,4 +719,4 @@ # CHECK-NEXT: 0. 1 1.0 1.0 0.0 movaps (%rax), %xmm0 # CHECK-NEXT: 1. 1 1.0 1.0 0.0 movaps (%rcx), %xmm1 # CHECK-NEXT: 2. 1 2.0 2.0 0.0 movaps (%rdx), %xmm2 -# CHECK-NEXT: 3. 1 2.0 2.0 0.0 movaps (%rbx), %xmm3 +# CHECK-NEXT: 3. 1 1.0 1.0 0.0 movaps (%rbx), %xmm3 diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/one-idioms.s b/llvm/test/tools/llvm-mca/X86/Barcelona/one-idioms.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/one-idioms.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/one-idioms.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=1 -register-file-stats < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -timeline -timeline-max-iterations=1 -register-file-stats < %s | FileCheck %s # These are dependency-breaking one-idioms. # Much like zero-idioms, but they produce ones, and do consume resources. @@ -15,13 +15,13 @@ # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 700 -# CHECK-NEXT: Total Cycles: 903 +# CHECK-NEXT: Total Cycles: 1569 # CHECK-NEXT: Total uOps: 700 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 0.78 -# CHECK-NEXT: IPC: 0.78 -# CHECK-NEXT: Block RThroughput: 3.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.45 +# CHECK-NEXT: IPC: 0.45 +# CHECK-NEXT: Block RThroughput: 14.5 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -32,53 +32,78 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 3 1.00 pcmpeqb %mm2, %mm2 -# CHECK-NEXT: 1 3 1.00 pcmpeqd %mm2, %mm2 -# CHECK-NEXT: 1 3 1.00 pcmpeqw %mm2, %mm2 -# CHECK-NEXT: 1 1 0.50 pcmpeqb %xmm2, %xmm2 -# CHECK-NEXT: 1 1 0.50 pcmpeqd %xmm2, %xmm2 -# CHECK-NEXT: 1 1 0.50 pcmpeqq %xmm2, %xmm2 -# CHECK-NEXT: 1 1 0.50 pcmpeqw %xmm2, %xmm2 +# CHECK-NEXT: 1 2 1.50 pcmpeqb %mm2, %mm2 +# CHECK-NEXT: 1 2 1.50 pcmpeqd %mm2, %mm2 +# CHECK-NEXT: 1 2 1.50 pcmpeqw %mm2, %mm2 +# CHECK-NEXT: 1 3 2.50 pcmpeqb %xmm2, %xmm2 +# CHECK-NEXT: 1 3 2.50 pcmpeqd %xmm2, %xmm2 +# CHECK-NEXT: 1 3 2.50 pcmpeqq %xmm2, %xmm2 +# CHECK-NEXT: 1 3 2.50 pcmpeqw %xmm2, %xmm2 # CHECK: Register File statistics: # CHECK-NEXT: Total number of mappings created: 700 -# CHECK-NEXT: Max number of mappings used: 128 +# CHECK-NEXT: Max number of mappings used: 65 + +# CHECK: * Register File #1 -- BnFpuPRF: +# CHECK-NEXT: Number of physical registers: 120 +# CHECK-NEXT: Total number of mappings created: 700 +# CHECK-NEXT: Max number of mappings used: 65 + +# CHECK: * Register File #2 -- BnIntPRF: +# CHECK-NEXT: Number of physical registers: 40 +# CHECK-NEXT: Total number of mappings created: 0 +# CHECK-NEXT: Max number of mappings used: 0 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - 4.10 - 2.90 - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - - - - 13.50 - 15.50 3.50 3.50 - - - - - - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - 1.00 - - - - pcmpeqb %mm2, %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pcmpeqd %mm2, %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pcmpeqw %mm2, %mm2 -# CHECK-NEXT: - - - 0.10 - 0.90 - - pcmpeqb %xmm2, %xmm2 -# CHECK-NEXT: - - - 0.10 - 0.90 - - pcmpeqd %xmm2, %xmm2 -# CHECK-NEXT: - - - 0.11 - 0.89 - - pcmpeqq %xmm2, %xmm2 -# CHECK-NEXT: - - - 0.79 - 0.21 - - pcmpeqw %xmm2, %xmm2 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - 0.48 - 2.52 0.65 0.35 - - - - - - - - - - - pcmpeqb %mm2, %mm2 +# CHECK-NEXT: - - - - - - - 0.51 - 2.49 0.65 0.35 - - - - - - - - - - - pcmpeqd %mm2, %mm2 +# CHECK-NEXT: - - - - - - - 2.46 - 0.54 0.67 0.33 - - - - - - - - - - - pcmpeqw %mm2, %mm2 +# CHECK-NEXT: - - - - - - - 5.00 - - 0.34 0.66 - - - - - - - - - - - pcmpeqb %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - 3.25 - 1.75 0.42 0.58 - - - - - - - - - - - pcmpeqd %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - 1.75 - 3.25 0.34 0.66 - - - - - - - - - - - pcmpeqq %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - 0.05 - 4.95 0.43 0.57 - - - - - - - - - - - pcmpeqw %xmm2, %xmm2 # CHECK: Timeline view: -# CHECK-NEXT: 01 +# CHECK-NEXT: 0123456789 # CHECK-NEXT: Index 0123456789 -# CHECK: [0,0] DeeeER .. pcmpeqb %mm2, %mm2 -# CHECK-NEXT: [0,1] D===eeeER .. pcmpeqd %mm2, %mm2 -# CHECK-NEXT: [0,2] D======eeeER pcmpeqw %mm2, %mm2 -# CHECK-NEXT: [0,3] DeE--------R pcmpeqb %xmm2, %xmm2 -# CHECK-NEXT: [0,4] .DeE-------R pcmpeqd %xmm2, %xmm2 -# CHECK-NEXT: [0,5] .D=eE------R pcmpeqq %xmm2, %xmm2 -# CHECK-NEXT: [0,6] .D==eE-----R pcmpeqw %xmm2, %xmm2 +# CHECK: [0,0] DeeER. . . . pcmpeqb %mm2, %mm2 +# CHECK-NEXT: [0,1] D===eeER . . . pcmpeqd %mm2, %mm2 +# CHECK-NEXT: [0,2] D======eeER . . pcmpeqw %mm2, %mm2 +# CHECK-NEXT: [0,3] .DeeeE----R . . pcmpeqb %xmm2, %xmm2 +# CHECK-NEXT: [0,4] .D=====eeeER . . pcmpeqd %xmm2, %xmm2 +# CHECK-NEXT: [0,5] .D========eeeER. . pcmpeqq %xmm2, %xmm2 +# CHECK-NEXT: [0,6] . D============eeeER pcmpeqw %xmm2, %xmm2 # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -88,9 +113,9 @@ # CHECK: [0] [1] [2] [3] # CHECK-NEXT: 0. 1 1.0 1.0 0.0 pcmpeqb %mm2, %mm2 -# CHECK-NEXT: 1. 1 4.0 0.0 0.0 pcmpeqd %mm2, %mm2 -# CHECK-NEXT: 2. 1 7.0 0.0 0.0 pcmpeqw %mm2, %mm2 -# CHECK-NEXT: 3. 1 1.0 1.0 8.0 pcmpeqb %xmm2, %xmm2 -# CHECK-NEXT: 4. 1 1.0 0.0 7.0 pcmpeqd %xmm2, %xmm2 -# CHECK-NEXT: 5. 1 2.0 0.0 6.0 pcmpeqq %xmm2, %xmm2 -# CHECK-NEXT: 6. 1 3.0 0.0 5.0 pcmpeqw %xmm2, %xmm2 +# CHECK-NEXT: 1. 1 4.0 1.0 0.0 pcmpeqd %mm2, %mm2 +# CHECK-NEXT: 2. 1 7.0 1.0 0.0 pcmpeqw %mm2, %mm2 +# CHECK-NEXT: 3. 1 1.0 1.0 4.0 pcmpeqb %xmm2, %xmm2 +# CHECK-NEXT: 4. 1 6.0 2.0 0.0 pcmpeqd %xmm2, %xmm2 +# CHECK-NEXT: 5. 1 9.0 0.0 0.0 pcmpeqq %xmm2, %xmm2 +# CHECK-NEXT: 6. 1 13.0 2.0 0.0 pcmpeqw %xmm2, %xmm2 diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-2.s b/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-2.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-2.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-2.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s imul %rax, %rbx lzcnt %ax, %bx @@ -7,13 +7,13 @@ # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 3 -# CHECK-NEXT: Total Cycles: 8 +# CHECK-NEXT: Total Cycles: 10 # CHECK-NEXT: Total uOps: 3 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 0.38 -# CHECK-NEXT: IPC: 0.38 -# CHECK-NEXT: Block RThroughput: 2.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.30 +# CHECK-NEXT: IPC: 0.30 +# CHECK-NEXT: Block RThroughput: 3.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -24,16 +24,16 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 3 1.00 imulq %rax, %rbx -# CHECK-NEXT: 1 3 1.00 lzcntw %ax, %bx -# CHECK-NEXT: 1 1 0.33 addl %ecx, %ebx +# CHECK-NEXT: 1 4 2.00 imulq %rax, %rbx +# CHECK-NEXT: 1 3 3.00 lzcntw %ax, %bx +# CHECK-NEXT: 1 2 1.00 addl %ecx, %ebx # CHECK: Timeline view: -# CHECK-NEXT: Index 01234567 +# CHECK-NEXT: Index 0123456789 -# CHECK: [0,0] DeeeER . imulq %rax, %rbx -# CHECK-NEXT: [0,1] D=eeeER. lzcntw %ax, %bx -# CHECK-NEXT: [0,2] D====eER addl %ecx, %ebx +# CHECK: [0,0] DeeeeER . imulq %rax, %rbx +# CHECK-NEXT: [0,1] D==eeeER . lzcntw %ax, %bx +# CHECK-NEXT: [0,2] D=====eeER addl %ecx, %ebx # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -43,5 +43,5 @@ # CHECK: [0] [1] [2] [3] # CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulq %rax, %rbx -# CHECK-NEXT: 1. 1 2.0 2.0 0.0 lzcntw %ax, %bx -# CHECK-NEXT: 2. 1 5.0 0.0 0.0 addl %ecx, %ebx +# CHECK-NEXT: 1. 1 3.0 0.0 0.0 lzcntw %ax, %bx +# CHECK-NEXT: 2. 1 6.0 0.0 0.0 addl %ecx, %ebx diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-3.s b/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-3.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-3.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-3.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -iterations=1500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s # The ILP is limited by the false dependency on %dx. So, the mov cannot execute # in parallel with the add. @@ -10,13 +10,13 @@ # CHECK: Iterations: 1500 # CHECK-NEXT: Instructions: 4500 -# CHECK-NEXT: Total Cycles: 1504 +# CHECK-NEXT: Total Cycles: 7503 # CHECK-NEXT: Total uOps: 4500 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 2.99 -# CHECK-NEXT: IPC: 2.99 -# CHECK-NEXT: Block RThroughput: 1.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.60 +# CHECK-NEXT: IPC: 0.60 +# CHECK-NEXT: Block RThroughput: 3.3 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -27,42 +27,58 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 1 0.33 addw %cx, %dx -# CHECK-NEXT: 1 1 0.33 movw %ax, %dx -# CHECK-NEXT: 1 1 0.33 xorw %bx, %dx +# CHECK-NEXT: 1 2 1.00 addw %cx, %dx +# CHECK-NEXT: 1 1 1.33 movw %ax, %dx +# CHECK-NEXT: 1 2 1.00 xorw %bx, %dx # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - 3.00 4.00 3.00 - - - - - - - 1.00 1.00 1.00 - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - 0.67 - - 0.33 - - addw %cx, %dx -# CHECK-NEXT: - - - 0.67 - 0.33 - - movw %ax, %dx -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorw %bx, %dx +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - 3.00 - - - - - - - - - 1.00 - - - - - - addw %cx, %dx +# CHECK-NEXT: - - - - - 4.00 - - - - - - - - - 1.00 - - - - - - - movw %ax, %dx +# CHECK-NEXT: - - - - 3.00 - - - - - - - - - 1.00 - - - - - - - - xorw %bx, %dx # CHECK: Timeline view: -# CHECK-NEXT: Index 0123456 +# CHECK-NEXT: 01234567 +# CHECK-NEXT: Index 0123456789 -# CHECK: [0,0] DeER .. addw %cx, %dx -# CHECK-NEXT: [0,1] DeER .. movw %ax, %dx -# CHECK-NEXT: [0,2] D=eER.. xorw %bx, %dx -# CHECK-NEXT: [1,0] D==eER. addw %cx, %dx -# CHECK-NEXT: [1,1] .DeE-R. movw %ax, %dx -# CHECK-NEXT: [1,2] .D=eER. xorw %bx, %dx -# CHECK-NEXT: [2,0] .D==eER addw %cx, %dx -# CHECK-NEXT: [2,1] .DeE--R movw %ax, %dx -# CHECK-NEXT: [2,2] . DeE-R xorw %bx, %dx +# CHECK: [0,0] DeeER. . . . addw %cx, %dx +# CHECK-NEXT: [0,1] D==eER . . . movw %ax, %dx +# CHECK-NEXT: [0,2] D===eeER . . . xorw %bx, %dx +# CHECK-NEXT: [1,0] .D====eeER. . . addw %cx, %dx +# CHECK-NEXT: [1,1] .D======eER . . movw %ax, %dx +# CHECK-NEXT: [1,2] .D=======eeER . . xorw %bx, %dx +# CHECK-NEXT: [2,0] . D========eeER. . addw %cx, %dx +# CHECK-NEXT: [2,1] . D==========eER . movw %ax, %dx +# CHECK-NEXT: [2,2] . D===========eeER xorw %bx, %dx # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -71,6 +87,6 @@ # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] -# CHECK-NEXT: 0. 3 2.3 0.3 0.0 addw %cx, %dx -# CHECK-NEXT: 1. 3 1.0 1.0 1.0 movw %ax, %dx -# CHECK-NEXT: 2. 3 1.7 0.0 0.3 xorw %bx, %dx +# CHECK-NEXT: 0. 3 5.0 0.3 0.0 addw %cx, %dx +# CHECK-NEXT: 1. 3 7.0 0.0 0.0 movw %ax, %dx +# CHECK-NEXT: 2. 3 8.0 0.0 0.0 xorw %bx, %dx diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-4.s b/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-4.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-4.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-4.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -iterations=1500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s # The lzcnt cannot execute in parallel with the imul because there is a false # dependency on %bx. @@ -10,13 +10,13 @@ # CHECK: Iterations: 1500 # CHECK-NEXT: Instructions: 4500 -# CHECK-NEXT: Total Cycles: 3005 +# CHECK-NEXT: Total Cycles: 9003 # CHECK-NEXT: Total uOps: 4500 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.50 -# CHECK-NEXT: IPC: 1.50 -# CHECK-NEXT: Block RThroughput: 2.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.50 +# CHECK-NEXT: IPC: 0.50 +# CHECK-NEXT: Block RThroughput: 3.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -27,43 +27,58 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 3 1.00 imulw %ax, %bx -# CHECK-NEXT: 1 3 1.00 lzcntw %ax, %bx -# CHECK-NEXT: 1 1 0.33 addw %cx, %bx +# CHECK-NEXT: 1 3 3.00 imulw %ax, %bx +# CHECK-NEXT: 1 3 3.00 lzcntw %ax, %bx +# CHECK-NEXT: 1 2 1.00 addw %cx, %bx # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - 0.50 2.00 - 0.50 - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: 3.00 - - - 1.00 1.00 1.00 - - - - - - 3.00 1.00 1.00 1.00 - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - 1.00 - - - - imulw %ax, %bx -# CHECK-NEXT: - - - 1.00 - - - - lzcntw %ax, %bx -# CHECK-NEXT: - - 0.50 - - 0.50 - - addw %cx, %bx +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - - - - - - - 3.00 1.00 - - - - - - - - imulw %ax, %bx +# CHECK-NEXT: 3.00 - - - - - - - - - - - - - - - 1.00 - - - - - - lzcntw %ax, %bx +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - - 1.00 - - - - - - - addw %cx, %bx # CHECK: Timeline view: -# CHECK-NEXT: 01 -# CHECK-NEXT: Index 0123456789 +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 0 -# CHECK: [0,0] DeeeER .. imulw %ax, %bx -# CHECK-NEXT: [0,1] D=eeeER .. lzcntw %ax, %bx -# CHECK-NEXT: [0,2] D====eER .. addw %cx, %bx -# CHECK-NEXT: [1,0] D=====eeeER. imulw %ax, %bx -# CHECK-NEXT: [1,1] .D=eeeE---R. lzcntw %ax, %bx -# CHECK-NEXT: [1,2] .D====eE--R. addw %cx, %bx -# CHECK-NEXT: [2,0] .D=====eeeER imulw %ax, %bx -# CHECK-NEXT: [2,1] .D==eeeE---R lzcntw %ax, %bx -# CHECK-NEXT: [2,2] . D====eE--R addw %cx, %bx +# CHECK: [0,0] DeeeER . . . imulw %ax, %bx +# CHECK-NEXT: [0,1] D=eeeER . . . lzcntw %ax, %bx +# CHECK-NEXT: [0,2] D====eeER . . . addw %cx, %bx +# CHECK-NEXT: [1,0] .D=====eeeER . . imulw %ax, %bx +# CHECK-NEXT: [1,1] .D======eeeER . . lzcntw %ax, %bx +# CHECK-NEXT: [1,2] .D=========eeER. . addw %cx, %bx +# CHECK-NEXT: [2,0] . D==========eeeER . imulw %ax, %bx +# CHECK-NEXT: [2,1] . D===========eeeER . lzcntw %ax, %bx +# CHECK-NEXT: [2,2] . D==============eeER addw %cx, %bx # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -72,6 +87,6 @@ # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] -# CHECK-NEXT: 0. 3 4.3 0.3 0.0 imulw %ax, %bx -# CHECK-NEXT: 1. 3 2.3 2.3 2.0 lzcntw %ax, %bx -# CHECK-NEXT: 2. 3 5.0 0.0 1.3 addw %cx, %bx +# CHECK-NEXT: 0. 3 6.0 0.3 0.0 imulw %ax, %bx +# CHECK-NEXT: 1. 3 7.0 0.0 0.0 lzcntw %ax, %bx +# CHECK-NEXT: 2. 3 10.0 0.0 0.0 addw %cx, %bx diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-5.s b/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-5.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-5.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-5.s @@ -1,17 +1,17 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -iterations=1500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s lzcnt %ax, %bx ## partial register stall. # CHECK: Iterations: 1500 # CHECK-NEXT: Instructions: 1500 -# CHECK-NEXT: Total Cycles: 1505 +# CHECK-NEXT: Total Cycles: 4503 # CHECK-NEXT: Total uOps: 1500 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.00 -# CHECK-NEXT: IPC: 1.00 -# CHECK-NEXT: Block RThroughput: 1.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.33 +# CHECK-NEXT: IPC: 0.33 +# CHECK-NEXT: Block RThroughput: 3.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -22,32 +22,48 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 3 1.00 lzcntw %ax, %bx +# CHECK-NEXT: 1 3 3.00 lzcntw %ax, %bx # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - 1.00 - - - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: 3.00 - - - - - - - - - - - - - - - 1.00 - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - 1.00 - - - - lzcntw %ax, %bx +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: 3.00 - - - - - - - - - - - - - - - 1.00 - - - - - - lzcntw %ax, %bx # CHECK: Timeline view: -# CHECK-NEXT: Index 01234567 +# CHECK-NEXT: 01 +# CHECK-NEXT: Index 0123456789 -# CHECK: [0,0] DeeeER . lzcntw %ax, %bx -# CHECK-NEXT: [1,0] D=eeeER. lzcntw %ax, %bx -# CHECK-NEXT: [2,0] D==eeeER lzcntw %ax, %bx +# CHECK: [0,0] DeeeER .. lzcntw %ax, %bx +# CHECK-NEXT: [1,0] D===eeeER .. lzcntw %ax, %bx +# CHECK-NEXT: [2,0] D======eeeER lzcntw %ax, %bx # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -56,4 +72,4 @@ # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] -# CHECK-NEXT: 0. 3 2.0 2.0 0.0 lzcntw %ax, %bx +# CHECK-NEXT: 0. 3 4.0 1.7 0.0 lzcntw %ax, %bx diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-6.s b/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-6.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-6.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-6.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -iterations=1500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s # Each lzcnt has a false dependency on %ecx; the first lzcnt has to wait on the # imul. However, the folded load can start immediately. @@ -12,13 +12,13 @@ # CHECK: Iterations: 1500 # CHECK-NEXT: Instructions: 4500 -# CHECK-NEXT: Total Cycles: 4510 -# CHECK-NEXT: Total uOps: 7500 +# CHECK-NEXT: Total Cycles: 13503 +# CHECK-NEXT: Total uOps: 4500 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.66 -# CHECK-NEXT: IPC: 1.00 -# CHECK-NEXT: Block RThroughput: 3.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.33 +# CHECK-NEXT: IPC: 0.33 +# CHECK-NEXT: Block RThroughput: 6.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -29,43 +29,58 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 3 1.00 imull %edx, %ecx -# CHECK-NEXT: 2 8 1.00 * lzcntw (%rsp), %cx -# CHECK-NEXT: 2 8 1.00 * lzcntw 2(%rsp), %cx +# CHECK-NEXT: 1 3 2.00 imull %edx, %ecx +# CHECK-NEXT: 1 6 3.00 * lzcntw (%rsp), %cx +# CHECK-NEXT: 1 6 3.00 * lzcntw 2(%rsp), %cx # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - 3.00 - - 1.00 1.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: 6.00 - - 2.00 - - - - - - - - - 2.00 1.00 - 2.00 1.00 1.00 1.00 1.00 - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - 1.00 - - - - imull %edx, %ecx -# CHECK-NEXT: - - - 1.00 - - - 1.00 lzcntw (%rsp), %cx -# CHECK-NEXT: - - - 1.00 - - 1.00 - lzcntw 2(%rsp), %cx +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 1.00 - - - - - - - - imull %edx, %ecx +# CHECK-NEXT: 3.00 - - 1.00 - - - - - - - - - - - - 1.00 - 1.00 - 1.00 - - lzcntw (%rsp), %cx +# CHECK-NEXT: 3.00 - - 1.00 - - - - - - - - - - - - 1.00 1.00 - 1.00 - - - lzcntw 2(%rsp), %cx # CHECK: Timeline view: -# CHECK-NEXT: 012345678 -# CHECK-NEXT: Index 0123456789 +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 0123456789 -# CHECK: [0,0] DeeeER . . . imull %edx, %ecx -# CHECK-NEXT: [0,1] D=eeeeeeeeER . . lzcntw (%rsp), %cx -# CHECK-NEXT: [0,2] .D=eeeeeeeeER . . lzcntw 2(%rsp), %cx -# CHECK-NEXT: [1,0] .D=========eeeER . imull %edx, %ecx -# CHECK-NEXT: [1,1] . D=eeeeeeeeE--R . lzcntw (%rsp), %cx -# CHECK-NEXT: [1,2] . D==eeeeeeeeE-R . lzcntw 2(%rsp), %cx -# CHECK-NEXT: [2,0] . D==========eeeER imull %edx, %ecx -# CHECK-NEXT: [2,1] . D==eeeeeeeeE---R lzcntw (%rsp), %cx -# CHECK-NEXT: [2,2] . D==eeeeeeeeE--R lzcntw 2(%rsp), %cx +# CHECK: [0,0] DeeeER . . . . . imull %edx, %ecx +# CHECK-NEXT: [0,1] DeeeeeeER . . . . . lzcntw (%rsp), %cx +# CHECK-NEXT: [0,2] D===eeeeeeER . . . . lzcntw 2(%rsp), %cx +# CHECK-NEXT: [1,0] .D========eeeER. . . . imull %edx, %ecx +# CHECK-NEXT: [1,1] .D========eeeeeeER . . . lzcntw (%rsp), %cx +# CHECK-NEXT: [1,2] .D===========eeeeeeER . . lzcntw 2(%rsp), %cx +# CHECK-NEXT: [2,0] . D================eeeER . . imull %edx, %ecx +# CHECK-NEXT: [2,1] . D================eeeeeeER . lzcntw (%rsp), %cx +# CHECK-NEXT: [2,2] . D===================eeeeeeER lzcntw 2(%rsp), %cx # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -74,6 +89,6 @@ # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] -# CHECK-NEXT: 0. 3 7.3 0.3 0.0 imull %edx, %ecx -# CHECK-NEXT: 1. 3 2.3 2.3 1.7 lzcntw (%rsp), %cx -# CHECK-NEXT: 2. 3 2.7 2.7 1.0 lzcntw 2(%rsp), %cx +# CHECK-NEXT: 0. 3 9.0 0.3 0.0 imull %edx, %ecx +# CHECK-NEXT: 1. 3 9.0 0.0 0.0 lzcntw (%rsp), %cx +# CHECK-NEXT: 2. 3 12.0 2.0 0.0 lzcntw 2(%rsp), %cx diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-7.s b/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-7.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-7.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update-7.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=5 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -timeline -timeline-max-iterations=5 < %s | FileCheck %s sete %r9b movzbl %al, %eax @@ -9,13 +9,13 @@ # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 500 -# CHECK-NEXT: Total Cycles: 504 +# CHECK-NEXT: Total Cycles: 804 # CHECK-NEXT: Total uOps: 500 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 0.99 -# CHECK-NEXT: IPC: 0.99 -# CHECK-NEXT: Block RThroughput: 1.3 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.62 +# CHECK-NEXT: IPC: 0.62 +# CHECK-NEXT: Block RThroughput: 6.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -26,63 +26,78 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 1 0.50 sete %r9b -# CHECK-NEXT: 1 1 0.33 movzbl %al, %eax -# CHECK-NEXT: 1 1 0.50 shll $2, %eax -# CHECK-NEXT: 1 3 1.00 imull %ecx, %eax -# CHECK-NEXT: 1 1 0.33 cmpl $1025, %eax +# CHECK-NEXT: 1 1 2.00 sete %r9b +# CHECK-NEXT: 1 2 1.00 movzbl %al, %eax +# CHECK-NEXT: 1 2 2.00 shll $2, %eax +# CHECK-NEXT: 1 3 2.00 imull %ecx, %eax +# CHECK-NEXT: 1 2 1.00 cmpl $1025, %eax # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - 1.66 1.67 - 1.67 - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - 6.00 5.97 6.03 - - - - - - 2.00 1.67 1.66 1.67 - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - 0.66 - - 0.34 - - sete %r9b -# CHECK-NEXT: - - 0.33 0.34 - 0.33 - - movzbl %al, %eax -# CHECK-NEXT: - - 0.34 - - 0.66 - - shll $2, %eax -# CHECK-NEXT: - - - 1.00 - - - - imull %ecx, %eax -# CHECK-NEXT: - - 0.33 0.33 - 0.34 - - cmpl $1025, %eax +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - 1.98 1.98 2.04 - - - - - - - 0.33 0.33 0.34 - - - - - - sete %r9b +# CHECK-NEXT: - - - - 0.99 1.02 0.99 - - - - - - - - 0.67 0.33 - - - - - - movzbl %al, %eax +# CHECK-NEXT: - - - - 2.04 1.98 1.98 - - - - - - - 0.34 0.33 0.33 - - - - - - shll $2, %eax +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 1.00 - - - - - - - - imull %ecx, %eax +# CHECK-NEXT: - - - - 0.99 0.99 1.02 - - - - - - - - 0.33 0.67 - - - - - - cmpl $1025, %eax # CHECK: Timeline view: -# CHECK-NEXT: 0123456789 -# CHECK-NEXT: Index 0123456789 012345678 +# CHECK-NEXT: 0123456789 0123456789 +# CHECK-NEXT: Index 0123456789 0123456789 0123 -# CHECK: [0,0] DeER . . . . . . sete %r9b -# CHECK-NEXT: [0,1] DeER . . . . . . movzbl %al, %eax -# CHECK-NEXT: [0,2] D=eER. . . . . . shll $2, %eax -# CHECK-NEXT: [0,3] D==eeeER . . . . . imull %ecx, %eax -# CHECK-NEXT: [0,4] .D====eER . . . . . cmpl $1025, %eax -# CHECK-NEXT: [1,0] .D=====eER. . . . . sete %r9b -# CHECK-NEXT: [1,1] .D====eE-R. . . . . movzbl %al, %eax -# CHECK-NEXT: [1,2] .D=====eER. . . . . shll $2, %eax -# CHECK-NEXT: [1,3] . D=====eeeER . . . . imull %ecx, %eax -# CHECK-NEXT: [1,4] . D========eER . . . . cmpl $1025, %eax -# CHECK-NEXT: [2,0] . D=========eER. . . . sete %r9b -# CHECK-NEXT: [2,1] . D========eE-R. . . . movzbl %al, %eax -# CHECK-NEXT: [2,2] . D========eER. . . . shll $2, %eax -# CHECK-NEXT: [2,3] . D=========eeeER . . . imull %ecx, %eax -# CHECK-NEXT: [2,4] . D============eER . . . cmpl $1025, %eax -# CHECK-NEXT: [3,0] . D=============eER. . . sete %r9b -# CHECK-NEXT: [3,1] . D===========eE-R. . . movzbl %al, %eax -# CHECK-NEXT: [3,2] . D============eER. . . shll $2, %eax -# CHECK-NEXT: [3,3] . D=============eeeER . . imull %ecx, %eax -# CHECK-NEXT: [3,4] . D================eER . . cmpl $1025, %eax -# CHECK-NEXT: [4,0] . D================eER. . sete %r9b -# CHECK-NEXT: [4,1] . D===============eE-R. . movzbl %al, %eax -# CHECK-NEXT: [4,2] . D================eER. . shll $2, %eax -# CHECK-NEXT: [4,3] . D=================eeeER. imull %ecx, %eax -# CHECK-NEXT: [4,4] . .D===================eER cmpl $1025, %eax +# CHECK: [0,0] DeER . . . . . . . . . sete %r9b +# CHECK-NEXT: [0,1] DeeER. . . . . . . . . movzbl %al, %eax +# CHECK-NEXT: [0,2] D==eeER . . . . . . . . shll $2, %eax +# CHECK-NEXT: [0,3] .D===eeeER. . . . . . . . imull %ecx, %eax +# CHECK-NEXT: [0,4] .D======eeER . . . . . . . cmpl $1025, %eax +# CHECK-NEXT: [1,0] .D========eER . . . . . . . sete %r9b +# CHECK-NEXT: [1,1] . D=====eeE-R . . . . . . . movzbl %al, %eax +# CHECK-NEXT: [1,2] . D========eeER. . . . . . . shll $2, %eax +# CHECK-NEXT: [1,3] . D==========eeeER . . . . . . imull %ecx, %eax +# CHECK-NEXT: [1,4] . D============eeER. . . . . . cmpl $1025, %eax +# CHECK-NEXT: [2,0] . D==============eER . . . . . sete %r9b +# CHECK-NEXT: [2,1] . D============eeE-R . . . . . movzbl %al, %eax +# CHECK-NEXT: [2,2] . D==============eeER . . . . . shll $2, %eax +# CHECK-NEXT: [2,3] . D================eeeER . . . . imull %ecx, %eax +# CHECK-NEXT: [2,4] . D===================eeER . . . . cmpl $1025, %eax +# CHECK-NEXT: [3,0] . D====================eER . . . . sete %r9b +# CHECK-NEXT: [3,1] . D==================eeE-R . . . . movzbl %al, %eax +# CHECK-NEXT: [3,2] . D=====================eeER . . . shll $2, %eax +# CHECK-NEXT: [3,3] . .D======================eeeER . . . imull %ecx, %eax +# CHECK-NEXT: [3,4] . .D=========================eeER . . cmpl $1025, %eax +# CHECK-NEXT: [4,0] . .D===========================eER . . sete %r9b +# CHECK-NEXT: [4,1] . . D========================eeE-R . . movzbl %al, %eax +# CHECK-NEXT: [4,2] . . D===========================eeER . . shll $2, %eax +# CHECK-NEXT: [4,3] . . D=============================eeeER . imull %ecx, %eax +# CHECK-NEXT: [4,4] . . D===============================eeER cmpl $1025, %eax # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -91,8 +106,8 @@ # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] -# CHECK-NEXT: 0. 5 9.6 0.2 0.0 sete %r9b -# CHECK-NEXT: 1. 5 8.6 0.2 0.8 movzbl %al, %eax -# CHECK-NEXT: 2. 5 9.4 0.0 0.0 shll $2, %eax -# CHECK-NEXT: 3. 5 10.2 0.0 0.0 imull %ecx, %eax -# CHECK-NEXT: 4. 5 12.8 0.0 0.0 cmpl $1025, %eax +# CHECK-NEXT: 0. 5 14.8 0.2 0.0 sete %r9b +# CHECK-NEXT: 1. 5 12.8 0.2 0.8 movzbl %al, %eax +# CHECK-NEXT: 2. 5 15.4 0.8 0.0 shll $2, %eax +# CHECK-NEXT: 3. 5 17.0 0.0 0.0 imull %ecx, %eax +# CHECK-NEXT: 4. 5 19.6 0.0 0.0 cmpl $1025, %eax diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update.s b/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/partial-reg-update.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s imul %ax, %cx add %al, %cl @@ -7,13 +7,13 @@ # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 3 -# CHECK-NEXT: Total Cycles: 8 +# CHECK-NEXT: Total Cycles: 10 # CHECK-NEXT: Total uOps: 3 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 0.38 -# CHECK-NEXT: IPC: 0.38 -# CHECK-NEXT: Block RThroughput: 1.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.30 +# CHECK-NEXT: IPC: 0.30 +# CHECK-NEXT: Block RThroughput: 3.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -24,16 +24,16 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 3 1.00 imulw %ax, %cx -# CHECK-NEXT: 1 1 0.33 addb %al, %cl -# CHECK-NEXT: 1 1 0.33 addl %ecx, %ebx +# CHECK-NEXT: 1 3 3.00 imulw %ax, %cx +# CHECK-NEXT: 1 2 1.00 addb %al, %cl +# CHECK-NEXT: 1 2 1.00 addl %ecx, %ebx # CHECK: Timeline view: -# CHECK-NEXT: Index 01234567 +# CHECK-NEXT: Index 0123456789 -# CHECK: [0,0] DeeeER . imulw %ax, %cx -# CHECK-NEXT: [0,1] D===eER. addb %al, %cl -# CHECK-NEXT: [0,2] D====eER addl %ecx, %ebx +# CHECK: [0,0] DeeeER . imulw %ax, %cx +# CHECK-NEXT: [0,1] D===eeER . addb %al, %cl +# CHECK-NEXT: [0,2] D=====eeER addl %ecx, %ebx # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -44,4 +44,4 @@ # CHECK: [0] [1] [2] [3] # CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulw %ax, %cx # CHECK-NEXT: 1. 1 4.0 0.0 0.0 addb %al, %cl -# CHECK-NEXT: 2. 1 5.0 0.0 0.0 addl %ecx, %ebx +# CHECK-NEXT: 2. 1 6.0 0.0 0.0 addl %ecx, %ebx diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/rcu-statistics.s b/llvm/test/tools/llvm-mca/X86/Barcelona/rcu-statistics.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/rcu-statistics.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/rcu-statistics.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -resource-pressure=false -retire-stats -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -resource-pressure=false -retire-stats -iterations=1 < %s | FileCheck %s sqrtps %xmm0, %xmm1 addps %xmm0, %xmm1 @@ -20,13 +20,13 @@ # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 16 -# CHECK-NEXT: Total Cycles: 62 +# CHECK-NEXT: Total Cycles: 84 # CHECK-NEXT: Total uOps: 16 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 0.26 -# CHECK-NEXT: IPC: 0.26 -# CHECK-NEXT: Block RThroughput: 15.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.19 +# CHECK-NEXT: IPC: 0.19 +# CHECK-NEXT: Block RThroughput: 30.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -37,28 +37,28 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 14 14.00 sqrtps %xmm0, %xmm1 -# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 -# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 -# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 -# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 -# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 -# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 -# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 -# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 -# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 -# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 -# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 -# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 -# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 -# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 -# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 21 18.00 sqrtps %xmm0, %xmm1 +# CHECK-NEXT: 1 4 2.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 4 2.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 4 2.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 4 2.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 4 2.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 4 2.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 4 2.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 4 2.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 4 2.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 4 2.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 4 2.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 4 2.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 4 2.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 4 2.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 4 2.00 addps %xmm0, %xmm1 # CHECK: Retire Control Unit - number of cycles where we saw N instructions retired: # CHECK-NEXT: [# retired], [# cycles] -# CHECK-NEXT: 0, 46 (74.2%) -# CHECK-NEXT: 1, 16 (25.8%) +# CHECK-NEXT: 0, 68 (81.0%) +# CHECK-NEXT: 1, 16 (19.0%) -# CHECK: Total ROB Entries: 168 -# CHECK-NEXT: Max Used ROB Entries: 16 ( 9.5% ) -# CHECK-NEXT: Average Used ROB Entries per cy: 9 ( 5.4% ) +# CHECK: Total ROB Entries: 72 +# CHECK-NEXT: Max Used ROB Entries: 16 ( 22.2% ) +# CHECK-NEXT: Average Used ROB Entries per cy: 9 ( 12.5% ) diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/read-advance-1.s b/llvm/test/tools/llvm-mca/X86/Barcelona/read-advance-1.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/read-advance-1.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/read-advance-1.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s # The vmul can start executing 2cy in advance. That is beause the first use # operand (i.e. %xmm1) is a ReadAfterLd. That means, the memory operand is @@ -10,13 +10,13 @@ # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 2 -# CHECK-NEXT: Total Cycles: 14 -# CHECK-NEXT: Total uOps: 3 +# CHECK-NEXT: Total Cycles: 11 +# CHECK-NEXT: Total uOps: 2 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 0.21 -# CHECK-NEXT: IPC: 0.14 -# CHECK-NEXT: Block RThroughput: 1.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.18 +# CHECK-NEXT: IPC: 0.18 +# CHECK-NEXT: Block RThroughput: 4.5 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -27,15 +27,15 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm1 -# CHECK-NEXT: 2 11 1.00 * mulps (%rdi), %xmm1 +# CHECK-NEXT: 1 4 2.00 addps %xmm0, %xmm1 +# CHECK-NEXT: 1 6 2.50 * mulps (%rdi), %xmm1 # CHECK: Timeline view: -# CHECK-NEXT: 0123 +# CHECK-NEXT: 0 # CHECK-NEXT: Index 0123456789 -# CHECK: [0,0] DeeeER . . addps %xmm0, %xmm1 -# CHECK-NEXT: [0,1] DeeeeeeeeeeeER mulps (%rdi), %xmm1 +# CHECK: [0,0] DeeeeER . addps %xmm0, %xmm1 +# CHECK-NEXT: [0,1] D==eeeeeeER mulps (%rdi), %xmm1 # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -45,4 +45,4 @@ # CHECK: [0] [1] [2] [3] # CHECK-NEXT: 0. 1 1.0 1.0 0.0 addps %xmm0, %xmm1 -# CHECK-NEXT: 1. 1 1.0 0.0 0.0 mulps (%rdi), %xmm1 +# CHECK-NEXT: 1. 1 3.0 0.0 0.0 mulps (%rdi), %xmm1 diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/read-advance-2.s b/llvm/test/tools/llvm-mca/X86/Barcelona/read-advance-2.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/read-advance-2.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/read-advance-2.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -resource-pressure=0 -timeline < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -iterations=1 -resource-pressure=0 -timeline < %s | FileCheck %s imull %esi imull (%rdi) @@ -9,13 +9,13 @@ # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 2 -# CHECK-NEXT: Total Cycles: 13 -# CHECK-NEXT: Total uOps: 7 +# CHECK-NEXT: Total Cycles: 12 +# CHECK-NEXT: Total uOps: 4 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 0.54 -# CHECK-NEXT: IPC: 0.15 -# CHECK-NEXT: Block RThroughput: 2.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.33 +# CHECK-NEXT: IPC: 0.17 +# CHECK-NEXT: Block RThroughput: 6.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -26,15 +26,15 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 3 4 1.00 imull %esi -# CHECK-NEXT: 4 9 1.00 * imull (%rdi) +# CHECK-NEXT: 2 3 3.00 imull %esi +# CHECK-NEXT: 2 6 3.00 * imull (%rdi) # CHECK: Timeline view: -# CHECK-NEXT: 012 +# CHECK-NEXT: 01 # CHECK-NEXT: Index 0123456789 -# CHECK: [0,0] DeeeeER . . imull %esi -# CHECK-NEXT: [0,1] .DeeeeeeeeeER imull (%rdi) +# CHECK: [0,0] DeeeER .. imull %esi +# CHECK-NEXT: [0,1] .D==eeeeeeER imull (%rdi) # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -44,4 +44,4 @@ # CHECK: [0] [1] [2] [3] # CHECK-NEXT: 0. 1 1.0 1.0 0.0 imull %esi -# CHECK-NEXT: 1. 1 1.0 1.0 0.0 imull (%rdi) +# CHECK-NEXT: 1. 1 3.0 3.0 0.0 imull (%rdi) diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/read-advance-3.s b/llvm/test/tools/llvm-mca/X86/Barcelona/read-advance-3.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/read-advance-3.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/read-advance-3.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -resource-pressure=0 -timeline -dispatch=3 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -iterations=1 -resource-pressure=0 -timeline -dispatch=3 < %s | FileCheck %s add %rdi, %rsi add (%rsp), %rsi @@ -7,13 +7,13 @@ # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 3 -# CHECK-NEXT: Total Cycles: 9 -# CHECK-NEXT: Total uOps: 4 +# CHECK-NEXT: Total Cycles: 8 +# CHECK-NEXT: Total uOps: 3 # CHECK: Dispatch Width: 3 -# CHECK-NEXT: uOps Per Cycle: 0.44 -# CHECK-NEXT: IPC: 0.33 -# CHECK-NEXT: Block RThroughput: 1.3 +# CHECK-NEXT: uOps Per Cycle: 0.38 +# CHECK-NEXT: IPC: 0.38 +# CHECK-NEXT: Block RThroughput: 3.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -24,16 +24,16 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 1 0.33 addq %rdi, %rsi -# CHECK-NEXT: 2 6 0.50 * addq (%rsp), %rsi -# CHECK-NEXT: 1 1 0.33 addq %rdx, %r8 +# CHECK-NEXT: 1 2 1.00 addq %rdi, %rsi +# CHECK-NEXT: 1 5 1.00 * addq (%rsp), %rsi +# CHECK-NEXT: 1 2 1.00 addq %rdx, %r8 # CHECK: Timeline view: -# CHECK-NEXT: Index 012345678 +# CHECK-NEXT: Index 01234567 -# CHECK: [0,0] DeER . . addq %rdi, %rsi -# CHECK-NEXT: [0,1] DeeeeeeER addq (%rsp), %rsi -# CHECK-NEXT: [0,2] .DeE----R addq %rdx, %r8 +# CHECK: [0,0] DeeER. . addq %rdi, %rsi +# CHECK-NEXT: [0,1] DeeeeeER addq (%rsp), %rsi +# CHECK-NEXT: [0,2] DeeE---R addq %rdx, %r8 # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -44,4 +44,4 @@ # CHECK: [0] [1] [2] [3] # CHECK-NEXT: 0. 1 1.0 1.0 0.0 addq %rdi, %rsi # CHECK-NEXT: 1. 1 1.0 0.0 0.0 addq (%rsp), %rsi -# CHECK-NEXT: 2. 1 1.0 1.0 4.0 addq %rdx, %r8 +# CHECK-NEXT: 2. 1 1.0 1.0 3.0 addq %rdx, %r8 diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-1.s b/llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-1.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-1.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-1.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=3 -timeline -register-file-stats < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -iterations=3 -timeline -register-file-stats < %s | FileCheck %s # The register move from XMM0 to XMM1 can be eliminated at register renaming # stage. So, it should not consume pipeline resources. @@ -10,13 +10,13 @@ # CHECK: Iterations: 3 # CHECK-NEXT: Instructions: 9 -# CHECK-NEXT: Total Cycles: 9 +# CHECK-NEXT: Total Cycles: 22 # CHECK-NEXT: Total uOps: 9 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.00 -# CHECK-NEXT: IPC: 1.00 -# CHECK-NEXT: Block RThroughput: 1.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.41 +# CHECK-NEXT: IPC: 0.41 +# CHECK-NEXT: Block RThroughput: 4.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -27,46 +27,72 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 0 0.25 xorps %xmm0, %xmm0 -# CHECK-NEXT: 1 1 1.00 movaps %xmm0, %xmm1 -# CHECK-NEXT: 1 3 1.00 addps %xmm1, %xmm1 +# CHECK-NEXT: 1 2 2.00 xorps %xmm0, %xmm0 +# CHECK-NEXT: 1 3 1.33 movaps %xmm0, %xmm1 +# CHECK-NEXT: 1 4 2.00 addps %xmm1, %xmm1 # CHECK: Register File statistics: # CHECK-NEXT: Total number of mappings created: 9 -# CHECK-NEXT: Max number of mappings used: 8 +# CHECK-NEXT: Max number of mappings used: 9 + +# CHECK: * Register File #1 -- BnFpuPRF: +# CHECK-NEXT: Number of physical registers: 120 +# CHECK-NEXT: Total number of mappings created: 9 +# CHECK-NEXT: Max number of mappings used: 9 + +# CHECK: * Register File #2 -- BnIntPRF: +# CHECK-NEXT: Number of physical registers: 40 +# CHECK-NEXT: Total number of mappings created: 0 +# CHECK-NEXT: Max number of mappings used: 0 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - 1.00 - 1.00 - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - - - - 4.00 2.67 5.33 1.00 1.00 1.00 - - - - - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - - - - - xorps %xmm0, %xmm0 -# CHECK-NEXT: - - - - - 1.00 - - movaps %xmm0, %xmm1 -# CHECK-NEXT: - - - 1.00 - - - - addps %xmm1, %xmm1 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - 2.67 - 1.33 0.33 0.67 - - - - - - - - - - - xorps %xmm0, %xmm0 +# CHECK-NEXT: - - - - - - - - 2.67 1.33 - - 1.00 - - - - - - - - - - movaps %xmm0, %xmm1 +# CHECK-NEXT: - - - - - - - 1.33 - 2.67 0.67 0.33 - - - - - - - - - - - addps %xmm1, %xmm1 # CHECK: Timeline view: -# CHECK-NEXT: Index 012345678 +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 01 -# CHECK: [0,0] DR . . xorps %xmm0, %xmm0 -# CHECK-NEXT: [0,1] DeER . . movaps %xmm0, %xmm1 -# CHECK-NEXT: [0,2] D=eeeER . addps %xmm1, %xmm1 -# CHECK-NEXT: [1,0] D-----R . xorps %xmm0, %xmm0 -# CHECK-NEXT: [1,1] .DeE--R . movaps %xmm0, %xmm1 -# CHECK-NEXT: [1,2] .D=eeeER. addps %xmm1, %xmm1 -# CHECK-NEXT: [2,0] .D-----R. xorps %xmm0, %xmm0 -# CHECK-NEXT: [2,1] .D=eE--R. movaps %xmm0, %xmm1 -# CHECK-NEXT: [2,2] . D=eeeER addps %xmm1, %xmm1 +# CHECK: [0,0] DeeER. . . .. xorps %xmm0, %xmm0 +# CHECK-NEXT: [0,1] D==eeeER . . .. movaps %xmm0, %xmm1 +# CHECK-NEXT: [0,2] D======eeeeER . .. addps %xmm1, %xmm1 +# CHECK-NEXT: [1,0] .D=eeE------R . .. xorps %xmm0, %xmm0 +# CHECK-NEXT: [1,1] .D===eeeE---R . .. movaps %xmm0, %xmm1 +# CHECK-NEXT: [1,2] .D=======eeeeER. .. addps %xmm1, %xmm1 +# CHECK-NEXT: [2,0] . D========eeER. .. xorps %xmm0, %xmm0 +# CHECK-NEXT: [2,1] . D==========eeeER .. movaps %xmm0, %xmm1 +# CHECK-NEXT: [2,2] . D=============eeeeER addps %xmm1, %xmm1 # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -75,6 +101,6 @@ # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] -# CHECK-NEXT: 0. 3 0.0 0.0 3.3 xorps %xmm0, %xmm0 -# CHECK-NEXT: 1. 3 1.3 1.3 1.3 movaps %xmm0, %xmm1 -# CHECK-NEXT: 2. 3 2.0 0.0 0.0 addps %xmm1, %xmm1 +# CHECK-NEXT: 0. 3 4.0 2.3 2.0 xorps %xmm0, %xmm0 +# CHECK-NEXT: 1. 3 6.0 0.0 1.0 movaps %xmm0, %xmm1 +# CHECK-NEXT: 2. 3 9.7 0.7 0.0 addps %xmm1, %xmm1 diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-2.s b/llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-2.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-2.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-2.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=3 -timeline -register-file-stats < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -iterations=3 -timeline -register-file-stats < %s | FileCheck %s pxor %mm0, %mm0 movq %mm0, %mm1 @@ -14,13 +14,13 @@ # CHECK: Iterations: 3 # CHECK-NEXT: Instructions: 27 -# CHECK-NEXT: Total Cycles: 22 +# CHECK-NEXT: Total Cycles: 65 # CHECK-NEXT: Total uOps: 27 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.23 -# CHECK-NEXT: IPC: 1.23 -# CHECK-NEXT: Block RThroughput: 4.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.42 +# CHECK-NEXT: IPC: 0.42 +# CHECK-NEXT: Block RThroughput: 9.3 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -31,77 +31,102 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 1 0.33 pxor %mm0, %mm0 -# CHECK-NEXT: 1 1 0.50 movq %mm0, %mm1 -# CHECK-NEXT: 1 0 0.25 xorps %xmm0, %xmm0 -# CHECK-NEXT: 1 1 1.00 movaps %xmm0, %xmm1 -# CHECK-NEXT: 1 1 1.00 movups %xmm1, %xmm2 -# CHECK-NEXT: 1 1 1.00 movapd %xmm2, %xmm3 -# CHECK-NEXT: 1 1 1.00 movupd %xmm3, %xmm4 -# CHECK-NEXT: 1 1 0.33 movdqa %xmm4, %xmm5 -# CHECK-NEXT: 1 1 0.33 movdqu %xmm5, %xmm0 +# CHECK-NEXT: 1 2 1.50 pxor %mm0, %mm0 +# CHECK-NEXT: 1 2 2.00 movq %mm0, %mm1 +# CHECK-NEXT: 1 2 2.00 xorps %xmm0, %xmm0 +# CHECK-NEXT: 1 3 1.33 movaps %xmm0, %xmm1 +# CHECK-NEXT: 1 3 1.33 movups %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.33 movapd %xmm2, %xmm3 +# CHECK-NEXT: 1 3 1.33 movupd %xmm3, %xmm4 +# CHECK-NEXT: 1 3 2.00 movdqa %xmm4, %xmm5 +# CHECK-NEXT: 1 3 2.00 movdqu %xmm5, %xmm0 # CHECK: Register File statistics: # CHECK-NEXT: Total number of mappings created: 27 -# CHECK-NEXT: Max number of mappings used: 21 +# CHECK-NEXT: Max number of mappings used: 23 + +# CHECK: * Register File #1 -- BnFpuPRF: +# CHECK-NEXT: Number of physical registers: 120 +# CHECK-NEXT: Total number of mappings created: 27 +# CHECK-NEXT: Max number of mappings used: 23 + +# CHECK: * Register File #2 -- BnIntPRF: +# CHECK-NEXT: Number of physical registers: 40 +# CHECK-NEXT: Total number of mappings created: 0 +# CHECK-NEXT: Max number of mappings used: 0 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - 1.67 1.67 - 4.67 - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - - - - 12.00 14.00 13.00 2.67 2.67 2.67 - - - - - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - 0.67 - 0.33 - - pxor %mm0, %mm0 -# CHECK-NEXT: - - 1.00 - - - - - movq %mm0, %mm1 -# CHECK-NEXT: - - - - - - - - xorps %xmm0, %xmm0 -# CHECK-NEXT: - - - - - 1.00 - - movaps %xmm0, %xmm1 -# CHECK-NEXT: - - - - - 1.00 - - movups %xmm1, %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - movapd %xmm2, %xmm3 -# CHECK-NEXT: - - - - - 1.00 - - movupd %xmm3, %xmm4 -# CHECK-NEXT: - - - 1.00 - - - - movdqa %xmm4, %xmm5 -# CHECK-NEXT: - - 0.67 - - 0.33 - - movdqu %xmm5, %xmm0 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - 2.00 - 1.00 0.33 0.67 - - - - - - - - - - - pxor %mm0, %mm0 +# CHECK-NEXT: - - - - - - - 1.33 - 2.67 - - - - - - - - - - - - - movq %mm0, %mm1 +# CHECK-NEXT: - - - - - - - 4.00 - - 0.67 0.33 - - - - - - - - - - - xorps %xmm0, %xmm0 +# CHECK-NEXT: - - - - - - - - 2.67 1.33 0.33 - 0.67 - - - - - - - - - - movaps %xmm0, %xmm1 +# CHECK-NEXT: - - - - - - - - 2.67 1.33 - 0.33 0.67 - - - - - - - - - - movups %xmm1, %xmm2 +# CHECK-NEXT: - - - - - - - 1.33 2.67 - 0.33 0.33 0.33 - - - - - - - - - - movapd %xmm2, %xmm3 +# CHECK-NEXT: - - - - - - - 1.33 - 2.67 0.33 0.33 0.33 - - - - - - - - - - movupd %xmm3, %xmm4 +# CHECK-NEXT: - - - - - - - - 4.00 2.00 0.33 0.33 0.33 - - - - - - - - - - movdqa %xmm4, %xmm5 +# CHECK-NEXT: - - - - - - - 2.00 2.00 2.00 0.33 0.33 0.33 - - - - - - - - - - movdqu %xmm5, %xmm0 # CHECK: Timeline view: -# CHECK-NEXT: 0123456789 -# CHECK-NEXT: Index 0123456789 01 +# CHECK-NEXT: 0123456789 0123456789 0123456789 +# CHECK-NEXT: Index 0123456789 0123456789 0123456789 01234 -# CHECK: [0,0] DeER . . . .. pxor %mm0, %mm0 -# CHECK-NEXT: [0,1] D=eER. . . .. movq %mm0, %mm1 -# CHECK-NEXT: [0,2] D---R. . . .. xorps %xmm0, %xmm0 -# CHECK-NEXT: [0,3] D=eER. . . .. movaps %xmm0, %xmm1 -# CHECK-NEXT: [0,4] .D=eER . . .. movups %xmm1, %xmm2 -# CHECK-NEXT: [0,5] .D==eER . . .. movapd %xmm2, %xmm3 -# CHECK-NEXT: [0,6] .D===eER . . .. movupd %xmm3, %xmm4 -# CHECK-NEXT: [0,7] .D====eER . . .. movdqa %xmm4, %xmm5 -# CHECK-NEXT: [0,8] . D====eER. . .. movdqu %xmm5, %xmm0 -# CHECK-NEXT: [1,0] . DeE----R. . .. pxor %mm0, %mm0 -# CHECK-NEXT: [1,1] . D=eE---R. . .. movq %mm0, %mm1 -# CHECK-NEXT: [1,2] . D=====ER. . .. xorps %xmm0, %xmm0 -# CHECK-NEXT: [1,3] . D====eER . .. movaps %xmm0, %xmm1 -# CHECK-NEXT: [1,4] . D=====eER . .. movups %xmm1, %xmm2 -# CHECK-NEXT: [1,5] . D======eER . .. movapd %xmm2, %xmm3 -# CHECK-NEXT: [1,6] . D=======eER . .. movupd %xmm3, %xmm4 -# CHECK-NEXT: [1,7] . D=======eER. .. movdqa %xmm4, %xmm5 -# CHECK-NEXT: [1,8] . D========eER .. movdqu %xmm5, %xmm0 -# CHECK-NEXT: [2,0] . DeE--------R .. pxor %mm0, %mm0 -# CHECK-NEXT: [2,1] . D=eE-------R .. movq %mm0, %mm1 -# CHECK-NEXT: [2,2] . D========ER .. xorps %xmm0, %xmm0 -# CHECK-NEXT: [2,3] . D========eER .. movaps %xmm0, %xmm1 -# CHECK-NEXT: [2,4] . D=========eER .. movups %xmm1, %xmm2 -# CHECK-NEXT: [2,5] . D==========eER .. movapd %xmm2, %xmm3 -# CHECK-NEXT: [2,6] . .D==========eER.. movupd %xmm3, %xmm4 -# CHECK-NEXT: [2,7] . .D===========eER. movdqa %xmm4, %xmm5 -# CHECK-NEXT: [2,8] . .D============eER movdqu %xmm5, %xmm0 +# CHECK: [0,0] DeeER. . . . . . . . . . . . . pxor %mm0, %mm0 +# CHECK-NEXT: [0,1] D===eeER . . . . . . . . . . . . movq %mm0, %mm1 +# CHECK-NEXT: [0,2] DeeE---R . . . . . . . . . . . . xorps %xmm0, %xmm0 +# CHECK-NEXT: [0,3] .D=eeeER . . . . . . . . . . . . movaps %xmm0, %xmm1 +# CHECK-NEXT: [0,4] .D=====eeeER . . . . . . . . . . . movups %xmm1, %xmm2 +# CHECK-NEXT: [0,5] .D=========eeeER . . . . . . . . . . movapd %xmm2, %xmm3 +# CHECK-NEXT: [0,6] . D===========eeeER . . . . . . . . . . movupd %xmm3, %xmm4 +# CHECK-NEXT: [0,7] . D==============eeeER . . . . . . . . . movdqa %xmm4, %xmm5 +# CHECK-NEXT: [0,8] . D=================eeeER. . . . . . . . . movdqu %xmm5, %xmm0 +# CHECK-NEXT: [1,0] . D=eeE----------------R. . . . . . . . . pxor %mm0, %mm0 +# CHECK-NEXT: [1,1] . D====eeE-------------R. . . . . . . . . movq %mm0, %mm1 +# CHECK-NEXT: [1,2] . D===================eeER . . . . . . . . xorps %xmm0, %xmm0 +# CHECK-NEXT: [1,3] . D====================eeeER. . . . . . . . movaps %xmm0, %xmm1 +# CHECK-NEXT: [1,4] . D=======================eeeER . . . . . . . movups %xmm1, %xmm2 +# CHECK-NEXT: [1,5] . D==========================eeeER . . . . . . movapd %xmm2, %xmm3 +# CHECK-NEXT: [1,6] . D============================eeeER . . . . . . movupd %xmm3, %xmm4 +# CHECK-NEXT: [1,7] . D===============================eeeER . . . . . movdqa %xmm4, %xmm5 +# CHECK-NEXT: [1,8] . D==================================eeeER. . . . . movdqu %xmm5, %xmm0 +# CHECK-NEXT: [2,0] . .D=eeE---------------------------------R. . . . . pxor %mm0, %mm0 +# CHECK-NEXT: [2,1] . .D====eeE------------------------------R. . . . . movq %mm0, %mm1 +# CHECK-NEXT: [2,2] . .D====================================eeER . . . . xorps %xmm0, %xmm0 +# CHECK-NEXT: [2,3] . . D=====================================eeeER. . . . movaps %xmm0, %xmm1 +# CHECK-NEXT: [2,4] . . D========================================eeeER . . . movups %xmm1, %xmm2 +# CHECK-NEXT: [2,5] . . D===========================================eeeER . . movapd %xmm2, %xmm3 +# CHECK-NEXT: [2,6] . . D=============================================eeeER . . movupd %xmm3, %xmm4 +# CHECK-NEXT: [2,7] . . D================================================eeeER . movdqa %xmm4, %xmm5 +# CHECK-NEXT: [2,8] . . D===================================================eeeER movdqu %xmm5, %xmm0 # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -110,12 +135,12 @@ # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] -# CHECK-NEXT: 0. 3 1.0 1.0 4.0 pxor %mm0, %mm0 -# CHECK-NEXT: 1. 3 2.0 0.0 3.3 movq %mm0, %mm1 -# CHECK-NEXT: 2. 3 5.0 0.0 1.0 xorps %xmm0, %xmm0 -# CHECK-NEXT: 3. 3 5.3 0.7 0.0 movaps %xmm0, %xmm1 -# CHECK-NEXT: 4. 3 6.0 0.0 0.0 movups %xmm1, %xmm2 -# CHECK-NEXT: 5. 3 7.0 0.0 0.0 movapd %xmm2, %xmm3 -# CHECK-NEXT: 6. 3 7.7 0.0 0.0 movupd %xmm3, %xmm4 -# CHECK-NEXT: 7. 3 8.3 0.0 0.0 movdqa %xmm4, %xmm5 -# CHECK-NEXT: 8. 3 9.0 0.0 0.0 movdqu %xmm5, %xmm0 +# CHECK-NEXT: 0. 3 1.7 1.3 16.3 pxor %mm0, %mm0 +# CHECK-NEXT: 1. 3 4.7 1.0 14.3 movq %mm0, %mm1 +# CHECK-NEXT: 2. 3 19.3 0.3 1.0 xorps %xmm0, %xmm0 +# CHECK-NEXT: 3. 3 20.3 0.0 0.0 movaps %xmm0, %xmm1 +# CHECK-NEXT: 4. 3 23.7 0.3 0.0 movups %xmm1, %xmm2 +# CHECK-NEXT: 5. 3 27.0 0.3 0.0 movapd %xmm2, %xmm3 +# CHECK-NEXT: 6. 3 29.0 0.0 0.0 movupd %xmm3, %xmm4 +# CHECK-NEXT: 7. 3 32.0 0.0 0.0 movdqa %xmm4, %xmm5 +# CHECK-NEXT: 8. 3 35.0 0.0 0.0 movdqu %xmm5, %xmm0 diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-3.s b/llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-3.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-3.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-3.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=3 -timeline -register-file-stats < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -iterations=3 -timeline -register-file-stats < %s | FileCheck %s vxorps %xmm0, %xmm0, %xmm0 movaps %xmm0, %xmm1 @@ -11,13 +11,13 @@ # CHECK: Iterations: 3 # CHECK-NEXT: Instructions: 21 -# CHECK-NEXT: Total Cycles: 21 +# CHECK-NEXT: Total Cycles: 63 # CHECK-NEXT: Total uOps: 21 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.00 -# CHECK-NEXT: IPC: 1.00 -# CHECK-NEXT: Block RThroughput: 4.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.33 +# CHECK-NEXT: IPC: 0.33 +# CHECK-NEXT: Block RThroughput: 9.3 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -28,67 +28,92 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 0 0.25 vxorps %xmm0, %xmm0, %xmm0 -# CHECK-NEXT: 1 1 1.00 movaps %xmm0, %xmm1 -# CHECK-NEXT: 1 1 1.00 movups %xmm1, %xmm2 -# CHECK-NEXT: 1 1 1.00 movapd %xmm2, %xmm3 -# CHECK-NEXT: 1 1 1.00 movupd %xmm3, %xmm4 -# CHECK-NEXT: 1 1 0.33 movdqa %xmm4, %xmm5 -# CHECK-NEXT: 1 1 0.33 movdqu %xmm5, %xmm0 +# CHECK-NEXT: 1 2 2.00 vxorps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: 1 3 1.33 movaps %xmm0, %xmm1 +# CHECK-NEXT: 1 3 1.33 movups %xmm1, %xmm2 +# CHECK-NEXT: 1 3 1.33 movapd %xmm2, %xmm3 +# CHECK-NEXT: 1 3 1.33 movupd %xmm3, %xmm4 +# CHECK-NEXT: 1 3 2.00 movdqa %xmm4, %xmm5 +# CHECK-NEXT: 1 3 2.00 movdqu %xmm5, %xmm0 # CHECK: Register File statistics: # CHECK-NEXT: Total number of mappings created: 21 -# CHECK-NEXT: Max number of mappings used: 17 +# CHECK-NEXT: Max number of mappings used: 20 + +# CHECK: * Register File #1 -- BnFpuPRF: +# CHECK-NEXT: Number of physical registers: 120 +# CHECK-NEXT: Total number of mappings created: 21 +# CHECK-NEXT: Max number of mappings used: 20 + +# CHECK: * Register File #2 -- BnIntPRF: +# CHECK-NEXT: Number of physical registers: 40 +# CHECK-NEXT: Total number of mappings created: 0 +# CHECK-NEXT: Max number of mappings used: 0 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - 1.00 1.00 - 4.00 - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - - - - 10.67 10.67 10.67 2.33 2.33 2.33 - - - - - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - - - - - vxorps %xmm0, %xmm0, %xmm0 -# CHECK-NEXT: - - - - - 1.00 - - movaps %xmm0, %xmm1 -# CHECK-NEXT: - - - - - 1.00 - - movups %xmm1, %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - movapd %xmm2, %xmm3 -# CHECK-NEXT: - - - - - 1.00 - - movupd %xmm3, %xmm4 -# CHECK-NEXT: - - - 1.00 - - - - movdqa %xmm4, %xmm5 -# CHECK-NEXT: - - 1.00 - - - - - movdqu %xmm5, %xmm0 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - 2.67 - 1.33 0.33 0.67 - - - - - - - - - - - vxorps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: - - - - - - - - 2.67 1.33 0.33 - 0.67 - - - - - - - - - - movaps %xmm0, %xmm1 +# CHECK-NEXT: - - - - - - - 1.33 1.33 1.33 0.33 0.33 0.33 - - - - - - - - - - movups %xmm1, %xmm2 +# CHECK-NEXT: - - - - - - - 1.33 1.33 1.33 0.33 0.33 0.33 - - - - - - - - - - movapd %xmm2, %xmm3 +# CHECK-NEXT: - - - - - - - 1.33 1.33 1.33 0.33 0.33 0.33 - - - - - - - - - - movupd %xmm3, %xmm4 +# CHECK-NEXT: - - - - - - - 2.00 2.00 2.00 0.33 0.33 0.33 - - - - - - - - - - movdqa %xmm4, %xmm5 +# CHECK-NEXT: - - - - - - - 2.00 2.00 2.00 0.33 0.33 0.33 - - - - - - - - - - movdqu %xmm5, %xmm0 # CHECK: Timeline view: -# CHECK-NEXT: 0123456789 -# CHECK-NEXT: Index 0123456789 0 +# CHECK-NEXT: 0123456789 0123456789 0123456789 +# CHECK-NEXT: Index 0123456789 0123456789 0123456789 012 -# CHECK: [0,0] DR . . . . vxorps %xmm0, %xmm0, %xmm0 -# CHECK-NEXT: [0,1] DeER . . . . movaps %xmm0, %xmm1 -# CHECK-NEXT: [0,2] D=eER. . . . movups %xmm1, %xmm2 -# CHECK-NEXT: [0,3] D==eER . . . movapd %xmm2, %xmm3 -# CHECK-NEXT: [0,4] .D==eER . . . movupd %xmm3, %xmm4 -# CHECK-NEXT: [0,5] .D===eER . . . movdqa %xmm4, %xmm5 -# CHECK-NEXT: [0,6] .D====eER . . . movdqu %xmm5, %xmm0 -# CHECK-NEXT: [1,0] .D=====ER . . . vxorps %xmm0, %xmm0, %xmm0 -# CHECK-NEXT: [1,1] . D====eER. . . movaps %xmm0, %xmm1 -# CHECK-NEXT: [1,2] . D=====eER . . movups %xmm1, %xmm2 -# CHECK-NEXT: [1,3] . D======eER . . movapd %xmm2, %xmm3 -# CHECK-NEXT: [1,4] . D=======eER . . movupd %xmm3, %xmm4 -# CHECK-NEXT: [1,5] . D=======eER . . movdqa %xmm4, %xmm5 -# CHECK-NEXT: [1,6] . D========eER. . movdqu %xmm5, %xmm0 -# CHECK-NEXT: [2,0] . D=========ER. . vxorps %xmm0, %xmm0, %xmm0 -# CHECK-NEXT: [2,1] . D=========eER . movaps %xmm0, %xmm1 -# CHECK-NEXT: [2,2] . D=========eER . movups %xmm1, %xmm2 -# CHECK-NEXT: [2,3] . D==========eER . movapd %xmm2, %xmm3 -# CHECK-NEXT: [2,4] . D===========eER . movupd %xmm3, %xmm4 -# CHECK-NEXT: [2,5] . D============eER. movdqa %xmm4, %xmm5 -# CHECK-NEXT: [2,6] . D============eER movdqu %xmm5, %xmm0 +# CHECK: [0,0] DeeER. . . . . . . . . . . . . vxorps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [0,1] D==eeeER . . . . . . . . . . . . movaps %xmm0, %xmm1 +# CHECK-NEXT: [0,2] D=====eeeER . . . . . . . . . . . movups %xmm1, %xmm2 +# CHECK-NEXT: [0,3] .D=======eeeER . . . . . . . . . . . movapd %xmm2, %xmm3 +# CHECK-NEXT: [0,4] .D==========eeeER . . . . . . . . . . movupd %xmm3, %xmm4 +# CHECK-NEXT: [0,5] .D=============eeeER. . . . . . . . . . movdqa %xmm4, %xmm5 +# CHECK-NEXT: [0,6] . D===============eeeER . . . . . . . . . movdqu %xmm5, %xmm0 +# CHECK-NEXT: [1,0] . D==================eeER. . . . . . . . . vxorps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [1,1] . D====================eeeER . . . . . . . . movaps %xmm0, %xmm1 +# CHECK-NEXT: [1,2] . D======================eeeER . . . . . . . movups %xmm1, %xmm2 +# CHECK-NEXT: [1,3] . D=========================eeeER . . . . . . . movapd %xmm2, %xmm3 +# CHECK-NEXT: [1,4] . D============================eeeER . . . . . . movupd %xmm3, %xmm4 +# CHECK-NEXT: [1,5] . D==============================eeeER. . . . . . movdqa %xmm4, %xmm5 +# CHECK-NEXT: [1,6] . D=================================eeeER . . . . . movdqu %xmm5, %xmm0 +# CHECK-NEXT: [2,0] . D====================================eeER. . . . . vxorps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: [2,1] . D=====================================eeeER . . . . movaps %xmm0, %xmm1 +# CHECK-NEXT: [2,2] . D========================================eeeER . . . movups %xmm1, %xmm2 +# CHECK-NEXT: [2,3] . D===========================================eeeER . . . movapd %xmm2, %xmm3 +# CHECK-NEXT: [2,4] . .D=============================================eeeER . . movupd %xmm3, %xmm4 +# CHECK-NEXT: [2,5] . .D================================================eeeER. . movdqa %xmm4, %xmm5 +# CHECK-NEXT: [2,6] . .D===================================================eeeER movdqu %xmm5, %xmm0 # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -97,10 +122,10 @@ # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] -# CHECK-NEXT: 0. 3 5.3 0.0 0.0 vxorps %xmm0, %xmm0, %xmm0 -# CHECK-NEXT: 1. 3 5.3 0.3 0.0 movaps %xmm0, %xmm1 -# CHECK-NEXT: 2. 3 6.0 0.0 0.0 movups %xmm1, %xmm2 -# CHECK-NEXT: 3. 3 7.0 0.0 0.0 movapd %xmm2, %xmm3 -# CHECK-NEXT: 4. 3 7.7 0.0 0.0 movupd %xmm3, %xmm4 -# CHECK-NEXT: 5. 3 8.3 0.0 0.0 movdqa %xmm4, %xmm5 -# CHECK-NEXT: 6. 3 9.0 0.0 0.0 movdqu %xmm5, %xmm0 +# CHECK-NEXT: 0. 3 19.0 0.3 0.0 vxorps %xmm0, %xmm0, %xmm0 +# CHECK-NEXT: 1. 3 20.7 0.0 0.0 movaps %xmm0, %xmm1 +# CHECK-NEXT: 2. 3 23.3 0.0 0.0 movups %xmm1, %xmm2 +# CHECK-NEXT: 3. 3 26.0 0.0 0.0 movapd %xmm2, %xmm3 +# CHECK-NEXT: 4. 3 28.7 0.0 0.0 movupd %xmm3, %xmm4 +# CHECK-NEXT: 5. 3 31.3 0.0 0.0 movdqa %xmm4, %xmm5 +# CHECK-NEXT: 6. 3 34.0 0.0 0.0 movdqu %xmm5, %xmm0 diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-4.s b/llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-4.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-4.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-4.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=3 -timeline -register-file-stats < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -iterations=3 -timeline -register-file-stats < %s | FileCheck %s xor %eax, %eax mov %eax, %ebx @@ -9,13 +9,13 @@ # CHECK: Iterations: 3 # CHECK-NEXT: Instructions: 15 -# CHECK-NEXT: Total Cycles: 15 +# CHECK-NEXT: Total Cycles: 24 # CHECK-NEXT: Total uOps: 15 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.00 -# CHECK-NEXT: IPC: 1.00 -# CHECK-NEXT: Block RThroughput: 1.3 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.63 +# CHECK-NEXT: IPC: 0.63 +# CHECK-NEXT: Block RThroughput: 6.3 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -26,57 +26,82 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 0 0.25 xorl %eax, %eax -# CHECK-NEXT: 1 1 0.33 movl %eax, %ebx -# CHECK-NEXT: 1 1 0.33 movl %ebx, %ecx -# CHECK-NEXT: 1 1 0.33 movl %ecx, %edx -# CHECK-NEXT: 1 1 0.33 movl %edx, %eax +# CHECK-NEXT: 1 2 1.00 xorl %eax, %eax +# CHECK-NEXT: 1 1 1.33 movl %eax, %ebx +# CHECK-NEXT: 1 1 1.33 movl %ebx, %ecx +# CHECK-NEXT: 1 1 1.33 movl %ecx, %edx +# CHECK-NEXT: 1 1 1.33 movl %edx, %eax # CHECK: Register File statistics: # CHECK-NEXT: Total number of mappings created: 18 -# CHECK-NEXT: Max number of mappings used: 15 +# CHECK-NEXT: Max number of mappings used: 16 + +# CHECK: * Register File #1 -- BnFpuPRF: +# CHECK-NEXT: Number of physical registers: 120 +# CHECK-NEXT: Total number of mappings created: 0 +# CHECK-NEXT: Max number of mappings used: 0 + +# CHECK: * Register File #2 -- BnIntPRF: +# CHECK-NEXT: Number of physical registers: 40 +# CHECK-NEXT: Total number of mappings created: 18 +# CHECK-NEXT: Max number of mappings used: 16 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - 1.33 1.33 - 1.33 - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - 6.33 6.33 6.33 - - - - - - - 1.67 1.67 1.67 - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - - - - - xorl %eax, %eax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movl %eax, %ebx -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movl %ebx, %ecx -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movl %ecx, %edx -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movl %edx, %eax +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - xorl %eax, %eax +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - movl %eax, %ebx +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - movl %ebx, %ecx +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - movl %ecx, %edx +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - movl %edx, %eax # CHECK: Timeline view: -# CHECK-NEXT: 01234 -# CHECK-NEXT: Index 0123456789 +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 0123 -# CHECK: [0,0] DR . . . xorl %eax, %eax -# CHECK-NEXT: [0,1] DeER . . . movl %eax, %ebx -# CHECK-NEXT: [0,2] D=eER. . . movl %ebx, %ecx -# CHECK-NEXT: [0,3] D==eER . . movl %ecx, %edx -# CHECK-NEXT: [0,4] .D==eER . . movl %edx, %eax -# CHECK-NEXT: [1,0] .D===ER . . xorl %eax, %eax -# CHECK-NEXT: [1,1] .D===eER . . movl %eax, %ebx -# CHECK-NEXT: [1,2] .D====eER . . movl %ebx, %ecx -# CHECK-NEXT: [1,3] . D====eER. . movl %ecx, %edx -# CHECK-NEXT: [1,4] . D=====eER . movl %edx, %eax -# CHECK-NEXT: [2,0] . D======ER . xorl %eax, %eax -# CHECK-NEXT: [2,1] . D======eER . movl %eax, %ebx -# CHECK-NEXT: [2,2] . D======eER . movl %ebx, %ecx -# CHECK-NEXT: [2,3] . D=======eER. movl %ecx, %edx -# CHECK-NEXT: [2,4] . D========eER movl %edx, %eax +# CHECK: [0,0] DeeER. . . . . xorl %eax, %eax +# CHECK-NEXT: [0,1] D==eER . . . . movl %eax, %ebx +# CHECK-NEXT: [0,2] D===eER . . . . movl %ebx, %ecx +# CHECK-NEXT: [0,3] .D===eER . . . . movl %ecx, %edx +# CHECK-NEXT: [0,4] .D=====eER. . . . movl %edx, %eax +# CHECK-NEXT: [1,0] .D======eeER . . . xorl %eax, %eax +# CHECK-NEXT: [1,1] . D=======eER . . . movl %eax, %ebx +# CHECK-NEXT: [1,2] . D========eER . . . movl %ebx, %ecx +# CHECK-NEXT: [1,3] . D=========eER. . . movl %ecx, %edx +# CHECK-NEXT: [1,4] . D==========eER . . movl %edx, %eax +# CHECK-NEXT: [2,0] . D===========eeER . . xorl %eax, %eax +# CHECK-NEXT: [2,1] . D=============eER. . movl %eax, %ebx +# CHECK-NEXT: [2,2] . D=============eER . movl %ebx, %ecx +# CHECK-NEXT: [2,3] . D==============eER . movl %ecx, %edx +# CHECK-NEXT: [2,4] . D================eER movl %edx, %eax # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -85,8 +110,8 @@ # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] -# CHECK-NEXT: 0. 3 3.7 0.0 0.0 xorl %eax, %eax -# CHECK-NEXT: 1. 3 4.0 0.3 0.0 movl %eax, %ebx -# CHECK-NEXT: 2. 3 4.7 0.0 0.0 movl %ebx, %ecx -# CHECK-NEXT: 3. 3 5.3 0.0 0.0 movl %ecx, %edx -# CHECK-NEXT: 4. 3 6.0 0.0 0.0 movl %edx, %eax +# CHECK-NEXT: 0. 3 6.7 0.3 0.0 xorl %eax, %eax +# CHECK-NEXT: 1. 3 8.3 0.0 0.0 movl %eax, %ebx +# CHECK-NEXT: 2. 3 9.0 0.0 0.0 movl %ebx, %ecx +# CHECK-NEXT: 3. 3 9.7 0.0 0.0 movl %ecx, %edx +# CHECK-NEXT: 4. 3 11.3 1.0 0.0 movl %edx, %eax diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-5.s b/llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-5.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-5.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-5.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=3 -timeline -register-file-stats < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -iterations=3 -timeline -register-file-stats < %s | FileCheck %s xor %rax, %rax mov %rax, %rbx @@ -9,13 +9,13 @@ # CHECK: Iterations: 3 # CHECK-NEXT: Instructions: 15 -# CHECK-NEXT: Total Cycles: 15 +# CHECK-NEXT: Total Cycles: 24 # CHECK-NEXT: Total uOps: 15 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 1.00 -# CHECK-NEXT: IPC: 1.00 -# CHECK-NEXT: Block RThroughput: 1.3 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.63 +# CHECK-NEXT: IPC: 0.63 +# CHECK-NEXT: Block RThroughput: 6.3 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -26,57 +26,82 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 0 0.25 xorq %rax, %rax -# CHECK-NEXT: 1 1 0.33 movq %rax, %rbx -# CHECK-NEXT: 1 1 0.33 movq %rbx, %rcx -# CHECK-NEXT: 1 1 0.33 movq %rcx, %rdx -# CHECK-NEXT: 1 1 0.33 movq %rdx, %rax +# CHECK-NEXT: 1 2 1.00 xorq %rax, %rax +# CHECK-NEXT: 1 1 1.33 movq %rax, %rbx +# CHECK-NEXT: 1 1 1.33 movq %rbx, %rcx +# CHECK-NEXT: 1 1 1.33 movq %rcx, %rdx +# CHECK-NEXT: 1 1 1.33 movq %rdx, %rax # CHECK: Register File statistics: # CHECK-NEXT: Total number of mappings created: 18 -# CHECK-NEXT: Max number of mappings used: 15 +# CHECK-NEXT: Max number of mappings used: 16 + +# CHECK: * Register File #1 -- BnFpuPRF: +# CHECK-NEXT: Number of physical registers: 120 +# CHECK-NEXT: Total number of mappings created: 0 +# CHECK-NEXT: Max number of mappings used: 0 + +# CHECK: * Register File #2 -- BnIntPRF: +# CHECK-NEXT: Number of physical registers: 40 +# CHECK-NEXT: Total number of mappings created: 18 +# CHECK-NEXT: Max number of mappings used: 16 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - 1.33 1.33 - 1.33 - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - 6.33 6.33 6.33 - - - - - - - 1.67 1.67 1.67 - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - - - - - xorq %rax, %rax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movq %rax, %rbx -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movq %rbx, %rcx -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movq %rcx, %rdx -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movq %rdx, %rax +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - xorq %rax, %rax +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - movq %rax, %rbx +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - movq %rbx, %rcx +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - movq %rcx, %rdx +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - movq %rdx, %rax # CHECK: Timeline view: -# CHECK-NEXT: 01234 -# CHECK-NEXT: Index 0123456789 +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 0123 -# CHECK: [0,0] DR . . . xorq %rax, %rax -# CHECK-NEXT: [0,1] DeER . . . movq %rax, %rbx -# CHECK-NEXT: [0,2] D=eER. . . movq %rbx, %rcx -# CHECK-NEXT: [0,3] D==eER . . movq %rcx, %rdx -# CHECK-NEXT: [0,4] .D==eER . . movq %rdx, %rax -# CHECK-NEXT: [1,0] .D===ER . . xorq %rax, %rax -# CHECK-NEXT: [1,1] .D===eER . . movq %rax, %rbx -# CHECK-NEXT: [1,2] .D====eER . . movq %rbx, %rcx -# CHECK-NEXT: [1,3] . D====eER. . movq %rcx, %rdx -# CHECK-NEXT: [1,4] . D=====eER . movq %rdx, %rax -# CHECK-NEXT: [2,0] . D======ER . xorq %rax, %rax -# CHECK-NEXT: [2,1] . D======eER . movq %rax, %rbx -# CHECK-NEXT: [2,2] . D======eER . movq %rbx, %rcx -# CHECK-NEXT: [2,3] . D=======eER. movq %rcx, %rdx -# CHECK-NEXT: [2,4] . D========eER movq %rdx, %rax +# CHECK: [0,0] DeeER. . . . . xorq %rax, %rax +# CHECK-NEXT: [0,1] D==eER . . . . movq %rax, %rbx +# CHECK-NEXT: [0,2] D===eER . . . . movq %rbx, %rcx +# CHECK-NEXT: [0,3] .D===eER . . . . movq %rcx, %rdx +# CHECK-NEXT: [0,4] .D=====eER. . . . movq %rdx, %rax +# CHECK-NEXT: [1,0] .D======eeER . . . xorq %rax, %rax +# CHECK-NEXT: [1,1] . D=======eER . . . movq %rax, %rbx +# CHECK-NEXT: [1,2] . D========eER . . . movq %rbx, %rcx +# CHECK-NEXT: [1,3] . D=========eER. . . movq %rcx, %rdx +# CHECK-NEXT: [1,4] . D==========eER . . movq %rdx, %rax +# CHECK-NEXT: [2,0] . D===========eeER . . xorq %rax, %rax +# CHECK-NEXT: [2,1] . D=============eER. . movq %rax, %rbx +# CHECK-NEXT: [2,2] . D=============eER . movq %rbx, %rcx +# CHECK-NEXT: [2,3] . D==============eER . movq %rcx, %rdx +# CHECK-NEXT: [2,4] . D================eER movq %rdx, %rax # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -85,8 +110,8 @@ # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] -# CHECK-NEXT: 0. 3 3.7 0.0 0.0 xorq %rax, %rax -# CHECK-NEXT: 1. 3 4.0 0.3 0.0 movq %rax, %rbx -# CHECK-NEXT: 2. 3 4.7 0.0 0.0 movq %rbx, %rcx -# CHECK-NEXT: 3. 3 5.3 0.0 0.0 movq %rcx, %rdx -# CHECK-NEXT: 4. 3 6.0 0.0 0.0 movq %rdx, %rax +# CHECK-NEXT: 0. 3 6.7 0.3 0.0 xorq %rax, %rax +# CHECK-NEXT: 1. 3 8.3 0.0 0.0 movq %rax, %rbx +# CHECK-NEXT: 2. 3 9.0 0.0 0.0 movq %rbx, %rcx +# CHECK-NEXT: 3. 3 9.7 0.0 0.0 movq %rcx, %rdx +# CHECK-NEXT: 4. 3 11.3 1.0 0.0 movq %rdx, %rax diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-6.s b/llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-6.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-6.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-6.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -timeline-max-iterations=3 -register-file-stats < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -timeline -timeline-max-iterations=3 -register-file-stats < %s | FileCheck %s xor %rsi, %rsi add %rcx, %rcx @@ -10,13 +10,13 @@ # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 600 -# CHECK-NEXT: Total Cycles: 172 +# CHECK-NEXT: Total Cycles: 639 # CHECK-NEXT: Total uOps: 600 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 3.49 -# CHECK-NEXT: IPC: 3.49 -# CHECK-NEXT: Block RThroughput: 1.7 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.94 +# CHECK-NEXT: IPC: 0.94 +# CHECK-NEXT: Block RThroughput: 6.3 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -27,61 +27,87 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 0 0.25 xorq %rsi, %rsi -# CHECK-NEXT: 1 1 0.33 addq %rcx, %rcx -# CHECK-NEXT: 1 1 0.33 addq %rcx, %rcx -# CHECK-NEXT: 1 1 0.33 addq %rcx, %rcx -# CHECK-NEXT: 1 1 0.33 addq %rcx, %rcx -# CHECK-NEXT: 1 1 0.33 movl %esi, %ecx +# CHECK-NEXT: 1 2 1.00 xorq %rsi, %rsi +# CHECK-NEXT: 1 2 1.00 addq %rcx, %rcx +# CHECK-NEXT: 1 2 1.00 addq %rcx, %rcx +# CHECK-NEXT: 1 2 1.00 addq %rcx, %rcx +# CHECK-NEXT: 1 2 1.00 addq %rcx, %rcx +# CHECK-NEXT: 1 1 1.33 movl %esi, %ecx # CHECK: Register File statistics: # CHECK-NEXT: Total number of mappings created: 1100 -# CHECK-NEXT: Max number of mappings used: 141 +# CHECK-NEXT: Max number of mappings used: 40 + +# CHECK: * Register File #1 -- BnFpuPRF: +# CHECK-NEXT: Number of physical registers: 120 +# CHECK-NEXT: Total number of mappings created: 0 +# CHECK-NEXT: Max number of mappings used: 0 + +# CHECK: * Register File #2 -- BnIntPRF: +# CHECK-NEXT: Number of physical registers: 40 +# CHECK-NEXT: Total number of mappings created: 1100 +# CHECK-NEXT: Max number of mappings used: 40 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - 1.66 1.67 - 1.67 - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - 6.33 6.34 6.33 - - - - - - - 2.00 2.00 2.00 - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - - - - - xorq %rsi, %rsi -# CHECK-NEXT: - - 0.66 0.33 - 0.01 - - addq %rcx, %rcx -# CHECK-NEXT: - - - 1.00 - - - - addq %rcx, %rcx -# CHECK-NEXT: - - - 0.33 - 0.67 - - addq %rcx, %rcx -# CHECK-NEXT: - - - 0.01 - 0.99 - - addq %rcx, %rcx -# CHECK-NEXT: - - 1.00 - - - - - movl %esi, %ecx +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - 0.99 2.01 - - - - - - - - 0.33 0.67 - - - - - - - xorq %rsi, %rsi +# CHECK-NEXT: - - - - - 1.02 1.98 - - - - - - - - 0.33 0.67 - - - - - - addq %rcx, %rcx +# CHECK-NEXT: - - - - 1.02 - 1.98 - - - - - - - 0.34 - 0.66 - - - - - - addq %rcx, %rcx +# CHECK-NEXT: - - - - 1.98 0.99 0.03 - - - - - - - 0.66 0.34 - - - - - - - addq %rcx, %rcx +# CHECK-NEXT: - - - - 1.02 0.96 1.02 - - - - - - - 0.34 0.33 0.33 - - - - - - addq %rcx, %rcx +# CHECK-NEXT: - - - - 1.32 1.36 1.32 - - - - - - - 0.33 0.33 0.34 - - - - - - movl %esi, %ecx # CHECK: Timeline view: -# CHECK-NEXT: Index 0123456789 +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 012345 -# CHECK: [0,0] DR . . xorq %rsi, %rsi -# CHECK-NEXT: [0,1] DeER . . addq %rcx, %rcx -# CHECK-NEXT: [0,2] D=eER. . addq %rcx, %rcx -# CHECK-NEXT: [0,3] D==eER . addq %rcx, %rcx -# CHECK-NEXT: [0,4] .D==eER . addq %rcx, %rcx -# CHECK-NEXT: [0,5] .DeE--R . movl %esi, %ecx -# CHECK-NEXT: [1,0] .D----R . xorq %rsi, %rsi -# CHECK-NEXT: [1,1] .D=eE-R . addq %rcx, %rcx -# CHECK-NEXT: [1,2] . D=eER . addq %rcx, %rcx -# CHECK-NEXT: [1,3] . D==eER . addq %rcx, %rcx -# CHECK-NEXT: [1,4] . D===eER. addq %rcx, %rcx -# CHECK-NEXT: [1,5] . DeE---R. movl %esi, %ecx -# CHECK-NEXT: [2,0] . D----R. xorq %rsi, %rsi -# CHECK-NEXT: [2,1] . DeE--R. addq %rcx, %rcx -# CHECK-NEXT: [2,2] . D=eE-R. addq %rcx, %rcx -# CHECK-NEXT: [2,3] . D==eER. addq %rcx, %rcx -# CHECK-NEXT: [2,4] . D==eER addq %rcx, %rcx -# CHECK-NEXT: [2,5] . DeE--R movl %esi, %ecx +# CHECK: [0,0] DeeER. . . . . xorq %rsi, %rsi +# CHECK-NEXT: [0,1] DeeER. . . . . addq %rcx, %rcx +# CHECK-NEXT: [0,2] D==eeER . . . . addq %rcx, %rcx +# CHECK-NEXT: [0,3] .D====eeER. . . . addq %rcx, %rcx +# CHECK-NEXT: [0,4] .D======eeER . . . addq %rcx, %rcx +# CHECK-NEXT: [0,5] .D==eE-----R . . . movl %esi, %ecx +# CHECK-NEXT: [1,0] . D=eeE----R . . . xorq %rsi, %rsi +# CHECK-NEXT: [1,1] . D====eeE--R . . . addq %rcx, %rcx +# CHECK-NEXT: [1,2] . D======eeER . . . addq %rcx, %rcx +# CHECK-NEXT: [1,3] . D=======eeER. . . addq %rcx, %rcx +# CHECK-NEXT: [1,4] . D==========eeER . . addq %rcx, %rcx +# CHECK-NEXT: [1,5] . D======eE-----R . . movl %esi, %ecx +# CHECK-NEXT: [2,0] . D=======eeE--R . . xorq %rsi, %rsi +# CHECK-NEXT: [2,1] . D=========eeE-R . . addq %rcx, %rcx +# CHECK-NEXT: [2,2] . D============eeER . addq %rcx, %rcx +# CHECK-NEXT: [2,3] . D=============eeER . addq %rcx, %rcx +# CHECK-NEXT: [2,4] . D================eeER addq %rcx, %rcx +# CHECK-NEXT: [2,5] . D=========eE--------R movl %esi, %ecx # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -90,9 +116,9 @@ # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] -# CHECK-NEXT: 0. 3 0.0 0.0 2.7 xorq %rsi, %rsi -# CHECK-NEXT: 1. 3 1.3 0.3 1.0 addq %rcx, %rcx -# CHECK-NEXT: 2. 3 2.0 0.0 0.3 addq %rcx, %rcx -# CHECK-NEXT: 3. 3 3.0 0.0 0.0 addq %rcx, %rcx -# CHECK-NEXT: 4. 3 3.3 0.0 0.0 addq %rcx, %rcx -# CHECK-NEXT: 5. 3 1.0 1.0 2.3 movl %esi, %ecx +# CHECK-NEXT: 0. 3 3.7 2.7 2.0 xorq %rsi, %rsi +# CHECK-NEXT: 1. 3 5.3 2.0 1.0 addq %rcx, %rcx +# CHECK-NEXT: 2. 3 7.7 0.3 0.0 addq %rcx, %rcx +# CHECK-NEXT: 3. 3 9.0 0.3 0.0 addq %rcx, %rcx +# CHECK-NEXT: 4. 3 11.7 0.7 0.0 addq %rcx, %rcx +# CHECK-NEXT: 5. 3 6.7 2.0 6.0 movl %esi, %ecx diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-3dnow.s b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-3dnow.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-3dnow.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-3dnow.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -instruction-tables < %s | FileCheck %s femms @@ -87,122 +87,137 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 31 31 10.33 * * U femms -# CHECK-NEXT: 1 3 1.00 pavgusb %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * pavgusb (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pf2id %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pf2id (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pf2iw %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pf2iw (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pfacc %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pfacc (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pfadd %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pfadd (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pfcmpeq %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pfcmpeq (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pfcmpge %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pfcmpge (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pfcmpgt %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pfcmpgt (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pfmax %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pfmax (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pfmin %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pfmin (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pfmul %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pfmul (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pfnacc %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pfnacc (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pfpnacc %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pfpnacc (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pfrcp %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pfrcp (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pfrcpit1 %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pfrcpit1 (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pfrcpit2 %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pfrcpit2 (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pfrsqit1 %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pfrsqit1 (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pfrsqrt %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pfrsqrt (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pfsub %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pfsub (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pfsubr %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pfsubr (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pi2fd %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pi2fd (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pi2fw %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pi2fw (%rax), %mm2 -# CHECK-NEXT: 1 5 1.00 pmulhrw %mm0, %mm2 -# CHECK-NEXT: 2 10 1.00 * pmulhrw (%rax), %mm2 -# CHECK-NEXT: 1 5 0.50 * * prefetch (%rax) -# CHECK-NEXT: 1 5 0.50 * * prefetchw (%rax) -# CHECK-NEXT: 1 1 1.00 pswapd %mm0, %mm2 -# CHECK-NEXT: 2 6 1.00 * pswapd (%rax), %mm2 +# CHECK-NEXT: 1 2 1.00 * * U femms +# CHECK-NEXT: 1 2 1.50 pavgusb %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * pavgusb (%rax), %mm2 +# CHECK-NEXT: 1 5 2.50 pf2id %mm0, %mm2 +# CHECK-NEXT: 1 7 3.00 * pf2id (%rax), %mm2 +# CHECK-NEXT: 1 5 2.50 pf2iw %mm0, %mm2 +# CHECK-NEXT: 1 7 3.00 * pf2iw (%rax), %mm2 +# CHECK-NEXT: 1 4 2.00 pfacc %mm0, %mm2 +# CHECK-NEXT: 1 6 2.50 * pfacc (%rax), %mm2 +# CHECK-NEXT: 1 4 2.00 pfadd %mm0, %mm2 +# CHECK-NEXT: 1 6 2.50 * pfadd (%rax), %mm2 +# CHECK-NEXT: 1 4 2.00 pfcmpeq %mm0, %mm2 +# CHECK-NEXT: 1 6 2.50 * pfcmpeq (%rax), %mm2 +# CHECK-NEXT: 1 4 2.00 pfcmpge %mm0, %mm2 +# CHECK-NEXT: 1 6 2.50 * pfcmpge (%rax), %mm2 +# CHECK-NEXT: 1 4 2.00 pfcmpgt %mm0, %mm2 +# CHECK-NEXT: 1 6 2.50 * pfcmpgt (%rax), %mm2 +# CHECK-NEXT: 1 4 2.00 pfmax %mm0, %mm2 +# CHECK-NEXT: 1 6 2.50 * pfmax (%rax), %mm2 +# CHECK-NEXT: 1 4 2.00 pfmin %mm0, %mm2 +# CHECK-NEXT: 1 6 2.50 * pfmin (%rax), %mm2 +# CHECK-NEXT: 1 4 2.00 pfmul %mm0, %mm2 +# CHECK-NEXT: 1 6 2.50 * pfmul (%rax), %mm2 +# CHECK-NEXT: 1 4 2.00 pfnacc %mm0, %mm2 +# CHECK-NEXT: 1 6 2.50 * pfnacc (%rax), %mm2 +# CHECK-NEXT: 1 4 2.00 pfpnacc %mm0, %mm2 +# CHECK-NEXT: 1 6 2.50 * pfpnacc (%rax), %mm2 +# CHECK-NEXT: 1 4 2.00 pfrcp %mm0, %mm2 +# CHECK-NEXT: 1 6 2.50 * pfrcp (%rax), %mm2 +# CHECK-NEXT: 1 4 2.00 pfrcpit1 %mm0, %mm2 +# CHECK-NEXT: 1 6 2.50 * pfrcpit1 (%rax), %mm2 +# CHECK-NEXT: 1 4 2.00 pfrcpit2 %mm0, %mm2 +# CHECK-NEXT: 1 6 2.50 * pfrcpit2 (%rax), %mm2 +# CHECK-NEXT: 1 4 2.00 pfrsqit1 %mm0, %mm2 +# CHECK-NEXT: 1 6 2.50 * pfrsqit1 (%rax), %mm2 +# CHECK-NEXT: 1 4 2.00 pfrsqrt %mm0, %mm2 +# CHECK-NEXT: 1 6 2.50 * pfrsqrt (%rax), %mm2 +# CHECK-NEXT: 1 4 2.00 pfsub %mm0, %mm2 +# CHECK-NEXT: 1 6 2.50 * pfsub (%rax), %mm2 +# CHECK-NEXT: 1 4 2.00 pfsubr %mm0, %mm2 +# CHECK-NEXT: 1 6 2.50 * pfsubr (%rax), %mm2 +# CHECK-NEXT: 1 5 2.00 pi2fd %mm0, %mm2 +# CHECK-NEXT: 1 7 3.00 * pi2fd (%rax), %mm2 +# CHECK-NEXT: 1 5 2.00 pi2fw %mm0, %mm2 +# CHECK-NEXT: 1 7 3.00 * pi2fw (%rax), %mm2 +# CHECK-NEXT: 1 3 1.50 pmulhrw %mm0, %mm2 +# CHECK-NEXT: 1 5 2.00 * pmulhrw (%rax), %mm2 +# CHECK-NEXT: 1 4 0.50 * * prefetch (%rax) +# CHECK-NEXT: 1 4 0.50 * * prefetchw (%rax) +# CHECK-NEXT: 1 2 2.00 pswapd %mm0, %mm2 +# CHECK-NEXT: 1 4 2.50 * pswapd (%rax), %mm2 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - 12.33 54.33 - 12.33 13.00 13.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - 0.67 0.67 0.67 - - - 100.00 11.00 100.00 22.33 22.33 4.33 - 0.67 0.67 0.67 13.00 13.00 13.00 13.00 - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - 10.33 10.33 - 10.33 - - femms -# CHECK-NEXT: - - - 1.00 - - - - pavgusb %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pavgusb (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pf2id %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pf2id (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pf2iw %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pf2iw (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pfacc %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfacc (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pfadd %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfadd (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pfcmpeq %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfcmpeq (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pfcmpge %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfcmpge (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pfcmpgt %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfcmpgt (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pfmax %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfmax (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pfmin %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfmin (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pfmul %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfmul (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pfnacc %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfnacc (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pfpnacc %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfpnacc (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pfrcp %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfrcp (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pfrcpit1 %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfrcpit1 (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pfrcpit2 %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfrcpit2 (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pfrsqit1 %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfrsqit1 (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pfrsqrt %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfrsqrt (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pfsub %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfsub (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pfsubr %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pfsubr (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pi2fd %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pi2fd (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pi2fw %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pi2fw (%rax), %mm2 -# CHECK-NEXT: - - 1.00 - - - - - pmulhrw %mm0, %mm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmulhrw (%rax), %mm2 -# CHECK-NEXT: - - - - - - 0.50 0.50 prefetch (%rax) -# CHECK-NEXT: - - - - - - 0.50 0.50 prefetchw (%rax) -# CHECK-NEXT: - - - - - 1.00 - - pswapd %mm0, %mm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 pswapd (%rax), %mm2 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - 1.00 1.00 1.00 0.33 0.33 0.33 - - - - - - - - - - femms +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - pavgusb %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pavgusb (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pf2id %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pf2id (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pf2iw %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pf2iw (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - pfacc %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pfacc (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - pfadd %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pfadd (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - pfcmpeq %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pfcmpeq (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - pfcmpge %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pfcmpge (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - pfcmpgt %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pfcmpgt (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - pfmax %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pfmax (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - pfmin %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pfmin (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - pfmul %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pfmul (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - pfnacc %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pfnacc (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - pfpnacc %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pfpnacc (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - pfrcp %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pfrcp (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - pfrcpit1 %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pfrcpit1 (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - pfrcpit2 %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pfrcpit2 (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - pfrsqit1 %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pfrsqit1 (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - pfrsqrt %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pfrsqrt (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - pfsub %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pfsub (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - pfsubr %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pfsubr (%rax), %mm2 +# CHECK-NEXT: - - - - - - - - 2.00 - - - 1.00 - - - - - - - - - - pi2fd %mm0, %mm2 +# CHECK-NEXT: - - - - - - - - 3.00 - - - 1.00 - - - - 0.50 0.50 0.50 0.50 - - pi2fd (%rax), %mm2 +# CHECK-NEXT: - - - - - - - - 2.00 - - - 1.00 - - - - - - - - - - pi2fw %mm0, %mm2 +# CHECK-NEXT: - - - - - - - - 3.00 - - - 1.00 - - - - 0.50 0.50 0.50 0.50 - - pi2fw (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - pmulhrw %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pmulhrw (%rax), %mm2 +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - prefetch (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - prefetchw (%rax) +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - pswapd %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pswapd (%rax), %mm2 diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-cmov.s b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-cmov.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-cmov.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-cmov.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -instruction-tables < %s | FileCheck %s cmovow %si, %di cmovnow %si, %di @@ -112,212 +112,227 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 2 2 0.67 cmovow %si, %di -# CHECK-NEXT: 2 2 0.67 cmovnow %si, %di -# CHECK-NEXT: 2 2 0.67 cmovbw %si, %di -# CHECK-NEXT: 2 2 0.67 cmovaew %si, %di -# CHECK-NEXT: 2 2 0.67 cmovew %si, %di -# CHECK-NEXT: 2 2 0.67 cmovnew %si, %di -# CHECK-NEXT: 3 3 1.00 cmovbew %si, %di -# CHECK-NEXT: 3 3 1.00 cmovaw %si, %di -# CHECK-NEXT: 2 2 0.67 cmovsw %si, %di -# CHECK-NEXT: 2 2 0.67 cmovnsw %si, %di -# CHECK-NEXT: 2 2 0.67 cmovpw %si, %di -# CHECK-NEXT: 2 2 0.67 cmovnpw %si, %di -# CHECK-NEXT: 2 2 0.67 cmovlw %si, %di -# CHECK-NEXT: 2 2 0.67 cmovgew %si, %di -# CHECK-NEXT: 2 2 0.67 cmovlew %si, %di -# CHECK-NEXT: 2 2 0.67 cmovgw %si, %di -# CHECK-NEXT: 3 7 0.67 * cmovow (%rax), %di -# CHECK-NEXT: 3 7 0.67 * cmovnow (%rax), %di -# CHECK-NEXT: 3 7 0.67 * cmovbw (%rax), %di -# CHECK-NEXT: 3 7 0.67 * cmovaew (%rax), %di -# CHECK-NEXT: 3 7 0.67 * cmovew (%rax), %di -# CHECK-NEXT: 3 7 0.67 * cmovnew (%rax), %di -# CHECK-NEXT: 4 8 1.00 * cmovbew (%rax), %di -# CHECK-NEXT: 4 8 1.00 * cmovaw (%rax), %di -# CHECK-NEXT: 3 7 0.67 * cmovsw (%rax), %di -# CHECK-NEXT: 3 7 0.67 * cmovnsw (%rax), %di -# CHECK-NEXT: 3 7 0.67 * cmovpw (%rax), %di -# CHECK-NEXT: 3 7 0.67 * cmovnpw (%rax), %di -# CHECK-NEXT: 3 7 0.67 * cmovlw (%rax), %di -# CHECK-NEXT: 3 7 0.67 * cmovgew (%rax), %di -# CHECK-NEXT: 3 7 0.67 * cmovlew (%rax), %di -# CHECK-NEXT: 3 7 0.67 * cmovgw (%rax), %di -# CHECK-NEXT: 2 2 0.67 cmovol %esi, %edi -# CHECK-NEXT: 2 2 0.67 cmovnol %esi, %edi -# CHECK-NEXT: 2 2 0.67 cmovbl %esi, %edi -# CHECK-NEXT: 2 2 0.67 cmovael %esi, %edi -# CHECK-NEXT: 2 2 0.67 cmovel %esi, %edi -# CHECK-NEXT: 2 2 0.67 cmovnel %esi, %edi -# CHECK-NEXT: 3 3 1.00 cmovbel %esi, %edi -# CHECK-NEXT: 3 3 1.00 cmoval %esi, %edi -# CHECK-NEXT: 2 2 0.67 cmovsl %esi, %edi -# CHECK-NEXT: 2 2 0.67 cmovnsl %esi, %edi -# CHECK-NEXT: 2 2 0.67 cmovpl %esi, %edi -# CHECK-NEXT: 2 2 0.67 cmovnpl %esi, %edi -# CHECK-NEXT: 2 2 0.67 cmovll %esi, %edi -# CHECK-NEXT: 2 2 0.67 cmovgel %esi, %edi -# CHECK-NEXT: 2 2 0.67 cmovlel %esi, %edi -# CHECK-NEXT: 2 2 0.67 cmovgl %esi, %edi -# CHECK-NEXT: 3 7 0.67 * cmovol (%rax), %edi -# CHECK-NEXT: 3 7 0.67 * cmovnol (%rax), %edi -# CHECK-NEXT: 3 7 0.67 * cmovbl (%rax), %edi -# CHECK-NEXT: 3 7 0.67 * cmovael (%rax), %edi -# CHECK-NEXT: 3 7 0.67 * cmovel (%rax), %edi -# CHECK-NEXT: 3 7 0.67 * cmovnel (%rax), %edi -# CHECK-NEXT: 4 8 1.00 * cmovbel (%rax), %edi -# CHECK-NEXT: 4 8 1.00 * cmoval (%rax), %edi -# CHECK-NEXT: 3 7 0.67 * cmovsl (%rax), %edi -# CHECK-NEXT: 3 7 0.67 * cmovnsl (%rax), %edi -# CHECK-NEXT: 3 7 0.67 * cmovpl (%rax), %edi -# CHECK-NEXT: 3 7 0.67 * cmovnpl (%rax), %edi -# CHECK-NEXT: 3 7 0.67 * cmovll (%rax), %edi -# CHECK-NEXT: 3 7 0.67 * cmovgel (%rax), %edi -# CHECK-NEXT: 3 7 0.67 * cmovlel (%rax), %edi -# CHECK-NEXT: 3 7 0.67 * cmovgl (%rax), %edi -# CHECK-NEXT: 2 2 0.67 cmovoq %rsi, %rdi -# CHECK-NEXT: 2 2 0.67 cmovnoq %rsi, %rdi -# CHECK-NEXT: 2 2 0.67 cmovbq %rsi, %rdi -# CHECK-NEXT: 2 2 0.67 cmovaeq %rsi, %rdi -# CHECK-NEXT: 2 2 0.67 cmoveq %rsi, %rdi -# CHECK-NEXT: 2 2 0.67 cmovneq %rsi, %rdi -# CHECK-NEXT: 3 3 1.00 cmovbeq %rsi, %rdi -# CHECK-NEXT: 3 3 1.00 cmovaq %rsi, %rdi -# CHECK-NEXT: 2 2 0.67 cmovsq %rsi, %rdi -# CHECK-NEXT: 2 2 0.67 cmovnsq %rsi, %rdi -# CHECK-NEXT: 2 2 0.67 cmovpq %rsi, %rdi -# CHECK-NEXT: 2 2 0.67 cmovnpq %rsi, %rdi -# CHECK-NEXT: 2 2 0.67 cmovlq %rsi, %rdi -# CHECK-NEXT: 2 2 0.67 cmovgeq %rsi, %rdi -# CHECK-NEXT: 2 2 0.67 cmovleq %rsi, %rdi -# CHECK-NEXT: 2 2 0.67 cmovgq %rsi, %rdi -# CHECK-NEXT: 3 7 0.67 * cmovoq (%rax), %rdi -# CHECK-NEXT: 3 7 0.67 * cmovnoq (%rax), %rdi -# CHECK-NEXT: 3 7 0.67 * cmovbq (%rax), %rdi -# CHECK-NEXT: 3 7 0.67 * cmovaeq (%rax), %rdi -# CHECK-NEXT: 3 7 0.67 * cmoveq (%rax), %rdi -# CHECK-NEXT: 3 7 0.67 * cmovneq (%rax), %rdi -# CHECK-NEXT: 4 8 1.00 * cmovbeq (%rax), %rdi -# CHECK-NEXT: 4 8 1.00 * cmovaq (%rax), %rdi -# CHECK-NEXT: 3 7 0.67 * cmovsq (%rax), %rdi -# CHECK-NEXT: 3 7 0.67 * cmovnsq (%rax), %rdi -# CHECK-NEXT: 3 7 0.67 * cmovpq (%rax), %rdi -# CHECK-NEXT: 3 7 0.67 * cmovnpq (%rax), %rdi -# CHECK-NEXT: 3 7 0.67 * cmovlq (%rax), %rdi -# CHECK-NEXT: 3 7 0.67 * cmovgeq (%rax), %rdi -# CHECK-NEXT: 3 7 0.67 * cmovleq (%rax), %rdi -# CHECK-NEXT: 3 7 0.67 * cmovgq (%rax), %rdi +# CHECK-NEXT: 1 2 2.00 cmovow %si, %di +# CHECK-NEXT: 1 2 2.00 cmovnow %si, %di +# CHECK-NEXT: 1 2 2.00 cmovbw %si, %di +# CHECK-NEXT: 1 2 2.00 cmovaew %si, %di +# CHECK-NEXT: 1 2 2.00 cmovew %si, %di +# CHECK-NEXT: 1 2 2.00 cmovnew %si, %di +# CHECK-NEXT: 1 2 2.00 cmovbew %si, %di +# CHECK-NEXT: 1 2 2.00 cmovaw %si, %di +# CHECK-NEXT: 1 2 2.00 cmovsw %si, %di +# CHECK-NEXT: 1 2 2.00 cmovnsw %si, %di +# CHECK-NEXT: 1 2 2.00 cmovpw %si, %di +# CHECK-NEXT: 1 2 2.00 cmovnpw %si, %di +# CHECK-NEXT: 1 2 2.00 cmovlw %si, %di +# CHECK-NEXT: 1 2 2.00 cmovgew %si, %di +# CHECK-NEXT: 1 2 2.00 cmovlew %si, %di +# CHECK-NEXT: 1 2 2.00 cmovgw %si, %di +# CHECK-NEXT: 1 5 2.00 * cmovow (%rax), %di +# CHECK-NEXT: 1 5 2.00 * cmovnow (%rax), %di +# CHECK-NEXT: 1 5 2.00 * cmovbw (%rax), %di +# CHECK-NEXT: 1 5 2.00 * cmovaew (%rax), %di +# CHECK-NEXT: 1 5 2.00 * cmovew (%rax), %di +# CHECK-NEXT: 1 5 2.00 * cmovnew (%rax), %di +# CHECK-NEXT: 1 5 2.00 * cmovbew (%rax), %di +# CHECK-NEXT: 1 5 2.00 * cmovaw (%rax), %di +# CHECK-NEXT: 1 5 2.00 * cmovsw (%rax), %di +# CHECK-NEXT: 1 5 2.00 * cmovnsw (%rax), %di +# CHECK-NEXT: 1 5 2.00 * cmovpw (%rax), %di +# CHECK-NEXT: 1 5 2.00 * cmovnpw (%rax), %di +# CHECK-NEXT: 1 5 2.00 * cmovlw (%rax), %di +# CHECK-NEXT: 1 5 2.00 * cmovgew (%rax), %di +# CHECK-NEXT: 1 5 2.00 * cmovlew (%rax), %di +# CHECK-NEXT: 1 5 2.00 * cmovgw (%rax), %di +# CHECK-NEXT: 1 2 2.00 cmovol %esi, %edi +# CHECK-NEXT: 1 2 2.00 cmovnol %esi, %edi +# CHECK-NEXT: 1 2 2.00 cmovbl %esi, %edi +# CHECK-NEXT: 1 2 2.00 cmovael %esi, %edi +# CHECK-NEXT: 1 2 2.00 cmovel %esi, %edi +# CHECK-NEXT: 1 2 2.00 cmovnel %esi, %edi +# CHECK-NEXT: 1 2 2.00 cmovbel %esi, %edi +# CHECK-NEXT: 1 2 2.00 cmoval %esi, %edi +# CHECK-NEXT: 1 2 2.00 cmovsl %esi, %edi +# CHECK-NEXT: 1 2 2.00 cmovnsl %esi, %edi +# CHECK-NEXT: 1 2 2.00 cmovpl %esi, %edi +# CHECK-NEXT: 1 2 2.00 cmovnpl %esi, %edi +# CHECK-NEXT: 1 2 2.00 cmovll %esi, %edi +# CHECK-NEXT: 1 2 2.00 cmovgel %esi, %edi +# CHECK-NEXT: 1 2 2.00 cmovlel %esi, %edi +# CHECK-NEXT: 1 2 2.00 cmovgl %esi, %edi +# CHECK-NEXT: 1 5 2.00 * cmovol (%rax), %edi +# CHECK-NEXT: 1 5 2.00 * cmovnol (%rax), %edi +# CHECK-NEXT: 1 5 2.00 * cmovbl (%rax), %edi +# CHECK-NEXT: 1 5 2.00 * cmovael (%rax), %edi +# CHECK-NEXT: 1 5 2.00 * cmovel (%rax), %edi +# CHECK-NEXT: 1 5 2.00 * cmovnel (%rax), %edi +# CHECK-NEXT: 1 5 2.00 * cmovbel (%rax), %edi +# CHECK-NEXT: 1 5 2.00 * cmoval (%rax), %edi +# CHECK-NEXT: 1 5 2.00 * cmovsl (%rax), %edi +# CHECK-NEXT: 1 5 2.00 * cmovnsl (%rax), %edi +# CHECK-NEXT: 1 5 2.00 * cmovpl (%rax), %edi +# CHECK-NEXT: 1 5 2.00 * cmovnpl (%rax), %edi +# CHECK-NEXT: 1 5 2.00 * cmovll (%rax), %edi +# CHECK-NEXT: 1 5 2.00 * cmovgel (%rax), %edi +# CHECK-NEXT: 1 5 2.00 * cmovlel (%rax), %edi +# CHECK-NEXT: 1 5 2.00 * cmovgl (%rax), %edi +# CHECK-NEXT: 1 2 2.00 cmovoq %rsi, %rdi +# CHECK-NEXT: 1 2 2.00 cmovnoq %rsi, %rdi +# CHECK-NEXT: 1 2 2.00 cmovbq %rsi, %rdi +# CHECK-NEXT: 1 2 2.00 cmovaeq %rsi, %rdi +# CHECK-NEXT: 1 2 2.00 cmoveq %rsi, %rdi +# CHECK-NEXT: 1 2 2.00 cmovneq %rsi, %rdi +# CHECK-NEXT: 1 2 2.00 cmovbeq %rsi, %rdi +# CHECK-NEXT: 1 2 2.00 cmovaq %rsi, %rdi +# CHECK-NEXT: 1 2 2.00 cmovsq %rsi, %rdi +# CHECK-NEXT: 1 2 2.00 cmovnsq %rsi, %rdi +# CHECK-NEXT: 1 2 2.00 cmovpq %rsi, %rdi +# CHECK-NEXT: 1 2 2.00 cmovnpq %rsi, %rdi +# CHECK-NEXT: 1 2 2.00 cmovlq %rsi, %rdi +# CHECK-NEXT: 1 2 2.00 cmovgeq %rsi, %rdi +# CHECK-NEXT: 1 2 2.00 cmovleq %rsi, %rdi +# CHECK-NEXT: 1 2 2.00 cmovgq %rsi, %rdi +# CHECK-NEXT: 1 5 2.00 * cmovoq (%rax), %rdi +# CHECK-NEXT: 1 5 2.00 * cmovnoq (%rax), %rdi +# CHECK-NEXT: 1 5 2.00 * cmovbq (%rax), %rdi +# CHECK-NEXT: 1 5 2.00 * cmovaeq (%rax), %rdi +# CHECK-NEXT: 1 5 2.00 * cmoveq (%rax), %rdi +# CHECK-NEXT: 1 5 2.00 * cmovneq (%rax), %rdi +# CHECK-NEXT: 1 5 2.00 * cmovbeq (%rax), %rdi +# CHECK-NEXT: 1 5 2.00 * cmovaq (%rax), %rdi +# CHECK-NEXT: 1 5 2.00 * cmovsq (%rax), %rdi +# CHECK-NEXT: 1 5 2.00 * cmovnsq (%rax), %rdi +# CHECK-NEXT: 1 5 2.00 * cmovpq (%rax), %rdi +# CHECK-NEXT: 1 5 2.00 * cmovnpq (%rax), %rdi +# CHECK-NEXT: 1 5 2.00 * cmovlq (%rax), %rdi +# CHECK-NEXT: 1 5 2.00 * cmovgeq (%rax), %rdi +# CHECK-NEXT: 1 5 2.00 * cmovleq (%rax), %rdi +# CHECK-NEXT: 1 5 2.00 * cmovgq (%rax), %rdi # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - 86.00 32.00 - 86.00 24.00 24.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - 16.00 16.00 16.00 192.00 192.00 192.00 - - - - - - - 32.00 32.00 32.00 24.00 24.00 24.00 24.00 - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovow %si, %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnow %si, %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovbw %si, %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovaew %si, %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovew %si, %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnew %si, %di -# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - cmovbew %si, %di -# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - cmovaw %si, %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovsw %si, %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnsw %si, %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovpw %si, %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnpw %si, %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovlw %si, %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovgew %si, %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovlew %si, %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovgw %si, %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovow (%rax), %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnow (%rax), %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovbw (%rax), %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovaew (%rax), %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovew (%rax), %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnew (%rax), %di -# CHECK-NEXT: - - 1.33 0.33 - 1.33 0.50 0.50 cmovbew (%rax), %di -# CHECK-NEXT: - - 1.33 0.33 - 1.33 0.50 0.50 cmovaw (%rax), %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovsw (%rax), %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnsw (%rax), %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovpw (%rax), %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnpw (%rax), %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovlw (%rax), %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovgew (%rax), %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovlew (%rax), %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovgw (%rax), %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovol %esi, %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnol %esi, %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovbl %esi, %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovael %esi, %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovel %esi, %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnel %esi, %edi -# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - cmovbel %esi, %edi -# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - cmoval %esi, %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovsl %esi, %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnsl %esi, %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovpl %esi, %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnpl %esi, %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovll %esi, %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovgel %esi, %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovlel %esi, %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovgl %esi, %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovol (%rax), %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnol (%rax), %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovbl (%rax), %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovael (%rax), %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovel (%rax), %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnel (%rax), %edi -# CHECK-NEXT: - - 1.33 0.33 - 1.33 0.50 0.50 cmovbel (%rax), %edi -# CHECK-NEXT: - - 1.33 0.33 - 1.33 0.50 0.50 cmoval (%rax), %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovsl (%rax), %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnsl (%rax), %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovpl (%rax), %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnpl (%rax), %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovll (%rax), %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovgel (%rax), %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovlel (%rax), %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovgl (%rax), %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovoq %rsi, %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnoq %rsi, %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovbq %rsi, %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovaeq %rsi, %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmoveq %rsi, %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovneq %rsi, %rdi -# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - cmovbeq %rsi, %rdi -# CHECK-NEXT: - - 1.33 0.33 - 1.33 - - cmovaq %rsi, %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovsq %rsi, %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnsq %rsi, %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovpq %rsi, %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovnpq %rsi, %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovlq %rsi, %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovgeq %rsi, %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovleq %rsi, %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - cmovgq %rsi, %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovoq (%rax), %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnoq (%rax), %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovbq (%rax), %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovaeq (%rax), %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmoveq (%rax), %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovneq (%rax), %rdi -# CHECK-NEXT: - - 1.33 0.33 - 1.33 0.50 0.50 cmovbeq (%rax), %rdi -# CHECK-NEXT: - - 1.33 0.33 - 1.33 0.50 0.50 cmovaq (%rax), %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovsq (%rax), %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnsq (%rax), %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovpq (%rax), %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovnpq (%rax), %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovlq (%rax), %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovgeq (%rax), %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovleq (%rax), %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 cmovgq (%rax), %rdi +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovow %si, %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovnow %si, %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovbw %si, %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovaew %si, %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovew %si, %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovnew %si, %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovbew %si, %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovaw %si, %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovsw %si, %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovnsw %si, %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovpw %si, %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovnpw %si, %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovlw %si, %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovgew %si, %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovlew %si, %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovgw %si, %di +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovow (%rax), %di +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovnow (%rax), %di +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovbw (%rax), %di +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovaew (%rax), %di +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovew (%rax), %di +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovnew (%rax), %di +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovbew (%rax), %di +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovaw (%rax), %di +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovsw (%rax), %di +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovnsw (%rax), %di +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovpw (%rax), %di +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovnpw (%rax), %di +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovlw (%rax), %di +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovgew (%rax), %di +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovlew (%rax), %di +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovgw (%rax), %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovol %esi, %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovnol %esi, %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovbl %esi, %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovael %esi, %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovel %esi, %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovnel %esi, %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovbel %esi, %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmoval %esi, %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovsl %esi, %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovnsl %esi, %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovpl %esi, %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovnpl %esi, %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovll %esi, %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovgel %esi, %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovlel %esi, %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovgl %esi, %edi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovol (%rax), %edi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovnol (%rax), %edi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovbl (%rax), %edi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovael (%rax), %edi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovel (%rax), %edi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovnel (%rax), %edi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovbel (%rax), %edi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmoval (%rax), %edi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovsl (%rax), %edi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovnsl (%rax), %edi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovpl (%rax), %edi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovnpl (%rax), %edi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovll (%rax), %edi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovgel (%rax), %edi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovlel (%rax), %edi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovgl (%rax), %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovoq %rsi, %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovnoq %rsi, %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovbq %rsi, %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovaeq %rsi, %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmoveq %rsi, %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovneq %rsi, %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovbeq %rsi, %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovaq %rsi, %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovsq %rsi, %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovnsq %rsi, %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovpq %rsi, %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovnpq %rsi, %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovlq %rsi, %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovgeq %rsi, %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovleq %rsi, %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmovgq %rsi, %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovoq (%rax), %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovnoq (%rax), %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovbq (%rax), %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovaeq (%rax), %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmoveq (%rax), %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovneq (%rax), %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovbeq (%rax), %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovaq (%rax), %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovsq (%rax), %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovnsq (%rax), %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovpq (%rax), %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovnpq (%rax), %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovlq (%rax), %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovgeq (%rax), %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovleq (%rax), %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmovgq (%rax), %rdi diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-cmpxchg.s b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-cmpxchg.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-cmpxchg.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-cmpxchg.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -instruction-tables < %s | FileCheck %s cmpxchg8b (%rax) cmpxchg16b (%rax) @@ -13,24 +13,39 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 3 6 1.00 * * cmpxchg8b (%rax) -# CHECK-NEXT: 3 6 1.00 * * cmpxchg16b (%rax) +# CHECK-NEXT: 6 5 24.33 * * cmpxchg8b (%rax) +# CHECK-NEXT: 6 5 24.33 * * cmpxchg16b (%rax) # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - 0.67 0.67 2.00 0.67 2.00 2.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - 1.33 1.33 1.33 48.67 48.67 48.67 - - - - - - - 0.67 0.67 0.67 2.00 2.00 1.00 1.00 1.00 1.00 # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 cmpxchg8b (%rax) -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 cmpxchg16b (%rax) +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - 0.67 0.67 0.67 24.33 24.33 24.33 - - - - - - - 0.33 0.33 0.33 1.00 1.00 0.50 0.50 0.50 0.50 cmpxchg8b (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 24.33 24.33 24.33 - - - - - - - 0.33 0.33 0.33 1.00 1.00 0.50 0.50 0.50 0.50 cmpxchg16b (%rax) diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-lea.s b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-lea.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-lea.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-lea.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -instruction-tables < %s | FileCheck %s lea 0(), %cx lea 0(), %ecx @@ -148,290 +148,305 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 1 0.50 leaw 0, %cx -# CHECK-NEXT: 1 1 0.50 leal 0, %ecx -# CHECK-NEXT: 1 1 0.50 leaq 0, %rcx -# CHECK-NEXT: 1 1 0.50 leaw (%eax), %cx -# CHECK-NEXT: 1 1 0.50 leal (%eax), %ecx -# CHECK-NEXT: 1 1 0.50 leaq (%eax), %rcx -# CHECK-NEXT: 1 1 0.50 leaw (%rax), %cx -# CHECK-NEXT: 1 1 0.50 leal (%rax), %ecx -# CHECK-NEXT: 1 1 0.50 leaq (%rax), %rcx -# CHECK-NEXT: 1 1 0.50 leaw (,%ebx), %cx -# CHECK-NEXT: 1 1 0.50 leal (,%ebx), %ecx -# CHECK-NEXT: 1 1 0.50 leaq (,%ebx), %rcx -# CHECK-NEXT: 1 1 0.50 leaw (,%rbx), %cx -# CHECK-NEXT: 1 1 0.50 leal (,%rbx), %ecx -# CHECK-NEXT: 1 1 0.50 leaq (,%rbx), %rcx -# CHECK-NEXT: 1 1 0.50 leaw (,%ebx), %cx -# CHECK-NEXT: 1 1 0.50 leal (,%ebx), %ecx -# CHECK-NEXT: 1 1 0.50 leaq (,%ebx), %rcx -# CHECK-NEXT: 1 1 0.50 leaw (,%rbx), %cx -# CHECK-NEXT: 1 1 0.50 leal (,%rbx), %ecx -# CHECK-NEXT: 1 1 0.50 leaq (,%rbx), %rcx -# CHECK-NEXT: 1 1 0.50 leaw (,%ebx,2), %cx -# CHECK-NEXT: 1 1 0.50 leal (,%ebx,2), %ecx -# CHECK-NEXT: 1 1 0.50 leaq (,%ebx,2), %rcx -# CHECK-NEXT: 1 1 0.50 leaw (,%rbx,2), %cx -# CHECK-NEXT: 1 1 0.50 leal (,%rbx,2), %ecx -# CHECK-NEXT: 1 1 0.50 leaq (,%rbx,2), %rcx -# CHECK-NEXT: 1 1 0.50 leaw (%eax,%ebx), %cx -# CHECK-NEXT: 1 1 0.50 leal (%eax,%ebx), %ecx -# CHECK-NEXT: 1 1 0.50 leaq (%eax,%ebx), %rcx -# CHECK-NEXT: 1 1 0.50 leaw (%rax,%rbx), %cx -# CHECK-NEXT: 1 1 0.50 leal (%rax,%rbx), %ecx -# CHECK-NEXT: 1 1 0.50 leaq (%rax,%rbx), %rcx -# CHECK-NEXT: 1 1 0.50 leaw (%eax,%ebx), %cx -# CHECK-NEXT: 1 1 0.50 leal (%eax,%ebx), %ecx -# CHECK-NEXT: 1 1 0.50 leaq (%eax,%ebx), %rcx -# CHECK-NEXT: 1 1 0.50 leaw (%rax,%rbx), %cx -# CHECK-NEXT: 1 1 0.50 leal (%rax,%rbx), %ecx -# CHECK-NEXT: 1 1 0.50 leaq (%rax,%rbx), %rcx -# CHECK-NEXT: 1 1 0.50 leaw (%eax,%ebx,2), %cx -# CHECK-NEXT: 1 1 0.50 leal (%eax,%ebx,2), %ecx -# CHECK-NEXT: 1 1 0.50 leaq (%eax,%ebx,2), %rcx -# CHECK-NEXT: 1 1 0.50 leaw (%rax,%rbx,2), %cx -# CHECK-NEXT: 1 1 0.50 leal (%rax,%rbx,2), %ecx -# CHECK-NEXT: 1 1 0.50 leaq (%rax,%rbx,2), %rcx -# CHECK-NEXT: 1 1 0.50 leaw -16, %cx -# CHECK-NEXT: 1 1 0.50 leal -16, %ecx -# CHECK-NEXT: 1 1 0.50 leaq -16, %rcx -# CHECK-NEXT: 1 1 0.50 leaw -16(%eax), %cx -# CHECK-NEXT: 1 1 0.50 leal -16(%eax), %ecx -# CHECK-NEXT: 1 1 0.50 leaq -16(%eax), %rcx -# CHECK-NEXT: 1 1 0.50 leaw -16(%rax), %cx -# CHECK-NEXT: 1 1 0.50 leal -16(%rax), %ecx -# CHECK-NEXT: 1 1 0.50 leaq -16(%rax), %rcx -# CHECK-NEXT: 1 1 0.50 leaw -16(,%ebx), %cx -# CHECK-NEXT: 1 1 0.50 leal -16(,%ebx), %ecx -# CHECK-NEXT: 1 1 0.50 leaq -16(,%ebx), %rcx -# CHECK-NEXT: 1 1 0.50 leaw -16(,%rbx), %cx -# CHECK-NEXT: 1 1 0.50 leal -16(,%rbx), %ecx -# CHECK-NEXT: 1 1 0.50 leaq -16(,%rbx), %rcx -# CHECK-NEXT: 1 1 0.50 leaw -16(,%ebx), %cx -# CHECK-NEXT: 1 1 0.50 leal -16(,%ebx), %ecx -# CHECK-NEXT: 1 1 0.50 leaq -16(,%ebx), %rcx -# CHECK-NEXT: 1 1 0.50 leaw -16(,%rbx), %cx -# CHECK-NEXT: 1 1 0.50 leal -16(,%rbx), %ecx -# CHECK-NEXT: 1 1 0.50 leaq -16(,%rbx), %rcx -# CHECK-NEXT: 1 1 0.50 leaw -16(,%ebx,2), %cx -# CHECK-NEXT: 1 1 0.50 leal -16(,%ebx,2), %ecx -# CHECK-NEXT: 1 1 0.50 leaq -16(,%ebx,2), %rcx -# CHECK-NEXT: 1 1 0.50 leaw -16(,%rbx,2), %cx -# CHECK-NEXT: 1 1 0.50 leal -16(,%rbx,2), %ecx -# CHECK-NEXT: 1 1 0.50 leaq -16(,%rbx,2), %rcx -# CHECK-NEXT: 1 1 0.50 leaw -16(%eax,%ebx), %cx -# CHECK-NEXT: 1 1 0.50 leal -16(%eax,%ebx), %ecx -# CHECK-NEXT: 1 1 0.50 leaq -16(%eax,%ebx), %rcx -# CHECK-NEXT: 1 1 0.50 leaw -16(%rax,%rbx), %cx -# CHECK-NEXT: 1 1 0.50 leal -16(%rax,%rbx), %ecx -# CHECK-NEXT: 1 1 0.50 leaq -16(%rax,%rbx), %rcx -# CHECK-NEXT: 1 1 0.50 leaw -16(%eax,%ebx), %cx -# CHECK-NEXT: 1 1 0.50 leal -16(%eax,%ebx), %ecx -# CHECK-NEXT: 1 1 0.50 leaq -16(%eax,%ebx), %rcx -# CHECK-NEXT: 1 1 0.50 leaw -16(%rax,%rbx), %cx -# CHECK-NEXT: 1 1 0.50 leal -16(%rax,%rbx), %ecx -# CHECK-NEXT: 1 1 0.50 leaq -16(%rax,%rbx), %rcx -# CHECK-NEXT: 1 1 0.50 leaw -16(%eax,%ebx,2), %cx -# CHECK-NEXT: 1 1 0.50 leal -16(%eax,%ebx,2), %ecx -# CHECK-NEXT: 1 1 0.50 leaq -16(%eax,%ebx,2), %rcx -# CHECK-NEXT: 1 1 0.50 leaw -16(%rax,%rbx,2), %cx -# CHECK-NEXT: 1 1 0.50 leal -16(%rax,%rbx,2), %ecx -# CHECK-NEXT: 1 1 0.50 leaq -16(%rax,%rbx,2), %rcx -# CHECK-NEXT: 1 1 0.50 leaw 1024, %cx -# CHECK-NEXT: 1 1 0.50 leal 1024, %ecx -# CHECK-NEXT: 1 1 0.50 leaq 1024, %rcx -# CHECK-NEXT: 1 1 0.50 leaw 1024(%eax), %cx -# CHECK-NEXT: 1 1 0.50 leal 1024(%eax), %ecx -# CHECK-NEXT: 1 1 0.50 leaq 1024(%eax), %rcx -# CHECK-NEXT: 1 1 0.50 leaw 1024(%rax), %cx -# CHECK-NEXT: 1 1 0.50 leal 1024(%rax), %ecx -# CHECK-NEXT: 1 1 0.50 leaq 1024(%rax), %rcx -# CHECK-NEXT: 1 1 0.50 leaw 1024(,%ebx), %cx -# CHECK-NEXT: 1 1 0.50 leal 1024(,%ebx), %ecx -# CHECK-NEXT: 1 1 0.50 leaq 1024(,%ebx), %rcx -# CHECK-NEXT: 1 1 0.50 leaw 1024(,%rbx), %cx -# CHECK-NEXT: 1 1 0.50 leal 1024(,%rbx), %ecx -# CHECK-NEXT: 1 1 0.50 leaq 1024(,%rbx), %rcx -# CHECK-NEXT: 1 1 0.50 leaw 1024(,%ebx), %cx -# CHECK-NEXT: 1 1 0.50 leal 1024(,%ebx), %ecx -# CHECK-NEXT: 1 1 0.50 leaq 1024(,%ebx), %rcx -# CHECK-NEXT: 1 1 0.50 leaw 1024(,%rbx), %cx -# CHECK-NEXT: 1 1 0.50 leal 1024(,%rbx), %ecx -# CHECK-NEXT: 1 1 0.50 leaq 1024(,%rbx), %rcx -# CHECK-NEXT: 1 1 0.50 leaw 1024(,%ebx,2), %cx -# CHECK-NEXT: 1 1 0.50 leal 1024(,%ebx,2), %ecx -# CHECK-NEXT: 1 1 0.50 leaq 1024(,%ebx,2), %rcx -# CHECK-NEXT: 1 1 0.50 leaw 1024(,%rbx,2), %cx -# CHECK-NEXT: 1 1 0.50 leal 1024(,%rbx,2), %ecx -# CHECK-NEXT: 1 1 0.50 leaq 1024(,%rbx,2), %rcx -# CHECK-NEXT: 1 1 0.50 leaw 1024(%eax,%ebx), %cx -# CHECK-NEXT: 1 1 0.50 leal 1024(%eax,%ebx), %ecx -# CHECK-NEXT: 1 1 0.50 leaq 1024(%eax,%ebx), %rcx -# CHECK-NEXT: 1 1 0.50 leaw 1024(%rax,%rbx), %cx -# CHECK-NEXT: 1 1 0.50 leal 1024(%rax,%rbx), %ecx -# CHECK-NEXT: 1 1 0.50 leaq 1024(%rax,%rbx), %rcx -# CHECK-NEXT: 1 1 0.50 leaw 1024(%eax,%ebx), %cx -# CHECK-NEXT: 1 1 0.50 leal 1024(%eax,%ebx), %ecx -# CHECK-NEXT: 1 1 0.50 leaq 1024(%eax,%ebx), %rcx -# CHECK-NEXT: 1 1 0.50 leaw 1024(%rax,%rbx), %cx -# CHECK-NEXT: 1 1 0.50 leal 1024(%rax,%rbx), %ecx -# CHECK-NEXT: 1 1 0.50 leaq 1024(%rax,%rbx), %rcx -# CHECK-NEXT: 1 1 0.50 leaw 1024(%eax,%ebx,2), %cx -# CHECK-NEXT: 1 1 0.50 leal 1024(%eax,%ebx,2), %ecx -# CHECK-NEXT: 1 1 0.50 leaq 1024(%eax,%ebx,2), %rcx -# CHECK-NEXT: 1 1 0.50 leaw 1024(%rax,%rbx,2), %cx -# CHECK-NEXT: 1 1 0.50 leal 1024(%rax,%rbx,2), %ecx -# CHECK-NEXT: 1 1 0.50 leaq 1024(%rax,%rbx,2), %rcx +# CHECK-NEXT: 1 1 2.67 leaw 0, %cx +# CHECK-NEXT: 1 1 2.67 leal 0, %ecx +# CHECK-NEXT: 1 1 2.67 leaq 0, %rcx +# CHECK-NEXT: 1 1 2.67 leaw (%eax), %cx +# CHECK-NEXT: 1 1 2.67 leal (%eax), %ecx +# CHECK-NEXT: 1 1 2.67 leaq (%eax), %rcx +# CHECK-NEXT: 1 1 2.67 leaw (%rax), %cx +# CHECK-NEXT: 1 1 2.67 leal (%rax), %ecx +# CHECK-NEXT: 1 1 2.67 leaq (%rax), %rcx +# CHECK-NEXT: 1 1 2.67 leaw (,%ebx), %cx +# CHECK-NEXT: 1 1 2.67 leal (,%ebx), %ecx +# CHECK-NEXT: 1 1 2.67 leaq (,%ebx), %rcx +# CHECK-NEXT: 1 1 2.67 leaw (,%rbx), %cx +# CHECK-NEXT: 1 1 2.67 leal (,%rbx), %ecx +# CHECK-NEXT: 1 1 2.67 leaq (,%rbx), %rcx +# CHECK-NEXT: 1 1 2.67 leaw (,%ebx), %cx +# CHECK-NEXT: 1 1 2.67 leal (,%ebx), %ecx +# CHECK-NEXT: 1 1 2.67 leaq (,%ebx), %rcx +# CHECK-NEXT: 1 1 2.67 leaw (,%rbx), %cx +# CHECK-NEXT: 1 1 2.67 leal (,%rbx), %ecx +# CHECK-NEXT: 1 1 2.67 leaq (,%rbx), %rcx +# CHECK-NEXT: 1 1 2.67 leaw (,%ebx,2), %cx +# CHECK-NEXT: 1 1 2.67 leal (,%ebx,2), %ecx +# CHECK-NEXT: 1 1 2.67 leaq (,%ebx,2), %rcx +# CHECK-NEXT: 1 1 2.67 leaw (,%rbx,2), %cx +# CHECK-NEXT: 1 1 2.67 leal (,%rbx,2), %ecx +# CHECK-NEXT: 1 1 2.67 leaq (,%rbx,2), %rcx +# CHECK-NEXT: 1 1 2.67 leaw (%eax,%ebx), %cx +# CHECK-NEXT: 1 1 2.67 leal (%eax,%ebx), %ecx +# CHECK-NEXT: 1 1 2.67 leaq (%eax,%ebx), %rcx +# CHECK-NEXT: 1 1 2.67 leaw (%rax,%rbx), %cx +# CHECK-NEXT: 1 1 2.67 leal (%rax,%rbx), %ecx +# CHECK-NEXT: 1 1 2.67 leaq (%rax,%rbx), %rcx +# CHECK-NEXT: 1 1 2.67 leaw (%eax,%ebx), %cx +# CHECK-NEXT: 1 1 2.67 leal (%eax,%ebx), %ecx +# CHECK-NEXT: 1 1 2.67 leaq (%eax,%ebx), %rcx +# CHECK-NEXT: 1 1 2.67 leaw (%rax,%rbx), %cx +# CHECK-NEXT: 1 1 2.67 leal (%rax,%rbx), %ecx +# CHECK-NEXT: 1 1 2.67 leaq (%rax,%rbx), %rcx +# CHECK-NEXT: 1 1 2.67 leaw (%eax,%ebx,2), %cx +# CHECK-NEXT: 1 1 2.67 leal (%eax,%ebx,2), %ecx +# CHECK-NEXT: 1 1 2.67 leaq (%eax,%ebx,2), %rcx +# CHECK-NEXT: 1 1 2.67 leaw (%rax,%rbx,2), %cx +# CHECK-NEXT: 1 1 2.67 leal (%rax,%rbx,2), %ecx +# CHECK-NEXT: 1 1 2.67 leaq (%rax,%rbx,2), %rcx +# CHECK-NEXT: 1 1 2.67 leaw -16, %cx +# CHECK-NEXT: 1 1 2.67 leal -16, %ecx +# CHECK-NEXT: 1 1 2.67 leaq -16, %rcx +# CHECK-NEXT: 1 1 2.67 leaw -16(%eax), %cx +# CHECK-NEXT: 1 1 2.67 leal -16(%eax), %ecx +# CHECK-NEXT: 1 1 2.67 leaq -16(%eax), %rcx +# CHECK-NEXT: 1 1 2.67 leaw -16(%rax), %cx +# CHECK-NEXT: 1 1 2.67 leal -16(%rax), %ecx +# CHECK-NEXT: 1 1 2.67 leaq -16(%rax), %rcx +# CHECK-NEXT: 1 1 2.67 leaw -16(,%ebx), %cx +# CHECK-NEXT: 1 1 2.67 leal -16(,%ebx), %ecx +# CHECK-NEXT: 1 1 2.67 leaq -16(,%ebx), %rcx +# CHECK-NEXT: 1 1 2.67 leaw -16(,%rbx), %cx +# CHECK-NEXT: 1 1 2.67 leal -16(,%rbx), %ecx +# CHECK-NEXT: 1 1 2.67 leaq -16(,%rbx), %rcx +# CHECK-NEXT: 1 1 2.67 leaw -16(,%ebx), %cx +# CHECK-NEXT: 1 1 2.67 leal -16(,%ebx), %ecx +# CHECK-NEXT: 1 1 2.67 leaq -16(,%ebx), %rcx +# CHECK-NEXT: 1 1 2.67 leaw -16(,%rbx), %cx +# CHECK-NEXT: 1 1 2.67 leal -16(,%rbx), %ecx +# CHECK-NEXT: 1 1 2.67 leaq -16(,%rbx), %rcx +# CHECK-NEXT: 1 1 2.67 leaw -16(,%ebx,2), %cx +# CHECK-NEXT: 1 1 2.67 leal -16(,%ebx,2), %ecx +# CHECK-NEXT: 1 1 2.67 leaq -16(,%ebx,2), %rcx +# CHECK-NEXT: 1 1 2.67 leaw -16(,%rbx,2), %cx +# CHECK-NEXT: 1 1 2.67 leal -16(,%rbx,2), %ecx +# CHECK-NEXT: 1 1 2.67 leaq -16(,%rbx,2), %rcx +# CHECK-NEXT: 1 1 2.67 leaw -16(%eax,%ebx), %cx +# CHECK-NEXT: 1 1 2.67 leal -16(%eax,%ebx), %ecx +# CHECK-NEXT: 1 1 2.67 leaq -16(%eax,%ebx), %rcx +# CHECK-NEXT: 1 1 2.67 leaw -16(%rax,%rbx), %cx +# CHECK-NEXT: 1 1 2.67 leal -16(%rax,%rbx), %ecx +# CHECK-NEXT: 1 1 2.67 leaq -16(%rax,%rbx), %rcx +# CHECK-NEXT: 1 1 2.67 leaw -16(%eax,%ebx), %cx +# CHECK-NEXT: 1 1 2.67 leal -16(%eax,%ebx), %ecx +# CHECK-NEXT: 1 1 2.67 leaq -16(%eax,%ebx), %rcx +# CHECK-NEXT: 1 1 2.67 leaw -16(%rax,%rbx), %cx +# CHECK-NEXT: 1 1 2.67 leal -16(%rax,%rbx), %ecx +# CHECK-NEXT: 1 1 2.67 leaq -16(%rax,%rbx), %rcx +# CHECK-NEXT: 1 1 2.67 leaw -16(%eax,%ebx,2), %cx +# CHECK-NEXT: 1 1 2.67 leal -16(%eax,%ebx,2), %ecx +# CHECK-NEXT: 1 1 2.67 leaq -16(%eax,%ebx,2), %rcx +# CHECK-NEXT: 1 1 2.67 leaw -16(%rax,%rbx,2), %cx +# CHECK-NEXT: 1 1 2.67 leal -16(%rax,%rbx,2), %ecx +# CHECK-NEXT: 1 1 2.67 leaq -16(%rax,%rbx,2), %rcx +# CHECK-NEXT: 1 1 2.67 leaw 1024, %cx +# CHECK-NEXT: 1 1 2.67 leal 1024, %ecx +# CHECK-NEXT: 1 1 2.67 leaq 1024, %rcx +# CHECK-NEXT: 1 1 2.67 leaw 1024(%eax), %cx +# CHECK-NEXT: 1 1 2.67 leal 1024(%eax), %ecx +# CHECK-NEXT: 1 1 2.67 leaq 1024(%eax), %rcx +# CHECK-NEXT: 1 1 2.67 leaw 1024(%rax), %cx +# CHECK-NEXT: 1 1 2.67 leal 1024(%rax), %ecx +# CHECK-NEXT: 1 1 2.67 leaq 1024(%rax), %rcx +# CHECK-NEXT: 1 1 2.67 leaw 1024(,%ebx), %cx +# CHECK-NEXT: 1 1 2.67 leal 1024(,%ebx), %ecx +# CHECK-NEXT: 1 1 2.67 leaq 1024(,%ebx), %rcx +# CHECK-NEXT: 1 1 2.67 leaw 1024(,%rbx), %cx +# CHECK-NEXT: 1 1 2.67 leal 1024(,%rbx), %ecx +# CHECK-NEXT: 1 1 2.67 leaq 1024(,%rbx), %rcx +# CHECK-NEXT: 1 1 2.67 leaw 1024(,%ebx), %cx +# CHECK-NEXT: 1 1 2.67 leal 1024(,%ebx), %ecx +# CHECK-NEXT: 1 1 2.67 leaq 1024(,%ebx), %rcx +# CHECK-NEXT: 1 1 2.67 leaw 1024(,%rbx), %cx +# CHECK-NEXT: 1 1 2.67 leal 1024(,%rbx), %ecx +# CHECK-NEXT: 1 1 2.67 leaq 1024(,%rbx), %rcx +# CHECK-NEXT: 1 1 2.67 leaw 1024(,%ebx,2), %cx +# CHECK-NEXT: 1 1 2.67 leal 1024(,%ebx,2), %ecx +# CHECK-NEXT: 1 1 2.67 leaq 1024(,%ebx,2), %rcx +# CHECK-NEXT: 1 1 2.67 leaw 1024(,%rbx,2), %cx +# CHECK-NEXT: 1 1 2.67 leal 1024(,%rbx,2), %ecx +# CHECK-NEXT: 1 1 2.67 leaq 1024(,%rbx,2), %rcx +# CHECK-NEXT: 1 1 2.67 leaw 1024(%eax,%ebx), %cx +# CHECK-NEXT: 1 1 2.67 leal 1024(%eax,%ebx), %ecx +# CHECK-NEXT: 1 1 2.67 leaq 1024(%eax,%ebx), %rcx +# CHECK-NEXT: 1 1 2.67 leaw 1024(%rax,%rbx), %cx +# CHECK-NEXT: 1 1 2.67 leal 1024(%rax,%rbx), %ecx +# CHECK-NEXT: 1 1 2.67 leaq 1024(%rax,%rbx), %rcx +# CHECK-NEXT: 1 1 2.67 leaw 1024(%eax,%ebx), %cx +# CHECK-NEXT: 1 1 2.67 leal 1024(%eax,%ebx), %ecx +# CHECK-NEXT: 1 1 2.67 leaq 1024(%eax,%ebx), %rcx +# CHECK-NEXT: 1 1 2.67 leaw 1024(%rax,%rbx), %cx +# CHECK-NEXT: 1 1 2.67 leal 1024(%rax,%rbx), %ecx +# CHECK-NEXT: 1 1 2.67 leaq 1024(%rax,%rbx), %rcx +# CHECK-NEXT: 1 1 2.67 leaw 1024(%eax,%ebx,2), %cx +# CHECK-NEXT: 1 1 2.67 leal 1024(%eax,%ebx,2), %ecx +# CHECK-NEXT: 1 1 2.67 leaq 1024(%eax,%ebx,2), %rcx +# CHECK-NEXT: 1 1 2.67 leaw 1024(%rax,%rbx,2), %cx +# CHECK-NEXT: 1 1 2.67 leal 1024(%rax,%rbx,2), %ecx +# CHECK-NEXT: 1 1 2.67 leaq 1024(%rax,%rbx,2), %rcx # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - 67.50 67.50 - - - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - 360.00 360.00 360.00 - - - - - - - 45.00 45.00 45.00 - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 0, %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal 0, %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 0, %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (%eax), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal (%eax), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (%eax), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (%rax), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal (%rax), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (%rax), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (,%ebx), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal (,%ebx), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (,%ebx), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (,%rbx), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal (,%rbx), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (,%rbx), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (,%ebx), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal (,%ebx), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (,%ebx), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (,%rbx), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal (,%rbx), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (,%rbx), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (,%ebx,2), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal (,%ebx,2), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (,%ebx,2), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (,%rbx,2), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal (,%rbx,2), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (,%rbx,2), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (%eax,%ebx), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal (%eax,%ebx), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (%eax,%ebx), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (%rax,%rbx), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal (%rax,%rbx), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (%rax,%rbx), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (%eax,%ebx), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal (%eax,%ebx), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (%eax,%ebx), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (%rax,%rbx), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal (%rax,%rbx), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (%rax,%rbx), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (%eax,%ebx,2), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal (%eax,%ebx,2), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (%eax,%ebx,2), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw (%rax,%rbx,2), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal (%rax,%rbx,2), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq (%rax,%rbx,2), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16, %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16, %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16, %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(%eax), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(%eax), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(%eax), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(%rax), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(%rax), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(%rax), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(,%ebx), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(,%ebx), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(,%ebx), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(,%rbx), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(,%rbx), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(,%rbx), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(,%ebx), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(,%ebx), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(,%ebx), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(,%rbx), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(,%rbx), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(,%rbx), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(,%ebx,2), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(,%ebx,2), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(,%ebx,2), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(,%rbx,2), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(,%rbx,2), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(,%rbx,2), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(%eax,%ebx), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(%eax,%ebx), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(%eax,%ebx), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(%rax,%rbx), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(%rax,%rbx), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(%rax,%rbx), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(%eax,%ebx), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(%eax,%ebx), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(%eax,%ebx), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(%rax,%rbx), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(%rax,%rbx), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(%rax,%rbx), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(%eax,%ebx,2), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(%eax,%ebx,2), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(%eax,%ebx,2), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw -16(%rax,%rbx,2), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal -16(%rax,%rbx,2), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq -16(%rax,%rbx,2), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024, %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024, %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024, %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(%eax), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(%eax), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(%eax), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(%rax), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(%rax), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(%rax), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(,%ebx), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(,%ebx), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(,%ebx), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(,%rbx), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(,%rbx), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(,%rbx), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(,%ebx), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(,%ebx), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(,%ebx), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(,%rbx), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(,%rbx), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(,%rbx), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(,%ebx,2), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(,%ebx,2), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(,%ebx,2), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(,%rbx,2), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(,%rbx,2), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(,%rbx,2), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(%eax,%ebx), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(%eax,%ebx), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(%eax,%ebx), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(%rax,%rbx), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(%rax,%rbx), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(%rax,%rbx), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(%eax,%ebx), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(%eax,%ebx), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(%eax,%ebx), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(%rax,%rbx), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(%rax,%rbx), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(%rax,%rbx), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(%eax,%ebx,2), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(%eax,%ebx,2), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(%eax,%ebx,2), %rcx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaw 1024(%rax,%rbx,2), %cx -# CHECK-NEXT: - - 0.50 0.50 - - - - leal 1024(%rax,%rbx,2), %ecx -# CHECK-NEXT: - - 0.50 0.50 - - - - leaq 1024(%rax,%rbx,2), %rcx +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw 0, %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal 0, %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq 0, %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw (%eax), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal (%eax), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq (%eax), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw (%rax), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal (%rax), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq (%rax), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw (,%ebx), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal (,%ebx), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq (,%ebx), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw (,%rbx), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal (,%rbx), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq (,%rbx), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw (,%ebx), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal (,%ebx), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq (,%ebx), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw (,%rbx), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal (,%rbx), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq (,%rbx), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw (,%ebx,2), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal (,%ebx,2), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq (,%ebx,2), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw (,%rbx,2), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal (,%rbx,2), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq (,%rbx,2), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw (%eax,%ebx), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal (%eax,%ebx), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq (%eax,%ebx), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw (%rax,%rbx), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal (%rax,%rbx), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq (%rax,%rbx), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw (%eax,%ebx), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal (%eax,%ebx), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq (%eax,%ebx), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw (%rax,%rbx), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal (%rax,%rbx), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq (%rax,%rbx), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw (%eax,%ebx,2), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal (%eax,%ebx,2), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq (%eax,%ebx,2), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw (%rax,%rbx,2), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal (%rax,%rbx,2), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq (%rax,%rbx,2), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw -16, %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal -16, %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq -16, %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw -16(%eax), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal -16(%eax), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq -16(%eax), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw -16(%rax), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal -16(%rax), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq -16(%rax), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw -16(,%ebx), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal -16(,%ebx), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq -16(,%ebx), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw -16(,%rbx), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal -16(,%rbx), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq -16(,%rbx), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw -16(,%ebx), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal -16(,%ebx), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq -16(,%ebx), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw -16(,%rbx), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal -16(,%rbx), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq -16(,%rbx), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw -16(,%ebx,2), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal -16(,%ebx,2), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq -16(,%ebx,2), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw -16(,%rbx,2), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal -16(,%rbx,2), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq -16(,%rbx,2), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw -16(%eax,%ebx), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal -16(%eax,%ebx), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq -16(%eax,%ebx), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw -16(%rax,%rbx), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal -16(%rax,%rbx), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq -16(%rax,%rbx), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw -16(%eax,%ebx), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal -16(%eax,%ebx), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq -16(%eax,%ebx), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw -16(%rax,%rbx), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal -16(%rax,%rbx), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq -16(%rax,%rbx), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw -16(%eax,%ebx,2), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal -16(%eax,%ebx,2), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq -16(%eax,%ebx,2), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw -16(%rax,%rbx,2), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal -16(%rax,%rbx,2), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq -16(%rax,%rbx,2), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw 1024, %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal 1024, %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq 1024, %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw 1024(%eax), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal 1024(%eax), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq 1024(%eax), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw 1024(%rax), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal 1024(%rax), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq 1024(%rax), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw 1024(,%ebx), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal 1024(,%ebx), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq 1024(,%ebx), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw 1024(,%rbx), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal 1024(,%rbx), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq 1024(,%rbx), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw 1024(,%ebx), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal 1024(,%ebx), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq 1024(,%ebx), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw 1024(,%rbx), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal 1024(,%rbx), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq 1024(,%rbx), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw 1024(,%ebx,2), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal 1024(,%ebx,2), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq 1024(,%ebx,2), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw 1024(,%rbx,2), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal 1024(,%rbx,2), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq 1024(,%rbx,2), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw 1024(%eax,%ebx), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal 1024(%eax,%ebx), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq 1024(%eax,%ebx), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw 1024(%rax,%rbx), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal 1024(%rax,%rbx), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq 1024(%rax,%rbx), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw 1024(%eax,%ebx), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal 1024(%eax,%ebx), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq 1024(%eax,%ebx), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw 1024(%rax,%rbx), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal 1024(%rax,%rbx), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq 1024(%rax,%rbx), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw 1024(%eax,%ebx,2), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal 1024(%eax,%ebx,2), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq 1024(%eax,%ebx,2), %rcx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaw 1024(%rax,%rbx,2), %cx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leal 1024(%rax,%rbx,2), %ecx +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - leaq 1024(%rax,%rbx,2), %rcx diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-lzcnt.s b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-lzcnt.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-lzcnt.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-lzcnt.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -instruction-tables < %s | FileCheck %s lzcntw %cx, %cx lzcntw (%rax), %cx @@ -19,32 +19,47 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 3 1.00 lzcntw %cx, %cx -# CHECK-NEXT: 2 8 1.00 * lzcntw (%rax), %cx -# CHECK-NEXT: 1 3 1.00 lzcntl %eax, %ecx -# CHECK-NEXT: 2 8 1.00 * lzcntl (%rax), %ecx -# CHECK-NEXT: 1 3 1.00 lzcntq %rax, %rcx -# CHECK-NEXT: 2 8 1.00 * lzcntq (%rax), %rcx +# CHECK-NEXT: 1 3 3.00 lzcntw %cx, %cx +# CHECK-NEXT: 1 6 3.00 * lzcntw (%rax), %cx +# CHECK-NEXT: 1 3 3.00 lzcntl %eax, %ecx +# CHECK-NEXT: 1 6 3.00 * lzcntl (%rax), %ecx +# CHECK-NEXT: 1 3 3.00 lzcntq %rax, %rcx +# CHECK-NEXT: 1 6 3.00 * lzcntq (%rax), %rcx # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - 6.00 - - 1.50 1.50 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: 18.00 - - 3.00 - - - - - - - - - - - - 6.00 1.50 1.50 1.50 1.50 - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - 1.00 - - - - lzcntw %cx, %cx -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 lzcntw (%rax), %cx -# CHECK-NEXT: - - - 1.00 - - - - lzcntl %eax, %ecx -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 lzcntl (%rax), %ecx -# CHECK-NEXT: - - - 1.00 - - - - lzcntq %rax, %rcx -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 lzcntq (%rax), %rcx +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: 3.00 - - - - - - - - - - - - - - - 1.00 - - - - - - lzcntw %cx, %cx +# CHECK-NEXT: 3.00 - - 1.00 - - - - - - - - - - - - 1.00 0.50 0.50 0.50 0.50 - - lzcntw (%rax), %cx +# CHECK-NEXT: 3.00 - - - - - - - - - - - - - - - 1.00 - - - - - - lzcntl %eax, %ecx +# CHECK-NEXT: 3.00 - - 1.00 - - - - - - - - - - - - 1.00 0.50 0.50 0.50 0.50 - - lzcntl (%rax), %ecx +# CHECK-NEXT: 3.00 - - - - - - - - - - - - - - - 1.00 - - - - - - lzcntq %rax, %rcx +# CHECK-NEXT: 3.00 - - 1.00 - - - - - - - - - - - - 1.00 0.50 0.50 0.50 0.50 - - lzcntq (%rax), %rcx diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-mmx.s b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-mmx.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-mmx.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-mmx.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -instruction-tables < %s | FileCheck %s emms @@ -164,230 +164,245 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 31 31 10.33 * * U emms -# CHECK-NEXT: 1 1 1.00 movd %eax, %mm2 -# CHECK-NEXT: 1 5 0.50 * movd (%rax), %mm2 -# CHECK-NEXT: 1 2 1.00 movd %mm0, %ecx -# CHECK-NEXT: 1 1 1.00 * U movd %mm0, (%rax) -# CHECK-NEXT: 1 1 1.00 movq %rax, %mm2 -# CHECK-NEXT: 1 5 0.50 * movq (%rax), %mm2 -# CHECK-NEXT: 1 2 1.00 movq %mm0, %rcx -# CHECK-NEXT: 1 1 1.00 * movq %mm0, (%rax) -# CHECK-NEXT: 1 1 1.00 packsswb %mm0, %mm2 -# CHECK-NEXT: 2 6 1.00 * packsswb (%rax), %mm2 -# CHECK-NEXT: 1 1 1.00 packssdw %mm0, %mm2 -# CHECK-NEXT: 2 6 1.00 * packssdw (%rax), %mm2 -# CHECK-NEXT: 1 1 1.00 packuswb %mm0, %mm2 -# CHECK-NEXT: 2 6 1.00 * packuswb (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 paddb %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * paddb (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 paddd %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * paddd (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 paddsb %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * paddsb (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 paddsw %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * paddsw (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 paddusb %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * paddusb (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 paddusw %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * paddusw (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 paddw %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * paddw (%rax), %mm2 -# CHECK-NEXT: 1 1 0.33 pand %mm0, %mm2 -# CHECK-NEXT: 2 6 0.50 * pand (%rax), %mm2 -# CHECK-NEXT: 1 1 0.33 pandn %mm0, %mm2 -# CHECK-NEXT: 2 6 0.50 * pandn (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pcmpeqb %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * pcmpeqb (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pcmpeqd %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * pcmpeqd (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pcmpeqw %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * pcmpeqw (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pcmpgtb %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * pcmpgtb (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pcmpgtd %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * pcmpgtd (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pcmpgtw %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * pcmpgtw (%rax), %mm2 -# CHECK-NEXT: 1 5 1.00 pmaddwd %mm0, %mm2 -# CHECK-NEXT: 2 10 1.00 * pmaddwd (%rax), %mm2 -# CHECK-NEXT: 1 5 1.00 pmulhw %mm0, %mm2 -# CHECK-NEXT: 2 10 1.00 * pmulhw (%rax), %mm2 -# CHECK-NEXT: 1 5 1.00 pmullw %mm0, %mm2 -# CHECK-NEXT: 2 10 1.00 * pmullw (%rax), %mm2 -# CHECK-NEXT: 1 1 0.33 por %mm0, %mm2 -# CHECK-NEXT: 2 6 0.50 * por (%rax), %mm2 -# CHECK-NEXT: 1 1 1.00 pslld $1, %mm2 -# CHECK-NEXT: 1 1 1.00 pslld %mm0, %mm2 -# CHECK-NEXT: 2 6 1.00 * pslld (%rax), %mm2 -# CHECK-NEXT: 1 1 1.00 psllq $1, %mm2 -# CHECK-NEXT: 1 1 1.00 psllq %mm0, %mm2 -# CHECK-NEXT: 2 6 1.00 * psllq (%rax), %mm2 -# CHECK-NEXT: 1 1 1.00 psllw $1, %mm2 -# CHECK-NEXT: 1 1 1.00 psllw %mm0, %mm2 -# CHECK-NEXT: 2 6 1.00 * psllw (%rax), %mm2 -# CHECK-NEXT: 1 1 1.00 psrad $1, %mm2 -# CHECK-NEXT: 1 1 1.00 psrad %mm0, %mm2 -# CHECK-NEXT: 2 6 1.00 * psrad (%rax), %mm2 -# CHECK-NEXT: 1 1 1.00 psraw $1, %mm2 -# CHECK-NEXT: 1 1 1.00 psraw %mm0, %mm2 -# CHECK-NEXT: 2 6 1.00 * psraw (%rax), %mm2 -# CHECK-NEXT: 1 1 1.00 psrld $1, %mm2 -# CHECK-NEXT: 1 1 1.00 psrld %mm0, %mm2 -# CHECK-NEXT: 2 6 1.00 * psrld (%rax), %mm2 -# CHECK-NEXT: 1 1 1.00 psrlq $1, %mm2 -# CHECK-NEXT: 1 1 1.00 psrlq %mm0, %mm2 -# CHECK-NEXT: 2 6 1.00 * psrlq (%rax), %mm2 -# CHECK-NEXT: 1 1 1.00 psrlw $1, %mm2 -# CHECK-NEXT: 1 1 1.00 psrlw %mm0, %mm2 -# CHECK-NEXT: 2 6 1.00 * psrlw (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 psubb %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * psubb (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 psubd %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * psubd (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 psubsb %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * psubsb (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 psubsw %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * psubsw (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 psubusb %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * psubusb (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 psubusw %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * psubusw (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 psubw %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * psubw (%rax), %mm2 -# CHECK-NEXT: 1 1 1.00 punpckhbw %mm0, %mm2 -# CHECK-NEXT: 2 6 1.00 * punpckhbw (%rax), %mm2 -# CHECK-NEXT: 1 1 1.00 punpckhdq %mm0, %mm2 -# CHECK-NEXT: 2 6 1.00 * punpckhdq (%rax), %mm2 -# CHECK-NEXT: 1 1 1.00 punpckhwd %mm0, %mm2 -# CHECK-NEXT: 2 6 1.00 * punpckhwd (%rax), %mm2 -# CHECK-NEXT: 1 1 1.00 punpcklbw %mm0, %mm2 -# CHECK-NEXT: 2 6 1.00 * punpcklbw (%rax), %mm2 -# CHECK-NEXT: 1 1 1.00 punpckldq %mm0, %mm2 -# CHECK-NEXT: 2 6 1.00 * punpckldq (%rax), %mm2 -# CHECK-NEXT: 1 1 1.00 punpcklwd %mm0, %mm2 -# CHECK-NEXT: 2 6 1.00 * punpcklwd (%rax), %mm2 -# CHECK-NEXT: 1 1 0.33 pxor %mm0, %mm2 -# CHECK-NEXT: 2 6 0.50 * pxor (%rax), %mm2 +# CHECK-NEXT: 1 2 1.00 * * U emms +# CHECK-NEXT: 2 6 3.00 movd %eax, %mm2 +# CHECK-NEXT: 1 3 0.50 * movd (%rax), %mm2 +# CHECK-NEXT: 1 6 2.00 movd %mm0, %ecx +# CHECK-NEXT: 1 2 1.00 * U movd %mm0, (%rax) +# CHECK-NEXT: 2 6 3.00 movq %rax, %mm2 +# CHECK-NEXT: 1 3 0.50 * movq (%rax), %mm2 +# CHECK-NEXT: 1 6 2.00 movq %mm0, %rcx +# CHECK-NEXT: 1 2 1.00 * movq %mm0, (%rax) +# CHECK-NEXT: 1 2 2.00 packsswb %mm0, %mm2 +# CHECK-NEXT: 1 4 2.50 * packsswb (%rax), %mm2 +# CHECK-NEXT: 1 2 2.00 packssdw %mm0, %mm2 +# CHECK-NEXT: 1 4 2.50 * packssdw (%rax), %mm2 +# CHECK-NEXT: 1 2 2.00 packuswb %mm0, %mm2 +# CHECK-NEXT: 1 4 2.50 * packuswb (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 paddb %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * paddb (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 paddd %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * paddd (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 paddsb %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * paddsb (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 paddsw %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * paddsw (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 paddusb %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * paddusb (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 paddusw %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * paddusw (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 paddw %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * paddw (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 pand %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * pand (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 pandn %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * pandn (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 pcmpeqb %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * pcmpeqb (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 pcmpeqd %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * pcmpeqd (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 pcmpeqw %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * pcmpeqw (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 pcmpgtb %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * pcmpgtb (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 pcmpgtd %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * pcmpgtd (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 pcmpgtw %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * pcmpgtw (%rax), %mm2 +# CHECK-NEXT: 1 3 1.50 pmaddwd %mm0, %mm2 +# CHECK-NEXT: 1 5 2.00 * pmaddwd (%rax), %mm2 +# CHECK-NEXT: 1 3 1.50 pmulhw %mm0, %mm2 +# CHECK-NEXT: 1 5 2.00 * pmulhw (%rax), %mm2 +# CHECK-NEXT: 1 3 1.50 pmullw %mm0, %mm2 +# CHECK-NEXT: 1 5 2.00 * pmullw (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 por %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * por (%rax), %mm2 +# CHECK-NEXT: 1 2 2.00 pslld $1, %mm2 +# CHECK-NEXT: 1 2 1.50 pslld %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * pslld (%rax), %mm2 +# CHECK-NEXT: 1 2 2.00 psllq $1, %mm2 +# CHECK-NEXT: 1 2 1.50 psllq %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * psllq (%rax), %mm2 +# CHECK-NEXT: 1 2 2.00 psllw $1, %mm2 +# CHECK-NEXT: 1 2 1.50 psllw %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * psllw (%rax), %mm2 +# CHECK-NEXT: 1 2 2.00 psrad $1, %mm2 +# CHECK-NEXT: 1 2 1.50 psrad %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * psrad (%rax), %mm2 +# CHECK-NEXT: 1 2 2.00 psraw $1, %mm2 +# CHECK-NEXT: 1 2 1.50 psraw %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * psraw (%rax), %mm2 +# CHECK-NEXT: 1 2 2.00 psrld $1, %mm2 +# CHECK-NEXT: 1 2 1.50 psrld %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * psrld (%rax), %mm2 +# CHECK-NEXT: 1 2 2.00 psrlq $1, %mm2 +# CHECK-NEXT: 1 2 1.50 psrlq %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * psrlq (%rax), %mm2 +# CHECK-NEXT: 1 2 2.00 psrlw $1, %mm2 +# CHECK-NEXT: 1 2 1.50 psrlw %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * psrlw (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 psubb %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * psubb (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 psubd %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * psubd (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 psubsb %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * psubsb (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 psubsw %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * psubsw (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 psubusb %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * psubusb (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 psubusw %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * psubusw (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 psubw %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * psubw (%rax), %mm2 +# CHECK-NEXT: 1 2 2.00 punpckhbw %mm0, %mm2 +# CHECK-NEXT: 1 4 2.50 * punpckhbw (%rax), %mm2 +# CHECK-NEXT: 1 2 2.00 punpckhdq %mm0, %mm2 +# CHECK-NEXT: 1 4 2.50 * punpckhdq (%rax), %mm2 +# CHECK-NEXT: 1 2 2.00 punpckhwd %mm0, %mm2 +# CHECK-NEXT: 1 4 2.50 * punpckhwd (%rax), %mm2 +# CHECK-NEXT: 1 2 2.00 punpcklbw %mm0, %mm2 +# CHECK-NEXT: 1 4 2.50 * punpcklbw (%rax), %mm2 +# CHECK-NEXT: 1 2 2.00 punpckldq %mm0, %mm2 +# CHECK-NEXT: 1 4 2.50 * punpckldq (%rax), %mm2 +# CHECK-NEXT: 1 2 2.00 punpcklwd %mm0, %mm2 +# CHECK-NEXT: 1 4 2.50 * punpcklwd (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 pxor %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * pxor (%rax), %mm2 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - 21.00 53.00 2.00 57.00 24.00 24.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - - - - 190.67 9.67 186.67 51.67 49.67 3.67 - - - - 24.00 24.00 23.00 23.00 1.00 1.00 # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - 10.33 10.33 - 10.33 - - emms -# CHECK-NEXT: - - - - - 1.00 - - movd %eax, %mm2 -# CHECK-NEXT: - - - - - - 0.50 0.50 movd (%rax), %mm2 -# CHECK-NEXT: - - 1.00 - - - - - movd %mm0, %ecx -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movd %mm0, (%rax) -# CHECK-NEXT: - - - - - 1.00 - - movq %rax, %mm2 -# CHECK-NEXT: - - - - - - 0.50 0.50 movq (%rax), %mm2 -# CHECK-NEXT: - - 1.00 - - - - - movq %mm0, %rcx -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movq %mm0, (%rax) -# CHECK-NEXT: - - - - - 1.00 - - packsswb %mm0, %mm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 packsswb (%rax), %mm2 -# CHECK-NEXT: - - - - - 1.00 - - packssdw %mm0, %mm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 packssdw (%rax), %mm2 -# CHECK-NEXT: - - - - - 1.00 - - packuswb %mm0, %mm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 packuswb (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - paddb %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 paddb (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - paddd %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 paddd (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - paddsb %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 paddsb (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - paddsw %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 paddsw (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - paddusb %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 paddusb (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - paddusw %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 paddusw (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - paddw %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 paddw (%rax), %mm2 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - pand %mm0, %mm2 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 pand (%rax), %mm2 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - pandn %mm0, %mm2 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 pandn (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pcmpeqb %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pcmpeqb (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pcmpeqd %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pcmpeqd (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pcmpeqw %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pcmpeqw (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pcmpgtb %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pcmpgtb (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pcmpgtd %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pcmpgtd (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pcmpgtw %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pcmpgtw (%rax), %mm2 -# CHECK-NEXT: - - 1.00 - - - - - pmaddwd %mm0, %mm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmaddwd (%rax), %mm2 -# CHECK-NEXT: - - 1.00 - - - - - pmulhw %mm0, %mm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmulhw (%rax), %mm2 -# CHECK-NEXT: - - 1.00 - - - - - pmullw %mm0, %mm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmullw (%rax), %mm2 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - por %mm0, %mm2 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 por (%rax), %mm2 -# CHECK-NEXT: - - - - - 1.00 - - pslld $1, %mm2 -# CHECK-NEXT: - - - - - 1.00 - - pslld %mm0, %mm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 pslld (%rax), %mm2 -# CHECK-NEXT: - - - - - 1.00 - - psllq $1, %mm2 -# CHECK-NEXT: - - - - - 1.00 - - psllq %mm0, %mm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 psllq (%rax), %mm2 -# CHECK-NEXT: - - - - - 1.00 - - psllw $1, %mm2 -# CHECK-NEXT: - - - - - 1.00 - - psllw %mm0, %mm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 psllw (%rax), %mm2 -# CHECK-NEXT: - - - - - 1.00 - - psrad $1, %mm2 -# CHECK-NEXT: - - - - - 1.00 - - psrad %mm0, %mm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 psrad (%rax), %mm2 -# CHECK-NEXT: - - - - - 1.00 - - psraw $1, %mm2 -# CHECK-NEXT: - - - - - 1.00 - - psraw %mm0, %mm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 psraw (%rax), %mm2 -# CHECK-NEXT: - - - - - 1.00 - - psrld $1, %mm2 -# CHECK-NEXT: - - - - - 1.00 - - psrld %mm0, %mm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 psrld (%rax), %mm2 -# CHECK-NEXT: - - - - - 1.00 - - psrlq $1, %mm2 -# CHECK-NEXT: - - - - - 1.00 - - psrlq %mm0, %mm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 psrlq (%rax), %mm2 -# CHECK-NEXT: - - - - - 1.00 - - psrlw $1, %mm2 -# CHECK-NEXT: - - - - - 1.00 - - psrlw %mm0, %mm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 psrlw (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - psubb %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 psubb (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - psubd %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 psubd (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - psubsb %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 psubsb (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - psubsw %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 psubsw (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - psubusb %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 psubusb (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - psubusw %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 psubusw (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - psubw %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 psubw (%rax), %mm2 -# CHECK-NEXT: - - - - - 1.00 - - punpckhbw %mm0, %mm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 punpckhbw (%rax), %mm2 -# CHECK-NEXT: - - - - - 1.00 - - punpckhdq %mm0, %mm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 punpckhdq (%rax), %mm2 -# CHECK-NEXT: - - - - - 1.00 - - punpckhwd %mm0, %mm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 punpckhwd (%rax), %mm2 -# CHECK-NEXT: - - - - - 1.00 - - punpcklbw %mm0, %mm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 punpcklbw (%rax), %mm2 -# CHECK-NEXT: - - - - - 1.00 - - punpckldq %mm0, %mm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 punpckldq (%rax), %mm2 -# CHECK-NEXT: - - - - - 1.00 - - punpcklwd %mm0, %mm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 punpcklwd (%rax), %mm2 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - pxor %mm0, %mm2 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 pxor (%rax), %mm2 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - 1.00 1.00 1.00 0.33 0.33 0.33 - - - - - - - - - - emms +# CHECK-NEXT: - - - - - - - 3.00 3.00 3.00 0.33 0.33 0.33 - - - - - - - - - - movd %eax, %mm2 +# CHECK-NEXT: - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 - - movd (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - - 1.00 - - - - - - - - - - - - movd %mm0, %ecx +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 0.50 0.50 - - 0.50 0.50 movd %mm0, (%rax) +# CHECK-NEXT: - - - - - - - 3.00 3.00 3.00 0.33 0.33 0.33 - - - - - - - - - - movq %rax, %mm2 +# CHECK-NEXT: - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 - - movq (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - - 1.00 - - - - - - - - - - - - movq %mm0, %rcx +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 0.50 0.50 - - 0.50 0.50 movq %mm0, (%rax) +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - packsswb %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - packsswb (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - packssdw %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - packssdw (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - packuswb %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - packuswb (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - paddb %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - paddb (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - paddd %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - paddd (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - paddsb %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - paddsb (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - paddsw %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - paddsw (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - paddusb %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - paddusb (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - paddusw %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - paddusw (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - paddw %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - paddw (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - pand %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pand (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - pandn %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pandn (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - pcmpeqb %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pcmpeqb (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - pcmpeqd %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pcmpeqd (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - pcmpeqw %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pcmpeqw (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - pcmpgtb %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pcmpgtb (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - pcmpgtd %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pcmpgtd (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - pcmpgtw %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pcmpgtw (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - pmaddwd %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pmaddwd (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - pmulhw %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pmulhw (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - pmullw %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pmullw (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - por %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - por (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - pslld $1, %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - pslld %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pslld (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - psllq $1, %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - psllq %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psllq (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - psllw $1, %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - psllw %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psllw (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - psrad $1, %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - psrad %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psrad (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - psraw $1, %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - psraw %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psraw (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - psrld $1, %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - psrld %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psrld (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - psrlq $1, %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - psrlq %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psrlq (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - psrlw $1, %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - psrlw %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psrlw (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - psubb %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psubb (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - psubd %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psubd (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - psubsb %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psubsb (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - psubsw %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psubsw (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - psubusb %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psubusb (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - psubusw %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psubusw (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - psubw %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psubw (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - punpckhbw %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - punpckhbw (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - punpckhdq %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - punpckhdq (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - punpckhwd %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - punpckhwd (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - punpcklbw %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - punpcklbw (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - punpckldq %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - punpckldq (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - punpcklwd %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - punpcklwd (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - pxor %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pxor (%rax), %mm2 diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-popcnt.s b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-popcnt.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-popcnt.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-popcnt.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -instruction-tables < %s | FileCheck %s popcntw %cx, %cx popcntw (%rax), %cx @@ -19,32 +19,47 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 3 1.00 popcntw %cx, %cx -# CHECK-NEXT: 2 9 1.00 * popcntw (%rax), %cx -# CHECK-NEXT: 1 3 1.00 popcntl %eax, %ecx -# CHECK-NEXT: 2 9 1.00 * popcntl (%rax), %ecx -# CHECK-NEXT: 1 3 1.00 popcntq %rax, %rcx -# CHECK-NEXT: 2 9 1.00 * popcntq (%rax), %rcx +# CHECK-NEXT: 1 3 3.00 popcntw %cx, %cx +# CHECK-NEXT: 1 6 3.00 * popcntw (%rax), %cx +# CHECK-NEXT: 1 3 3.00 popcntl %eax, %ecx +# CHECK-NEXT: 1 6 3.00 * popcntl (%rax), %ecx +# CHECK-NEXT: 1 3 3.00 popcntq %rax, %rcx +# CHECK-NEXT: 1 6 3.00 * popcntq (%rax), %rcx # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - 6.00 - - 1.50 1.50 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: 18.00 - - 3.00 - - - - - - - - - - - - 6.00 1.50 1.50 1.50 1.50 - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - 1.00 - - - - popcntw %cx, %cx -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 popcntw (%rax), %cx -# CHECK-NEXT: - - - 1.00 - - - - popcntl %eax, %ecx -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 popcntl (%rax), %ecx -# CHECK-NEXT: - - - 1.00 - - - - popcntq %rax, %rcx -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 popcntq (%rax), %rcx +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: 3.00 - - - - - - - - - - - - - - - 1.00 - - - - - - popcntw %cx, %cx +# CHECK-NEXT: 3.00 - - 1.00 - - - - - - - - - - - - 1.00 0.50 0.50 0.50 0.50 - - popcntw (%rax), %cx +# CHECK-NEXT: 3.00 - - - - - - - - - - - - - - - 1.00 - - - - - - popcntl %eax, %ecx +# CHECK-NEXT: 3.00 - - 1.00 - - - - - - - - - - - - 1.00 0.50 0.50 0.50 0.50 - - popcntl (%rax), %ecx +# CHECK-NEXT: 3.00 - - - - - - - - - - - - - - - 1.00 - - - - - - popcntq %rax, %rcx +# CHECK-NEXT: 3.00 - - 1.00 - - - - - - - - - - - - 1.00 0.50 0.50 0.50 0.50 - - popcntq (%rax), %rcx diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-prefetchw.s b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-prefetchw.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-prefetchw.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-prefetchw.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -instruction-tables < %s | FileCheck %s prefetch (%rax) prefetchw (%rax) @@ -13,24 +13,39 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 5 0.50 * * prefetch (%rax) -# CHECK-NEXT: 1 5 0.50 * * prefetchw (%rax) +# CHECK-NEXT: 1 4 0.50 * * prefetch (%rax) +# CHECK-NEXT: 1 4 0.50 * * prefetchw (%rax) # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - - - - 1.00 1.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - 0.67 0.67 0.67 - - - - - - - - - - 0.67 0.67 0.67 1.00 1.00 1.00 1.00 - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - - - 0.50 0.50 prefetch (%rax) -# CHECK-NEXT: - - - - - - 0.50 0.50 prefetchw (%rax) +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - prefetch (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - prefetchw (%rax) diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse1.s b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse1.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse1.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse1.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -instruction-tables < %s | FileCheck %s addps %xmm0, %xmm2 addps (%rax), %xmm2 @@ -194,268 +194,283 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 3 1.00 addps %xmm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * addps (%rax), %xmm2 -# CHECK-NEXT: 1 3 1.00 addss %xmm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * addss (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 andnps %xmm0, %xmm2 -# CHECK-NEXT: 2 7 1.00 * andnps (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 andps %xmm0, %xmm2 -# CHECK-NEXT: 2 7 1.00 * andps (%rax), %xmm2 -# CHECK-NEXT: 1 3 1.00 cmpeqps %xmm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * cmpeqps (%rax), %xmm2 -# CHECK-NEXT: 1 3 1.00 cmpeqss %xmm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * cmpeqss (%rax), %xmm2 -# CHECK-NEXT: 2 2 1.00 comiss %xmm0, %xmm1 -# CHECK-NEXT: 3 8 1.00 * comiss (%rax), %xmm1 -# CHECK-NEXT: 1 3 1.00 cvtpi2ps %mm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * cvtpi2ps (%rax), %xmm2 -# CHECK-NEXT: 1 3 1.00 cvtps2pi %xmm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * cvtps2pi (%rax), %mm2 -# CHECK-NEXT: 3 5 2.00 cvtsi2ss %ecx, %xmm2 -# CHECK-NEXT: 3 5 2.00 cvtsi2ss %rcx, %xmm2 -# CHECK-NEXT: 3 10 1.00 * cvtsi2ssl (%rax), %xmm2 -# CHECK-NEXT: 3 10 1.00 * cvtsi2ssl (%rax), %xmm2 -# CHECK-NEXT: 2 5 1.00 cvtss2si %xmm0, %ecx -# CHECK-NEXT: 2 5 1.00 cvtss2si %xmm0, %rcx -# CHECK-NEXT: 3 9 1.00 * cvtss2si (%rax), %ecx -# CHECK-NEXT: 3 9 1.00 * cvtss2si (%rax), %rcx -# CHECK-NEXT: 1 3 1.00 cvttps2pi %xmm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * cvttps2pi (%rax), %mm2 -# CHECK-NEXT: 2 5 1.00 cvttss2si %xmm0, %ecx -# CHECK-NEXT: 2 5 1.00 cvttss2si %xmm0, %rcx -# CHECK-NEXT: 3 9 1.00 * cvttss2si (%rax), %ecx -# CHECK-NEXT: 3 9 1.00 * cvttss2si (%rax), %rcx -# CHECK-NEXT: 1 14 14.00 divps %xmm0, %xmm2 -# CHECK-NEXT: 2 20 14.00 * divps (%rax), %xmm2 -# CHECK-NEXT: 1 14 14.00 divss %xmm0, %xmm2 -# CHECK-NEXT: 2 20 14.00 * divss (%rax), %xmm2 -# CHECK-NEXT: 4 5 1.00 * U ldmxcsr (%rax) -# CHECK-NEXT: 1 1 1.00 * * U maskmovq %mm0, %mm1 -# CHECK-NEXT: 1 3 1.00 maxps %xmm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * maxps (%rax), %xmm2 -# CHECK-NEXT: 1 3 1.00 maxss %xmm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * maxss (%rax), %xmm2 -# CHECK-NEXT: 1 3 1.00 minps %xmm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * minps (%rax), %xmm2 -# CHECK-NEXT: 1 3 1.00 minss %xmm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * minss (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 movaps %xmm0, %xmm2 -# CHECK-NEXT: 1 1 1.00 * movaps %xmm0, (%rax) -# CHECK-NEXT: 1 6 0.50 * movaps (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 movhlps %xmm0, %xmm2 -# CHECK-NEXT: 1 1 1.00 movlhps %xmm0, %xmm2 -# CHECK-NEXT: 1 1 1.00 * movhps %xmm0, (%rax) -# CHECK-NEXT: 2 7 1.00 * movhps (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 * movlps %xmm0, (%rax) -# CHECK-NEXT: 2 7 1.00 * movlps (%rax), %xmm2 -# CHECK-NEXT: 1 2 1.00 movmskps %xmm0, %ecx -# CHECK-NEXT: 1 1 1.00 * movntps %xmm0, (%rax) -# CHECK-NEXT: 1 1 1.00 * * U movntq %mm0, (%rax) -# CHECK-NEXT: 1 1 1.00 movss %xmm0, %xmm2 -# CHECK-NEXT: 1 1 1.00 * movss %xmm0, (%rax) -# CHECK-NEXT: 1 6 0.50 * movss (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 movups %xmm0, %xmm2 -# CHECK-NEXT: 1 1 1.00 * movups %xmm0, (%rax) -# CHECK-NEXT: 1 6 0.50 * movups (%rax), %xmm2 -# CHECK-NEXT: 1 5 1.00 mulps %xmm0, %xmm2 -# CHECK-NEXT: 2 11 1.00 * mulps (%rax), %xmm2 -# CHECK-NEXT: 1 5 1.00 mulss %xmm0, %xmm2 -# CHECK-NEXT: 2 11 1.00 * mulss (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 orps %xmm0, %xmm2 -# CHECK-NEXT: 2 7 1.00 * orps (%rax), %xmm2 -# CHECK-NEXT: 1 3 1.00 pavgb %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * pavgb (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pavgw %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * pavgw (%rax), %mm2 -# CHECK-NEXT: 2 3 1.00 pextrw $1, %mm0, %ecx -# CHECK-NEXT: 2 2 1.00 pinsrw $1, %eax, %mm2 -# CHECK-NEXT: 2 7 0.50 * pinsrw $1, (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pmaxsw %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * pmaxsw (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pmaxub %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * pmaxub (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pminsw %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * pminsw (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 pminub %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * pminub (%rax), %mm2 -# CHECK-NEXT: 1 1 1.00 pmovmskb %mm0, %ecx -# CHECK-NEXT: 1 5 1.00 pmulhuw %mm0, %mm2 -# CHECK-NEXT: 2 10 1.00 * pmulhuw (%rax), %mm2 -# CHECK-NEXT: 1 5 0.50 * * prefetcht0 (%rax) -# CHECK-NEXT: 1 5 0.50 * * prefetcht1 (%rax) -# CHECK-NEXT: 1 5 0.50 * * prefetcht2 (%rax) -# CHECK-NEXT: 1 5 0.50 * * prefetchnta (%rax) -# CHECK-NEXT: 1 5 1.00 psadbw %mm0, %mm2 -# CHECK-NEXT: 2 10 1.00 * psadbw (%rax), %mm2 -# CHECK-NEXT: 1 1 1.00 pshufw $1, %mm0, %mm2 -# CHECK-NEXT: 2 6 1.00 * pshufw $1, (%rax), %mm2 -# CHECK-NEXT: 1 5 1.00 rcpps %xmm0, %xmm2 -# CHECK-NEXT: 2 11 1.00 * rcpps (%rax), %xmm2 -# CHECK-NEXT: 1 5 1.00 rcpss %xmm0, %xmm2 -# CHECK-NEXT: 2 11 1.00 * rcpss (%rax), %xmm2 -# CHECK-NEXT: 1 5 1.00 rsqrtps %xmm0, %xmm2 -# CHECK-NEXT: 2 11 1.00 * rsqrtps (%rax), %xmm2 -# CHECK-NEXT: 1 5 1.00 rsqrtss %xmm0, %xmm2 -# CHECK-NEXT: 2 11 1.00 * rsqrtss (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 * * U sfence -# CHECK-NEXT: 1 1 1.00 shufps $1, %xmm0, %xmm2 -# CHECK-NEXT: 2 7 1.00 * shufps $1, (%rax), %xmm2 -# CHECK-NEXT: 1 14 14.00 sqrtps %xmm0, %xmm2 -# CHECK-NEXT: 2 20 14.00 * sqrtps (%rax), %xmm2 -# CHECK-NEXT: 1 14 14.00 sqrtss %xmm0, %xmm2 -# CHECK-NEXT: 2 20 14.00 * sqrtss (%rax), %xmm2 -# CHECK-NEXT: 4 5 1.00 * U stmxcsr (%rax) -# CHECK-NEXT: 1 3 1.00 subps %xmm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * subps (%rax), %xmm2 -# CHECK-NEXT: 1 3 1.00 subss %xmm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * subss (%rax), %xmm2 -# CHECK-NEXT: 2 2 1.00 ucomiss %xmm0, %xmm1 -# CHECK-NEXT: 3 8 1.00 * ucomiss (%rax), %xmm1 -# CHECK-NEXT: 1 1 1.00 unpckhps %xmm0, %xmm2 -# CHECK-NEXT: 2 7 1.00 * unpckhps (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 unpcklps %xmm0, %xmm2 -# CHECK-NEXT: 2 7 1.00 * unpcklps (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 xorps %xmm0, %xmm2 -# CHECK-NEXT: 2 7 1.00 * xorps (%rax), %xmm2 +# CHECK-NEXT: 1 4 2.00 addps %xmm0, %xmm2 +# CHECK-NEXT: 1 6 2.50 * addps (%rax), %xmm2 +# CHECK-NEXT: 1 4 2.00 addss %xmm0, %xmm2 +# CHECK-NEXT: 1 6 2.50 * addss (%rax), %xmm2 +# CHECK-NEXT: 1 2 2.00 andnps %xmm0, %xmm2 +# CHECK-NEXT: 1 4 2.50 * andnps (%rax), %xmm2 +# CHECK-NEXT: 1 2 2.00 andps %xmm0, %xmm2 +# CHECK-NEXT: 1 4 2.50 * andps (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 cmpeqps %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * cmpeqps (%rax), %xmm2 +# CHECK-NEXT: 1 3 3.00 cmpeqss %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.50 * cmpeqss (%rax), %xmm2 +# CHECK-NEXT: 1 1 2.50 comiss %xmm0, %xmm1 +# CHECK-NEXT: 1 3 3.00 * comiss (%rax), %xmm1 +# CHECK-NEXT: 1 5 2.00 cvtpi2ps %mm0, %xmm2 +# CHECK-NEXT: 1 7 3.00 * cvtpi2ps (%rax), %xmm2 +# CHECK-NEXT: 1 5 2.50 cvtps2pi %xmm0, %mm2 +# CHECK-NEXT: 1 7 3.00 * cvtps2pi (%rax), %mm2 +# CHECK-NEXT: 3 3 3.00 cvtsi2ss %ecx, %xmm2 +# CHECK-NEXT: 3 3 3.00 cvtsi2ss %rcx, %xmm2 +# CHECK-NEXT: 3 5 4.00 * cvtsi2ssl (%rax), %xmm2 +# CHECK-NEXT: 3 5 4.00 * cvtsi2ssl (%rax), %xmm2 +# CHECK-NEXT: 2 8 2.50 cvtss2si %xmm0, %ecx +# CHECK-NEXT: 2 8 2.50 cvtss2si %xmm0, %rcx +# CHECK-NEXT: 2 10 3.00 * cvtss2si (%rax), %ecx +# CHECK-NEXT: 2 10 3.00 * cvtss2si (%rax), %rcx +# CHECK-NEXT: 1 5 2.50 cvttps2pi %xmm0, %mm2 +# CHECK-NEXT: 1 7 3.00 * cvttps2pi (%rax), %mm2 +# CHECK-NEXT: 2 8 2.50 cvttss2si %xmm0, %ecx +# CHECK-NEXT: 2 8 2.50 cvttss2si %xmm0, %rcx +# CHECK-NEXT: 2 10 3.00 * cvttss2si (%rax), %ecx +# CHECK-NEXT: 2 10 3.00 * cvttss2si (%rax), %rcx +# CHECK-NEXT: 1 18 15.00 divps %xmm0, %xmm2 +# CHECK-NEXT: 1 20 16.00 * divps (%rax), %xmm2 +# CHECK-NEXT: 1 16 13.00 divss %xmm0, %xmm2 +# CHECK-NEXT: 1 18 14.00 * divss (%rax), %xmm2 +# CHECK-NEXT: 12 12 10.00 * U ldmxcsr (%rax) +# CHECK-NEXT: 1 2 2.00 * * U maskmovq %mm0, %mm1 +# CHECK-NEXT: 1 3 2.50 maxps %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * maxps (%rax), %xmm2 +# CHECK-NEXT: 1 3 3.00 maxss %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.50 * maxss (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 minps %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * minps (%rax), %xmm2 +# CHECK-NEXT: 1 3 3.00 minss %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.50 * minss (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.33 movaps %xmm0, %xmm2 +# CHECK-NEXT: 2 2 1.00 * movaps %xmm0, (%rax) +# CHECK-NEXT: 1 2 0.50 * movaps (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 movhlps %xmm0, %xmm2 +# CHECK-NEXT: 1 3 2.50 movlhps %xmm0, %xmm2 +# CHECK-NEXT: 1 2 1.00 * movhps %xmm0, (%rax) +# CHECK-NEXT: 1 5 3.00 * movhps (%rax), %xmm2 +# CHECK-NEXT: 1 2 1.00 * movlps %xmm0, (%rax) +# CHECK-NEXT: 1 5 3.00 * movlps (%rax), %xmm2 +# CHECK-NEXT: 1 6 2.00 movmskps %xmm0, %ecx +# CHECK-NEXT: 2 3 1.00 * movntps %xmm0, (%rax) +# CHECK-NEXT: 2 2 1.00 * * U movntq %mm0, (%rax) +# CHECK-NEXT: 1 3 2.50 movss %xmm0, %xmm2 +# CHECK-NEXT: 1 2 1.00 * movss %xmm0, (%rax) +# CHECK-NEXT: 1 2 0.50 * movss (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.33 movups %xmm0, %xmm2 +# CHECK-NEXT: 2 2 1.00 * movups %xmm0, (%rax) +# CHECK-NEXT: 1 2 0.50 * movups (%rax), %xmm2 +# CHECK-NEXT: 1 4 2.00 mulps %xmm0, %xmm2 +# CHECK-NEXT: 1 6 2.50 * mulps (%rax), %xmm2 +# CHECK-NEXT: 1 4 2.50 mulss %xmm0, %xmm2 +# CHECK-NEXT: 1 6 3.00 * mulss (%rax), %xmm2 +# CHECK-NEXT: 1 2 2.00 orps %xmm0, %xmm2 +# CHECK-NEXT: 1 4 2.50 * orps (%rax), %xmm2 +# CHECK-NEXT: 1 2 1.50 pavgb %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * pavgb (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 pavgw %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * pavgw (%rax), %mm2 +# CHECK-NEXT: 2 7 5.00 pextrw $1, %mm0, %ecx +# CHECK-NEXT: 2 3 3.00 pinsrw $1, %eax, %mm2 +# CHECK-NEXT: 1 5 4.00 * pinsrw $1, (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 pmaxsw %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * pmaxsw (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 pmaxub %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * pmaxub (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 pminsw %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * pminsw (%rax), %mm2 +# CHECK-NEXT: 1 2 1.50 pminub %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * pminub (%rax), %mm2 +# CHECK-NEXT: 1 6 4.00 pmovmskb %mm0, %ecx +# CHECK-NEXT: 1 3 1.50 pmulhuw %mm0, %mm2 +# CHECK-NEXT: 1 5 2.00 * pmulhuw (%rax), %mm2 +# CHECK-NEXT: 1 4 0.50 * * prefetcht0 (%rax) +# CHECK-NEXT: 1 4 0.50 * * prefetcht1 (%rax) +# CHECK-NEXT: 1 4 0.50 * * prefetcht2 (%rax) +# CHECK-NEXT: 1 4 0.50 * * prefetchnta (%rax) +# CHECK-NEXT: 1 3 1.50 psadbw %mm0, %mm2 +# CHECK-NEXT: 1 5 2.00 * psadbw (%rax), %mm2 +# CHECK-NEXT: 1 2 2.00 pshufw $1, %mm0, %mm2 +# CHECK-NEXT: 1 4 2.50 * pshufw $1, (%rax), %mm2 +# CHECK-NEXT: 1 3 2.00 rcpps %xmm0, %xmm2 +# CHECK-NEXT: 1 5 2.50 * rcpps (%rax), %xmm2 +# CHECK-NEXT: 1 3 3.00 rcpss %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.50 * rcpss (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.00 rsqrtps %xmm0, %xmm2 +# CHECK-NEXT: 1 5 2.50 * rsqrtps (%rax), %xmm2 +# CHECK-NEXT: 1 3 3.00 rsqrtss %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.50 * rsqrtss (%rax), %xmm2 +# CHECK-NEXT: 6 1 0.50 * * U sfence +# CHECK-NEXT: 1 3 2.50 shufps $1, %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * shufps $1, (%rax), %xmm2 +# CHECK-NEXT: 1 21 18.00 sqrtps %xmm0, %xmm2 +# CHECK-NEXT: 1 23 19.00 * sqrtps (%rax), %xmm2 +# CHECK-NEXT: 1 19 16.00 sqrtss %xmm0, %xmm2 +# CHECK-NEXT: 1 21 17.00 * sqrtss (%rax), %xmm2 +# CHECK-NEXT: 3 12 11.00 * U stmxcsr (%rax) +# CHECK-NEXT: 1 4 2.00 subps %xmm0, %xmm2 +# CHECK-NEXT: 1 6 2.50 * subps (%rax), %xmm2 +# CHECK-NEXT: 1 4 2.00 subss %xmm0, %xmm2 +# CHECK-NEXT: 1 6 2.50 * subss (%rax), %xmm2 +# CHECK-NEXT: 1 1 2.50 ucomiss %xmm0, %xmm1 +# CHECK-NEXT: 1 3 3.00 * ucomiss (%rax), %xmm1 +# CHECK-NEXT: 1 3 2.50 unpckhps %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * unpckhps (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 unpcklps %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * unpcklps (%rax), %xmm2 +# CHECK-NEXT: 1 2 2.00 xorps %xmm0, %xmm2 +# CHECK-NEXT: 1 4 2.50 * xorps (%rax), %xmm2 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - 112.00 41.00 55.50 10.00 34.50 33.50 33.50 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - 2.33 2.33 2.33 21.00 21.00 21.00 234.17 29.67 356.17 48.17 54.17 14.67 - 2.33 2.33 2.33 35.00 35.00 29.00 29.00 6.00 6.00 # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - 1.00 - - - - addps %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 addps (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - - - - addss %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 addss (%rax), %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - andnps %xmm0, %xmm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 andnps (%rax), %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - andps %xmm0, %xmm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 andps (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - - - - cmpeqps %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cmpeqps (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - - - - cmpeqss %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cmpeqss (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 1.00 - - - - comiss %xmm0, %xmm1 -# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 comiss (%rax), %xmm1 -# CHECK-NEXT: - - - 1.00 - - - - cvtpi2ps %mm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cvtpi2ps (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - - - - cvtps2pi %xmm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cvtps2pi (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - 2.00 - - cvtsi2ss %ecx, %xmm2 -# CHECK-NEXT: - - - 1.00 - 2.00 - - cvtsi2ss %rcx, %xmm2 -# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvtsi2ssl (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvtsi2ssl (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 1.00 - - - - cvtss2si %xmm0, %ecx -# CHECK-NEXT: - - 1.00 1.00 - - - - cvtss2si %xmm0, %rcx -# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 cvtss2si (%rax), %ecx -# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 cvtss2si (%rax), %rcx -# CHECK-NEXT: - - - 1.00 - - - - cvttps2pi %xmm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cvttps2pi (%rax), %mm2 -# CHECK-NEXT: - - 1.00 1.00 - - - - cvttss2si %xmm0, %ecx -# CHECK-NEXT: - - 1.00 1.00 - - - - cvttss2si %xmm0, %rcx -# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 cvttss2si (%rax), %ecx -# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 cvttss2si (%rax), %rcx -# CHECK-NEXT: - 14.00 1.00 - - - - - divps %xmm0, %xmm2 -# CHECK-NEXT: - 14.00 1.00 - - - 0.50 0.50 divps (%rax), %xmm2 -# CHECK-NEXT: - 14.00 1.00 - - - - - divss %xmm0, %xmm2 -# CHECK-NEXT: - 14.00 1.00 - - - 0.50 0.50 divss (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - 1.00 1.00 0.50 0.50 ldmxcsr (%rax) -# CHECK-NEXT: - - - - - 1.00 - - maskmovq %mm0, %mm1 -# CHECK-NEXT: - - - 1.00 - - - - maxps %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 maxps (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - - - - maxss %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 maxss (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - - - - minps %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 minps (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - - - - minss %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 minss (%rax), %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - movaps %xmm0, %xmm2 -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movaps %xmm0, (%rax) -# CHECK-NEXT: - - - - - - 0.50 0.50 movaps (%rax), %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - movhlps %xmm0, %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - movlhps %xmm0, %xmm2 -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movhps %xmm0, (%rax) -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 movhps (%rax), %xmm2 -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movlps %xmm0, (%rax) -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 movlps (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - movmskps %xmm0, %ecx -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movntps %xmm0, (%rax) -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movntq %mm0, (%rax) -# CHECK-NEXT: - - - - - 1.00 - - movss %xmm0, %xmm2 -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movss %xmm0, (%rax) -# CHECK-NEXT: - - - - - - 0.50 0.50 movss (%rax), %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - movups %xmm0, %xmm2 -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movups %xmm0, (%rax) -# CHECK-NEXT: - - - - - - 0.50 0.50 movups (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - mulps %xmm0, %xmm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 mulps (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - mulss %xmm0, %xmm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 mulss (%rax), %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - orps %xmm0, %xmm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 orps (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - - - - pavgb %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pavgb (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pavgw %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pavgw (%rax), %mm2 -# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - pextrw $1, %mm0, %ecx -# CHECK-NEXT: - - - 0.50 - 1.50 - - pinsrw $1, %eax, %mm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pinsrw $1, (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pmaxsw %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pmaxsw (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pmaxub %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pmaxub (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pminsw %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pminsw (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pminub %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 pminub (%rax), %mm2 -# CHECK-NEXT: - - 1.00 - - - - - pmovmskb %mm0, %ecx -# CHECK-NEXT: - - 1.00 - - - - - pmulhuw %mm0, %mm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmulhuw (%rax), %mm2 -# CHECK-NEXT: - - - - - - 0.50 0.50 prefetcht0 (%rax) -# CHECK-NEXT: - - - - - - 0.50 0.50 prefetcht1 (%rax) -# CHECK-NEXT: - - - - - - 0.50 0.50 prefetcht2 (%rax) -# CHECK-NEXT: - - - - - - 0.50 0.50 prefetchnta (%rax) -# CHECK-NEXT: - - 1.00 - - - - - psadbw %mm0, %mm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 psadbw (%rax), %mm2 -# CHECK-NEXT: - - - - - 1.00 - - pshufw $1, %mm0, %mm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 pshufw $1, (%rax), %mm2 -# CHECK-NEXT: - - 1.00 - - - - - rcpps %xmm0, %xmm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 rcpps (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - rcpss %xmm0, %xmm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 rcpss (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - rsqrtps %xmm0, %xmm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 rsqrtps (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - rsqrtss %xmm0, %xmm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 rsqrtss (%rax), %xmm2 -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 sfence -# CHECK-NEXT: - - - - - 1.00 - - shufps $1, %xmm0, %xmm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 shufps $1, (%rax), %xmm2 -# CHECK-NEXT: - 14.00 1.00 - - - - - sqrtps %xmm0, %xmm2 -# CHECK-NEXT: - 14.00 1.00 - - - 0.50 0.50 sqrtps (%rax), %xmm2 -# CHECK-NEXT: - 14.00 1.00 - - - - - sqrtss %xmm0, %xmm2 -# CHECK-NEXT: - 14.00 1.00 - - - 0.50 0.50 sqrtss (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - 1.00 1.00 0.50 0.50 stmxcsr (%rax) -# CHECK-NEXT: - - - 1.00 - - - - subps %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 subps (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - - - - subss %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 subss (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 1.00 - - - - ucomiss %xmm0, %xmm1 -# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 ucomiss (%rax), %xmm1 -# CHECK-NEXT: - - - - - 1.00 - - unpckhps %xmm0, %xmm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 unpckhps (%rax), %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - unpcklps %xmm0, %xmm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 unpcklps (%rax), %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - xorps %xmm0, %xmm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 xorps (%rax), %xmm2 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - addps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - addps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - addss %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - addss (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - andnps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - andnps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - andps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - andps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - cmpeqps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - cmpeqps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - - - - - - - cmpeqss %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.50 - 3.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - cmpeqss (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - comiss %xmm0, %xmm1 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - comiss (%rax), %xmm1 +# CHECK-NEXT: - - - - - - - - 2.00 - - - 1.00 - - - - - - - - - - cvtpi2ps %mm0, %xmm2 +# CHECK-NEXT: - - - - - - - - 3.00 - - - 1.00 - - - - 0.50 0.50 0.50 0.50 - - cvtpi2ps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - cvtps2pi %xmm0, %mm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - cvtps2pi (%rax), %mm2 +# CHECK-NEXT: - - - - - - - - 3.00 - - - 1.00 - - - - - - - - - - cvtsi2ss %ecx, %xmm2 +# CHECK-NEXT: - - - - - - - - 3.00 - - - 1.00 - - - - - - - - - - cvtsi2ss %rcx, %xmm2 +# CHECK-NEXT: - - - - - - - - 4.00 - - - 1.00 - - - - 0.50 0.50 0.50 0.50 - - cvtsi2ssl (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - - 4.00 - - - 1.00 - - - - 0.50 0.50 0.50 0.50 - - cvtsi2ssl (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - cvtss2si %xmm0, %ecx +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - cvtss2si %xmm0, %rcx +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - cvtss2si (%rax), %ecx +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - cvtss2si (%rax), %rcx +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - cvttps2pi %xmm0, %mm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - cvttps2pi (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - cvttss2si %xmm0, %ecx +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - cvttss2si %xmm0, %rcx +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - cvttss2si (%rax), %ecx +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - cvttss2si (%rax), %rcx +# CHECK-NEXT: - - - - - - - - - 15.00 - 1.00 - - - - - - - - - - - divps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - - - 16.00 - 1.00 - - - - - 0.50 0.50 0.50 0.50 - - divps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - - - 13.00 - 1.00 - - - - - - - - - - - divss %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - - - 14.00 - 1.00 - - - - - 0.50 0.50 0.50 0.50 - - divss (%rax), %xmm2 +# CHECK-NEXT: - 0.33 0.33 0.33 10.00 10.00 10.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - ldmxcsr (%rax) +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - maskmovq %mm0, %mm1 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - maxps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - maxps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - - - - - - - maxss %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.50 - 3.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - maxss (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - minps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - minps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - - - - - - - minss %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.50 - 3.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - minss (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 1.33 1.33 1.33 0.33 0.33 0.33 - - - - - - - - - - movaps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 1.00 1.00 - - 1.00 1.00 movaps %xmm0, (%rax) +# CHECK-NEXT: - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 - - movaps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - movhlps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - movlhps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 0.50 0.50 - - 0.50 0.50 movhps %xmm0, (%rax) +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - movhps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 0.50 0.50 - - 0.50 0.50 movlps %xmm0, (%rax) +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - movlps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.00 - - 1.00 - - - - - - - - - - - - movmskps %xmm0, %ecx +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 1.00 1.00 - - 1.00 1.00 movntps %xmm0, (%rax) +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 0.50 0.50 - - 0.50 0.50 movntq %mm0, (%rax) +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - movss %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 0.50 0.50 - - 0.50 0.50 movss %xmm0, (%rax) +# CHECK-NEXT: - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 - - movss (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 1.33 1.33 1.33 0.33 0.33 0.33 - - - - - - - - - - movups %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 1.00 1.00 - - 1.00 1.00 movups %xmm0, (%rax) +# CHECK-NEXT: - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 - - movups (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - mulps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - mulps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - mulss %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - mulss (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - orps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - orps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - pavgb %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pavgb (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - pavgw %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pavgw (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 5.00 - 5.00 0.50 0.50 - - - - - - - - - - - pextrw $1, %mm0, %ecx +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - - - - - - - pinsrw $1, %eax, %mm2 +# CHECK-NEXT: - - - - - - - 4.00 - 4.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pinsrw $1, (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - pmaxsw %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pmaxsw (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - pmaxub %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pmaxub (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - pminsw %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pminsw (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - pminub %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pminub (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 4.00 - - 1.00 - - - - - - - - - - - - pmovmskb %mm0, %ecx +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - pmulhuw %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pmulhuw (%rax), %mm2 +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - prefetcht0 (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - prefetcht1 (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - prefetcht2 (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - prefetchnta (%rax) +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - psadbw %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psadbw (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - pshufw $1, %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pshufw $1, (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - rcpps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - rcpps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - - - - - - - rcpss %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.50 - 3.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - rcpss (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - rsqrtps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - rsqrtps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - - - - - - - rsqrtss %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.50 - 3.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - rsqrtss (%rax), %xmm2 +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 sfence +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - shufps $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - shufps $1, (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - - - 18.00 - 1.00 - - - - - - - - - - - sqrtps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - - - 19.00 - 1.00 - - - - - 0.50 0.50 0.50 0.50 - - sqrtps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - - - 16.00 - 1.00 - - - - - - - - - - - sqrtss %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - - - 17.00 - 1.00 - - - - - 0.50 0.50 0.50 0.50 - - sqrtss (%rax), %xmm2 +# CHECK-NEXT: - 0.33 0.33 0.33 11.00 11.00 11.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 stmxcsr (%rax) +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - subps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - subps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - subss %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - subss (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - ucomiss %xmm0, %xmm1 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - ucomiss (%rax), %xmm1 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - unpckhps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - unpckhps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - unpcklps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - unpcklps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - xorps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - xorps (%rax), %xmm2 diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse2.s b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse2.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse2.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse2.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -instruction-tables < %s | FileCheck %s addpd %xmm0, %xmm2 addpd (%rax), %xmm2 @@ -407,554 +407,569 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 3 1.00 addpd %xmm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * addpd (%rax), %xmm2 -# CHECK-NEXT: 1 3 1.00 addsd %xmm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * addsd (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 andnpd %xmm0, %xmm2 -# CHECK-NEXT: 2 7 1.00 * andnpd (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 andpd %xmm0, %xmm2 -# CHECK-NEXT: 2 7 1.00 * andpd (%rax), %xmm2 -# CHECK-NEXT: 4 5 1.00 * * U clflush (%rax) -# CHECK-NEXT: 1 3 1.00 cmpeqpd %xmm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * cmpeqpd (%rax), %xmm2 -# CHECK-NEXT: 1 3 1.00 cmpeqsd %xmm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * cmpeqsd (%rax), %xmm2 -# CHECK-NEXT: 2 2 1.00 comisd %xmm0, %xmm1 -# CHECK-NEXT: 3 8 1.00 * comisd (%rax), %xmm1 -# CHECK-NEXT: 2 4 1.00 cvtdq2pd %xmm0, %xmm2 -# CHECK-NEXT: 3 10 1.00 * cvtdq2pd (%rax), %xmm2 -# CHECK-NEXT: 1 3 1.00 cvtdq2ps %xmm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * cvtdq2ps (%rax), %xmm2 -# CHECK-NEXT: 2 4 1.00 cvtpd2dq %xmm0, %xmm2 -# CHECK-NEXT: 3 10 1.00 * cvtpd2dq (%rax), %xmm2 -# CHECK-NEXT: 2 4 1.00 cvtpd2pi %xmm0, %mm2 -# CHECK-NEXT: 3 10 1.00 * cvtpd2pi (%rax), %mm2 -# CHECK-NEXT: 2 4 1.00 cvtpd2ps %xmm0, %xmm2 -# CHECK-NEXT: 3 10 1.00 * cvtpd2ps (%rax), %xmm2 -# CHECK-NEXT: 2 4 1.00 cvtpi2pd %mm0, %xmm2 -# CHECK-NEXT: 3 10 1.00 * cvtpi2pd (%rax), %xmm2 -# CHECK-NEXT: 1 3 1.00 cvtps2dq %xmm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * cvtps2dq (%rax), %xmm2 -# CHECK-NEXT: 2 2 1.00 cvtps2pd %xmm0, %xmm2 -# CHECK-NEXT: 2 7 1.00 * cvtps2pd (%rax), %xmm2 -# CHECK-NEXT: 2 5 1.00 cvtsd2si %xmm0, %ecx -# CHECK-NEXT: 2 5 1.00 cvtsd2si %xmm0, %rcx -# CHECK-NEXT: 3 9 1.00 * cvtsd2si (%rax), %ecx -# CHECK-NEXT: 3 9 1.00 * cvtsd2si (%rax), %rcx -# CHECK-NEXT: 2 4 1.00 cvtsd2ss %xmm0, %xmm2 -# CHECK-NEXT: 3 10 1.00 * cvtsd2ss (%rax), %xmm2 -# CHECK-NEXT: 2 4 1.00 cvtsi2sd %ecx, %xmm2 -# CHECK-NEXT: 2 4 1.00 cvtsi2sd %rcx, %xmm2 -# CHECK-NEXT: 2 9 1.00 * cvtsi2sdl (%rax), %xmm2 -# CHECK-NEXT: 2 9 1.00 * cvtsi2sdl (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 cvtss2sd %xmm0, %xmm2 -# CHECK-NEXT: 2 7 1.00 * cvtss2sd (%rax), %xmm2 -# CHECK-NEXT: 2 4 1.00 cvttpd2dq %xmm0, %xmm2 -# CHECK-NEXT: 3 10 1.00 * cvttpd2dq (%rax), %xmm2 -# CHECK-NEXT: 2 4 1.00 cvttpd2pi %xmm0, %mm2 -# CHECK-NEXT: 3 10 1.00 * cvttpd2pi (%rax), %mm2 -# CHECK-NEXT: 1 3 1.00 cvttps2dq %xmm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * cvttps2dq (%rax), %xmm2 -# CHECK-NEXT: 2 5 1.00 cvttsd2si %xmm0, %ecx -# CHECK-NEXT: 2 5 1.00 cvttsd2si %xmm0, %rcx -# CHECK-NEXT: 3 9 1.00 * cvttsd2si (%rax), %ecx -# CHECK-NEXT: 3 9 1.00 * cvttsd2si (%rax), %rcx -# CHECK-NEXT: 1 22 22.00 divpd %xmm0, %xmm2 -# CHECK-NEXT: 2 28 22.00 * divpd (%rax), %xmm2 -# CHECK-NEXT: 1 22 22.00 divsd %xmm0, %xmm2 -# CHECK-NEXT: 2 28 22.00 * divsd (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 * * U lfence -# CHECK-NEXT: 1 1 1.00 * * U maskmovdqu %xmm0, %xmm1 -# CHECK-NEXT: 1 3 1.00 maxpd %xmm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * maxpd (%rax), %xmm2 -# CHECK-NEXT: 1 3 1.00 maxsd %xmm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * maxsd (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 * * U mfence -# CHECK-NEXT: 1 3 1.00 minpd %xmm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * minpd (%rax), %xmm2 -# CHECK-NEXT: 1 3 1.00 minsd %xmm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * minsd (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 movapd %xmm0, %xmm2 -# CHECK-NEXT: 1 1 1.00 * movapd %xmm0, (%rax) -# CHECK-NEXT: 1 6 0.50 * movapd (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 movd %eax, %xmm2 -# CHECK-NEXT: 1 6 0.50 * movd (%rax), %xmm2 -# CHECK-NEXT: 1 2 1.00 movd %xmm0, %ecx -# CHECK-NEXT: 1 1 1.00 * movd %xmm0, (%rax) -# CHECK-NEXT: 1 1 0.33 movdqa %xmm0, %xmm2 -# CHECK-NEXT: 1 1 1.00 * movdqa %xmm0, (%rax) -# CHECK-NEXT: 1 6 0.50 * movdqa (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.33 movdqu %xmm0, %xmm2 -# CHECK-NEXT: 1 1 1.00 * movdqu %xmm0, (%rax) -# CHECK-NEXT: 1 6 0.50 * movdqu (%rax), %xmm2 -# CHECK-NEXT: 2 2 1.00 movdq2q %xmm0, %mm2 -# CHECK-NEXT: 1 1 1.00 * movhpd %xmm0, (%rax) -# CHECK-NEXT: 2 7 1.00 * movhpd (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 * movlpd %xmm0, (%rax) -# CHECK-NEXT: 2 7 1.00 * movlpd (%rax), %xmm2 -# CHECK-NEXT: 1 2 1.00 movmskpd %xmm0, %ecx -# CHECK-NEXT: 1 1 1.00 * movntil %eax, (%rax) -# CHECK-NEXT: 1 1 1.00 * movntiq %rax, (%rax) -# CHECK-NEXT: 1 1 1.00 * movntdq %xmm0, (%rax) -# CHECK-NEXT: 1 1 1.00 * movntpd %xmm0, (%rax) -# CHECK-NEXT: 1 1 0.33 movq %xmm0, %xmm2 -# CHECK-NEXT: 1 1 1.00 movq %rax, %xmm2 -# CHECK-NEXT: 1 6 0.50 * movq (%rax), %xmm2 -# CHECK-NEXT: 1 2 1.00 movq %xmm0, %rcx -# CHECK-NEXT: 1 1 1.00 * movq %xmm0, (%rax) -# CHECK-NEXT: 1 1 0.33 movq2dq %mm0, %xmm2 -# CHECK-NEXT: 1 1 1.00 movsd %xmm0, %xmm2 -# CHECK-NEXT: 1 1 1.00 * movsd %xmm0, (%rax) -# CHECK-NEXT: 1 6 0.50 * movsd (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 movupd %xmm0, %xmm2 -# CHECK-NEXT: 1 1 1.00 * movupd %xmm0, (%rax) -# CHECK-NEXT: 1 6 0.50 * movupd (%rax), %xmm2 -# CHECK-NEXT: 1 5 1.00 mulpd %xmm0, %xmm2 -# CHECK-NEXT: 2 11 1.00 * mulpd (%rax), %xmm2 -# CHECK-NEXT: 1 5 1.00 mulsd %xmm0, %xmm2 -# CHECK-NEXT: 2 11 1.00 * mulsd (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 orpd %xmm0, %xmm2 -# CHECK-NEXT: 2 7 1.00 * orpd (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 packssdw %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * packssdw (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 packsswb %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * packsswb (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 packuswb %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * packuswb (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 paddb %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * paddb (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 paddd %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * paddd (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 paddq %mm0, %mm2 -# CHECK-NEXT: 2 7 0.50 * paddq (%rax), %mm2 -# CHECK-NEXT: 1 1 0.50 paddq %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * paddq (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 paddsb %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * paddsb (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 paddsw %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * paddsw (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 paddusb %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * paddusb (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 paddusw %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * paddusw (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 paddw %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * paddw (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.33 pand %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * pand (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.33 pandn %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * pandn (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 pavgb %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * pavgb (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 pavgw %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * pavgw (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 pcmpeqb %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * pcmpeqb (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 pcmpeqd %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * pcmpeqd (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 pcmpeqw %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * pcmpeqw (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 pcmpgtb %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * pcmpgtb (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 pcmpgtd %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * pcmpgtd (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 pcmpgtw %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * pcmpgtw (%rax), %xmm2 -# CHECK-NEXT: 2 3 1.00 pextrw $1, %xmm0, %ecx -# CHECK-NEXT: 2 2 1.00 pinsrw $1, %eax, %xmm0 -# CHECK-NEXT: 2 7 0.50 * pinsrw $1, (%rax), %xmm0 -# CHECK-NEXT: 1 5 1.00 pmaddwd %xmm0, %xmm2 -# CHECK-NEXT: 2 11 1.00 * pmaddwd (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 pmaxsw %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * pmaxsw (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 pmaxub %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * pmaxub (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 pminsw %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * pminsw (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 pminub %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * pminub (%rax), %xmm2 -# CHECK-NEXT: 1 2 1.00 pmovmskb %xmm0, %ecx -# CHECK-NEXT: 1 5 1.00 pmulhuw %xmm0, %xmm2 -# CHECK-NEXT: 2 11 1.00 * pmulhuw (%rax), %xmm2 -# CHECK-NEXT: 1 5 1.00 pmulhw %xmm0, %xmm2 -# CHECK-NEXT: 2 11 1.00 * pmulhw (%rax), %xmm2 -# CHECK-NEXT: 1 5 1.00 pmullw %xmm0, %xmm2 -# CHECK-NEXT: 2 11 1.00 * pmullw (%rax), %xmm2 -# CHECK-NEXT: 1 5 1.00 pmuludq %mm0, %mm2 -# CHECK-NEXT: 2 10 1.00 * pmuludq (%rax), %mm2 -# CHECK-NEXT: 1 5 1.00 pmuludq %xmm0, %xmm2 -# CHECK-NEXT: 2 11 1.00 * pmuludq (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.33 por %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * por (%rax), %xmm2 -# CHECK-NEXT: 1 5 1.00 psadbw %xmm0, %xmm2 -# CHECK-NEXT: 2 11 1.00 * psadbw (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 pshufd $1, %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * pshufd $1, (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 pshufhw $1, %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * pshufhw $1, (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 pshuflw $1, %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * pshuflw $1, (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 pslld $1, %xmm2 -# CHECK-NEXT: 2 2 1.00 pslld %xmm0, %xmm2 -# CHECK-NEXT: 3 8 1.00 * pslld (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 pslldq $1, %xmm2 -# CHECK-NEXT: 1 1 1.00 psllq $1, %xmm2 -# CHECK-NEXT: 2 2 1.00 psllq %xmm0, %xmm2 -# CHECK-NEXT: 3 8 1.00 * psllq (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 psllw $1, %xmm2 -# CHECK-NEXT: 2 2 1.00 psllw %xmm0, %xmm2 -# CHECK-NEXT: 3 8 1.00 * psllw (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 psrad $1, %xmm2 -# CHECK-NEXT: 2 2 1.00 psrad %xmm0, %xmm2 -# CHECK-NEXT: 3 8 1.00 * psrad (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 psraw $1, %xmm2 -# CHECK-NEXT: 2 2 1.00 psraw %xmm0, %xmm2 -# CHECK-NEXT: 3 8 1.00 * psraw (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 psrld $1, %xmm2 -# CHECK-NEXT: 2 2 1.00 psrld %xmm0, %xmm2 -# CHECK-NEXT: 3 8 1.00 * psrld (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 psrldq $1, %xmm2 -# CHECK-NEXT: 1 1 1.00 psrlq $1, %xmm2 -# CHECK-NEXT: 2 2 1.00 psrlq %xmm0, %xmm2 -# CHECK-NEXT: 3 8 1.00 * psrlq (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 psrlw $1, %xmm2 -# CHECK-NEXT: 2 2 1.00 psrlw %xmm0, %xmm2 -# CHECK-NEXT: 3 8 1.00 * psrlw (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 psubb %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * psubb (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 psubd %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * psubd (%rax), %xmm2 -# CHECK-NEXT: 1 3 1.00 psubq %mm0, %mm2 -# CHECK-NEXT: 2 8 1.00 * psubq (%rax), %mm2 -# CHECK-NEXT: 1 1 0.50 psubq %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * psubq (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 psubsb %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * psubsb (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 psubsw %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * psubsw (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 psubusb %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * psubusb (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 psubusw %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * psubusw (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 psubw %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * psubw (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 punpckhbw %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * punpckhbw (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 punpckhdq %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * punpckhdq (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 punpckhqdq %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * punpckhqdq (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 punpckhwd %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * punpckhwd (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 punpcklbw %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * punpcklbw (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 punpckldq %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * punpckldq (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 punpcklqdq %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * punpcklqdq (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.50 punpcklwd %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * punpcklwd (%rax), %xmm2 -# CHECK-NEXT: 1 1 0.33 pxor %xmm0, %xmm2 -# CHECK-NEXT: 2 7 0.50 * pxor (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 shufpd $1, %xmm0, %xmm2 -# CHECK-NEXT: 2 7 1.00 * shufpd $1, (%rax), %xmm2 -# CHECK-NEXT: 1 21 21.00 sqrtpd %xmm0, %xmm2 -# CHECK-NEXT: 2 27 21.00 * sqrtpd (%rax), %xmm2 -# CHECK-NEXT: 1 21 21.00 sqrtsd %xmm0, %xmm2 -# CHECK-NEXT: 2 27 21.00 * sqrtsd (%rax), %xmm2 -# CHECK-NEXT: 1 3 1.00 subpd %xmm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * subpd (%rax), %xmm2 -# CHECK-NEXT: 1 3 1.00 subsd %xmm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * subsd (%rax), %xmm2 -# CHECK-NEXT: 2 2 1.00 ucomisd %xmm0, %xmm1 -# CHECK-NEXT: 3 8 1.00 * ucomisd (%rax), %xmm1 -# CHECK-NEXT: 1 1 1.00 unpckhpd %xmm0, %xmm2 -# CHECK-NEXT: 2 7 1.00 * unpckhpd (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 unpcklpd %xmm0, %xmm2 -# CHECK-NEXT: 2 7 1.00 * unpcklpd (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 xorpd %xmm0, %xmm2 -# CHECK-NEXT: 2 7 1.00 * xorpd (%rax), %xmm2 +# CHECK-NEXT: 1 4 2.50 addpd %xmm0, %xmm2 +# CHECK-NEXT: 1 6 3.00 * addpd (%rax), %xmm2 +# CHECK-NEXT: 1 4 2.50 addsd %xmm0, %xmm2 +# CHECK-NEXT: 1 6 3.00 * addsd (%rax), %xmm2 +# CHECK-NEXT: 1 2 2.00 andnpd %xmm0, %xmm2 +# CHECK-NEXT: 1 4 2.50 * andnpd (%rax), %xmm2 +# CHECK-NEXT: 1 2 2.00 andpd %xmm0, %xmm2 +# CHECK-NEXT: 1 4 2.50 * andpd (%rax), %xmm2 +# CHECK-NEXT: 1 4 0.50 * * U clflush (%rax) +# CHECK-NEXT: 1 3 3.00 cmpeqpd %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.50 * cmpeqpd (%rax), %xmm2 +# CHECK-NEXT: 1 3 3.00 cmpeqsd %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.50 * cmpeqsd (%rax), %xmm2 +# CHECK-NEXT: 1 1 2.50 comisd %xmm0, %xmm1 +# CHECK-NEXT: 1 3 3.00 * comisd (%rax), %xmm1 +# CHECK-NEXT: 1 49 2.50 cvtdq2pd %xmm0, %xmm2 +# CHECK-NEXT: 1 51 3.00 * cvtdq2pd (%rax), %xmm2 +# CHECK-NEXT: 1 5 2.00 cvtdq2ps %xmm0, %xmm2 +# CHECK-NEXT: 1 7 3.00 * cvtdq2ps (%rax), %xmm2 +# CHECK-NEXT: 2 7 2.50 cvtpd2dq %xmm0, %xmm2 +# CHECK-NEXT: 2 9 3.00 * cvtpd2dq (%rax), %xmm2 +# CHECK-NEXT: 2 7 2.50 cvtpd2pi %xmm0, %mm2 +# CHECK-NEXT: 2 9 3.00 * cvtpd2pi (%rax), %mm2 +# CHECK-NEXT: 2 8 2.50 cvtpd2ps %xmm0, %xmm2 +# CHECK-NEXT: 2 10 3.00 * cvtpd2ps (%rax), %xmm2 +# CHECK-NEXT: 1 49 2.50 cvtpi2pd %mm0, %xmm2 +# CHECK-NEXT: 1 51 3.00 * cvtpi2pd (%rax), %xmm2 +# CHECK-NEXT: 1 5 2.50 cvtps2dq %xmm0, %xmm2 +# CHECK-NEXT: 1 7 3.00 * cvtps2dq (%rax), %xmm2 +# CHECK-NEXT: 1 42 2.00 cvtps2pd %xmm0, %xmm2 +# CHECK-NEXT: 1 44 3.00 * cvtps2pd (%rax), %xmm2 +# CHECK-NEXT: 2 8 2.50 cvtsd2si %xmm0, %ecx +# CHECK-NEXT: 2 8 2.50 cvtsd2si %xmm0, %rcx +# CHECK-NEXT: 2 10 3.00 * cvtsd2si (%rax), %ecx +# CHECK-NEXT: 2 10 3.00 * cvtsd2si (%rax), %rcx +# CHECK-NEXT: 3 9 2.50 cvtsd2ss %xmm0, %xmm2 +# CHECK-NEXT: 3 11 3.00 * cvtsd2ss (%rax), %xmm2 +# CHECK-NEXT: 3 3 3.00 cvtsi2sd %ecx, %xmm2 +# CHECK-NEXT: 3 3 3.00 cvtsi2sd %rcx, %xmm2 +# CHECK-NEXT: 3 5 4.00 * cvtsi2sdl (%rax), %xmm2 +# CHECK-NEXT: 3 5 4.00 * cvtsi2sdl (%rax), %xmm2 +# CHECK-NEXT: 2 8 2.50 cvtss2sd %xmm0, %xmm2 +# CHECK-NEXT: 2 10 3.00 * cvtss2sd (%rax), %xmm2 +# CHECK-NEXT: 2 7 2.50 cvttpd2dq %xmm0, %xmm2 +# CHECK-NEXT: 2 9 3.00 * cvttpd2dq (%rax), %xmm2 +# CHECK-NEXT: 2 7 2.50 cvttpd2pi %xmm0, %mm2 +# CHECK-NEXT: 2 9 3.00 * cvttpd2pi (%rax), %mm2 +# CHECK-NEXT: 1 5 2.50 cvttps2dq %xmm0, %xmm2 +# CHECK-NEXT: 1 7 3.00 * cvttps2dq (%rax), %xmm2 +# CHECK-NEXT: 2 8 2.50 cvttsd2si %xmm0, %ecx +# CHECK-NEXT: 2 8 2.50 cvttsd2si %xmm0, %rcx +# CHECK-NEXT: 2 10 3.00 * cvttsd2si (%rax), %ecx +# CHECK-NEXT: 2 10 3.00 * cvttsd2si (%rax), %rcx +# CHECK-NEXT: 1 20 17.00 divpd %xmm0, %xmm2 +# CHECK-NEXT: 1 22 18.00 * divpd (%rax), %xmm2 +# CHECK-NEXT: 1 20 17.00 divsd %xmm0, %xmm2 +# CHECK-NEXT: 1 22 18.00 * divsd (%rax), %xmm2 +# CHECK-NEXT: 6 1 0.50 * * U lfence +# CHECK-NEXT: 2 2 1.00 * * U maskmovdqu %xmm0, %xmm1 +# CHECK-NEXT: 1 3 3.00 maxpd %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.50 * maxpd (%rax), %xmm2 +# CHECK-NEXT: 1 3 3.00 maxsd %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.50 * maxsd (%rax), %xmm2 +# CHECK-NEXT: 6 1 0.50 * * U mfence +# CHECK-NEXT: 1 3 3.00 minpd %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.50 * minpd (%rax), %xmm2 +# CHECK-NEXT: 1 3 3.00 minsd %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.50 * minsd (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.33 movapd %xmm0, %xmm2 +# CHECK-NEXT: 2 2 1.00 * movapd %xmm0, (%rax) +# CHECK-NEXT: 1 2 0.50 * movapd (%rax), %xmm2 +# CHECK-NEXT: 2 6 3.00 movd %eax, %xmm2 +# CHECK-NEXT: 1 3 0.50 * movd (%rax), %xmm2 +# CHECK-NEXT: 1 6 2.00 movd %xmm0, %ecx +# CHECK-NEXT: 1 2 1.00 * movd %xmm0, (%rax) +# CHECK-NEXT: 1 3 2.00 movdqa %xmm0, %xmm2 +# CHECK-NEXT: 2 2 1.00 * movdqa %xmm0, (%rax) +# CHECK-NEXT: 1 2 0.50 * movdqa (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.00 movdqu %xmm0, %xmm2 +# CHECK-NEXT: 2 2 1.00 * movdqu %xmm0, (%rax) +# CHECK-NEXT: 1 2 0.50 * movdqu (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.00 movdq2q %xmm0, %mm2 +# CHECK-NEXT: 1 2 1.00 * movhpd %xmm0, (%rax) +# CHECK-NEXT: 1 5 3.00 * movhpd (%rax), %xmm2 +# CHECK-NEXT: 1 2 1.00 * movlpd %xmm0, (%rax) +# CHECK-NEXT: 1 5 3.00 * movlpd (%rax), %xmm2 +# CHECK-NEXT: 1 6 2.00 movmskpd %xmm0, %ecx +# CHECK-NEXT: 1 3 0.50 * movntil %eax, (%rax) +# CHECK-NEXT: 1 3 0.50 * movntiq %rax, (%rax) +# CHECK-NEXT: 2 2 1.00 * movntdq %xmm0, (%rax) +# CHECK-NEXT: 2 3 1.00 * movntpd %xmm0, (%rax) +# CHECK-NEXT: 1 3 2.50 movq %xmm0, %xmm2 +# CHECK-NEXT: 2 6 3.00 movq %rax, %xmm2 +# CHECK-NEXT: 1 3 0.50 * movq (%rax), %xmm2 +# CHECK-NEXT: 1 6 2.00 movq %xmm0, %rcx +# CHECK-NEXT: 1 2 1.00 * movq %xmm0, (%rax) +# CHECK-NEXT: 1 3 2.00 movq2dq %mm0, %xmm2 +# CHECK-NEXT: 1 3 2.50 movsd %xmm0, %xmm2 +# CHECK-NEXT: 1 2 1.00 * movsd %xmm0, (%rax) +# CHECK-NEXT: 1 2 0.50 * movsd (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.33 movupd %xmm0, %xmm2 +# CHECK-NEXT: 2 2 1.00 * movupd %xmm0, (%rax) +# CHECK-NEXT: 1 2 0.50 * movupd (%rax), %xmm2 +# CHECK-NEXT: 1 4 2.50 mulpd %xmm0, %xmm2 +# CHECK-NEXT: 1 6 3.00 * mulpd (%rax), %xmm2 +# CHECK-NEXT: 1 4 2.50 mulsd %xmm0, %xmm2 +# CHECK-NEXT: 1 6 3.00 * mulsd (%rax), %xmm2 +# CHECK-NEXT: 1 2 2.00 orpd %xmm0, %xmm2 +# CHECK-NEXT: 1 4 2.50 * orpd (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 packssdw %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * packssdw (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 packsswb %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * packsswb (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 packuswb %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * packuswb (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 paddb %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * paddb (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 paddd %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * paddd (%rax), %xmm2 +# CHECK-NEXT: 1 2 1.50 paddq %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * paddq (%rax), %mm2 +# CHECK-NEXT: 1 3 2.50 paddq %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * paddq (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 paddsb %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * paddsb (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 paddsw %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * paddsw (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 paddusb %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * paddusb (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 paddusw %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * paddusw (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 paddw %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * paddw (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 pand %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * pand (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 pandn %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * pandn (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 pavgb %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * pavgb (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 pavgw %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * pavgw (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 pcmpeqb %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * pcmpeqb (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 pcmpeqd %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * pcmpeqd (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 pcmpeqw %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * pcmpeqw (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 pcmpgtb %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * pcmpgtb (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 pcmpgtd %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * pcmpgtd (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 pcmpgtw %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * pcmpgtw (%rax), %xmm2 +# CHECK-NEXT: 2 7 5.00 pextrw $1, %xmm0, %ecx +# CHECK-NEXT: 2 3 3.00 pinsrw $1, %eax, %xmm0 +# CHECK-NEXT: 1 5 4.00 * pinsrw $1, (%rax), %xmm0 +# CHECK-NEXT: 1 3 2.50 pmaddwd %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * pmaddwd (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 pmaxsw %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * pmaxsw (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 pmaxub %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * pmaxub (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 pminsw %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * pminsw (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 pminub %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * pminub (%rax), %xmm2 +# CHECK-NEXT: 1 7 2.50 pmovmskb %xmm0, %ecx +# CHECK-NEXT: 1 3 2.50 pmulhuw %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * pmulhuw (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 pmulhw %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * pmulhw (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 pmullw %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * pmullw (%rax), %xmm2 +# CHECK-NEXT: 1 3 1.50 pmuludq %mm0, %mm2 +# CHECK-NEXT: 1 5 2.00 * pmuludq (%rax), %mm2 +# CHECK-NEXT: 1 3 2.50 pmuludq %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * pmuludq (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 por %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * por (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 psadbw %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * psadbw (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 pshufd $1, %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * pshufd $1, (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 pshufhw $1, %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * pshufhw $1, (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 pshuflw $1, %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * pshuflw $1, (%rax), %xmm2 +# CHECK-NEXT: 1 3 3.00 pslld $1, %xmm2 +# CHECK-NEXT: 1 3 2.50 pslld %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * pslld (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 pslldq $1, %xmm2 +# CHECK-NEXT: 1 3 3.00 psllq $1, %xmm2 +# CHECK-NEXT: 1 3 2.50 psllq %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * psllq (%rax), %xmm2 +# CHECK-NEXT: 1 3 3.00 psllw $1, %xmm2 +# CHECK-NEXT: 1 3 2.50 psllw %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * psllw (%rax), %xmm2 +# CHECK-NEXT: 1 3 3.00 psrad $1, %xmm2 +# CHECK-NEXT: 1 3 2.50 psrad %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * psrad (%rax), %xmm2 +# CHECK-NEXT: 1 3 3.00 psraw $1, %xmm2 +# CHECK-NEXT: 1 3 2.50 psraw %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * psraw (%rax), %xmm2 +# CHECK-NEXT: 1 3 3.00 psrld $1, %xmm2 +# CHECK-NEXT: 1 3 2.50 psrld %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * psrld (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 psrldq $1, %xmm2 +# CHECK-NEXT: 1 3 3.00 psrlq $1, %xmm2 +# CHECK-NEXT: 1 3 2.50 psrlq %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * psrlq (%rax), %xmm2 +# CHECK-NEXT: 1 3 3.00 psrlw $1, %xmm2 +# CHECK-NEXT: 1 3 2.50 psrlw %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * psrlw (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 psubb %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * psubb (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 psubd %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * psubd (%rax), %xmm2 +# CHECK-NEXT: 1 2 1.50 psubq %mm0, %mm2 +# CHECK-NEXT: 1 4 2.00 * psubq (%rax), %mm2 +# CHECK-NEXT: 1 3 2.50 psubq %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * psubq (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 psubsb %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * psubsb (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 psubsw %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * psubsw (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 psubusb %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * psubusb (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 psubusw %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * psubusw (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 psubw %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * psubw (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 punpckhbw %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * punpckhbw (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 punpckhdq %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * punpckhdq (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 punpckhqdq %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * punpckhqdq (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 punpckhwd %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * punpckhwd (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 punpcklbw %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * punpcklbw (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 punpckldq %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * punpckldq (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 punpcklqdq %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * punpcklqdq (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 punpcklwd %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * punpcklwd (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 pxor %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * pxor (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 shufpd $1, %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * shufpd $1, (%rax), %xmm2 +# CHECK-NEXT: 1 27 24.00 sqrtpd %xmm0, %xmm2 +# CHECK-NEXT: 1 29 25.00 * sqrtpd (%rax), %xmm2 +# CHECK-NEXT: 1 27 24.00 sqrtsd %xmm0, %xmm2 +# CHECK-NEXT: 1 29 25.00 * sqrtsd (%rax), %xmm2 +# CHECK-NEXT: 1 4 2.50 subpd %xmm0, %xmm2 +# CHECK-NEXT: 1 6 3.00 * subpd (%rax), %xmm2 +# CHECK-NEXT: 1 4 2.50 subsd %xmm0, %xmm2 +# CHECK-NEXT: 1 6 3.00 * subsd (%rax), %xmm2 +# CHECK-NEXT: 1 1 2.50 ucomisd %xmm0, %xmm1 +# CHECK-NEXT: 1 3 3.00 * ucomisd (%rax), %xmm1 +# CHECK-NEXT: 1 3 2.50 unpckhpd %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * unpckhpd (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 unpcklpd %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * unpcklpd (%rax), %xmm2 +# CHECK-NEXT: 1 2 2.00 xorpd %xmm0, %xmm2 +# CHECK-NEXT: 1 4 2.50 * xorpd (%rax), %xmm2 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - 172.00 75.83 118.33 17.00 100.83 67.00 67.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - 1.67 1.67 1.67 - - - 620.00 55.00 782.00 116.00 121.00 25.00 - 1.67 1.67 1.67 70.00 70.00 59.00 59.00 11.00 11.00 # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - 1.00 - - - - addpd %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 addpd (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - - - - addsd %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 addsd (%rax), %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - andnpd %xmm0, %xmm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 andnpd (%rax), %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - andpd %xmm0, %xmm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 andpd (%rax), %xmm2 -# CHECK-NEXT: - - 0.50 0.50 1.00 1.00 0.50 0.50 clflush (%rax) -# CHECK-NEXT: - - - 1.00 - - - - cmpeqpd %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cmpeqpd (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - - - - cmpeqsd %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cmpeqsd (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 1.00 - - - - comisd %xmm0, %xmm1 -# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 comisd (%rax), %xmm1 -# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtdq2pd %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvtdq2pd (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - - - - cvtdq2ps %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cvtdq2ps (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtpd2dq %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvtpd2dq (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtpd2pi %xmm0, %mm2 -# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvtpd2pi (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtpd2ps %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvtpd2ps (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtpi2pd %mm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvtpi2pd (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - - - - cvtps2dq %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cvtps2dq (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - - 1.00 - - cvtps2pd %xmm0, %xmm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 cvtps2pd (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 1.00 - - - - cvtsd2si %xmm0, %ecx -# CHECK-NEXT: - - 1.00 1.00 - - - - cvtsd2si %xmm0, %rcx -# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 cvtsd2si (%rax), %ecx -# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 cvtsd2si (%rax), %rcx -# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtsd2ss %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvtsd2ss (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtsi2sd %ecx, %xmm2 -# CHECK-NEXT: - - - 1.00 - 1.00 - - cvtsi2sd %rcx, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cvtsi2sdl (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cvtsi2sdl (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - cvtss2sd %xmm0, %xmm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 cvtss2sd (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - 1.00 - - cvttpd2dq %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvttpd2dq (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - 1.00 - - cvttpd2pi %xmm0, %mm2 -# CHECK-NEXT: - - - 1.00 - 1.00 0.50 0.50 cvttpd2pi (%rax), %mm2 -# CHECK-NEXT: - - - 1.00 - - - - cvttps2dq %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 cvttps2dq (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 1.00 - - - - cvttsd2si %xmm0, %ecx -# CHECK-NEXT: - - 1.00 1.00 - - - - cvttsd2si %xmm0, %rcx -# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 cvttsd2si (%rax), %ecx -# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 cvttsd2si (%rax), %rcx -# CHECK-NEXT: - 22.00 1.00 - - - - - divpd %xmm0, %xmm2 -# CHECK-NEXT: - 22.00 1.00 - - - 0.50 0.50 divpd (%rax), %xmm2 -# CHECK-NEXT: - 22.00 1.00 - - - - - divsd %xmm0, %xmm2 -# CHECK-NEXT: - 22.00 1.00 - - - 0.50 0.50 divsd (%rax), %xmm2 -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 lfence -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 maskmovdqu %xmm0, %xmm1 -# CHECK-NEXT: - - - 1.00 - - - - maxpd %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 maxpd (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - - - - maxsd %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 maxsd (%rax), %xmm2 -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 mfence -# CHECK-NEXT: - - - 1.00 - - - - minpd %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 minpd (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - - - - minsd %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 minsd (%rax), %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - movapd %xmm0, %xmm2 -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movapd %xmm0, (%rax) -# CHECK-NEXT: - - - - - - 0.50 0.50 movapd (%rax), %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - movd %eax, %xmm2 -# CHECK-NEXT: - - - - - - 0.50 0.50 movd (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - movd %xmm0, %ecx -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movd %xmm0, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movdqa %xmm0, %xmm2 -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movdqa %xmm0, (%rax) -# CHECK-NEXT: - - - - - - 0.50 0.50 movdqa (%rax), %xmm2 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movdqu %xmm0, %xmm2 -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movdqu %xmm0, (%rax) -# CHECK-NEXT: - - - - - - 0.50 0.50 movdqu (%rax), %xmm2 -# CHECK-NEXT: - - 0.33 0.33 - 1.33 - - movdq2q %xmm0, %mm2 -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movhpd %xmm0, (%rax) -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 movhpd (%rax), %xmm2 -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movlpd %xmm0, (%rax) -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 movlpd (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - movmskpd %xmm0, %ecx -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movntil %eax, (%rax) -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movntiq %rax, (%rax) -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movntdq %xmm0, (%rax) -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movntpd %xmm0, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movq %xmm0, %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - movq %rax, %xmm2 -# CHECK-NEXT: - - - - - - 0.50 0.50 movq (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - movq %xmm0, %rcx -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movq %xmm0, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movq2dq %mm0, %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - movsd %xmm0, %xmm2 -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movsd %xmm0, (%rax) -# CHECK-NEXT: - - - - - - 0.50 0.50 movsd (%rax), %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - movupd %xmm0, %xmm2 -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movupd %xmm0, (%rax) -# CHECK-NEXT: - - - - - - 0.50 0.50 movupd (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - mulpd %xmm0, %xmm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 mulpd (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - mulsd %xmm0, %xmm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 mulsd (%rax), %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - orpd %xmm0, %xmm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 orpd (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - packssdw %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 packssdw (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - packsswb %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 packsswb (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - packuswb %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 packuswb (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - paddb %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddb (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - paddd %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddd (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - paddq %mm0, %mm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddq (%rax), %mm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - paddq %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddq (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - paddsb %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddsb (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - paddsw %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddsw (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - paddusb %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddusb (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - paddusw %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddusw (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - paddw %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 paddw (%rax), %xmm2 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - pand %xmm0, %xmm2 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 pand (%rax), %xmm2 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - pandn %xmm0, %xmm2 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 pandn (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - pavgb %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pavgb (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - pavgw %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pavgw (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - pcmpeqb %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pcmpeqb (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - pcmpeqd %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pcmpeqd (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - pcmpeqw %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pcmpeqw (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - pcmpgtb %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pcmpgtb (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - pcmpgtd %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pcmpgtd (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - pcmpgtw %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pcmpgtw (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - pextrw $1, %xmm0, %ecx -# CHECK-NEXT: - - - 0.50 - 1.50 - - pinsrw $1, %eax, %xmm0 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pinsrw $1, (%rax), %xmm0 -# CHECK-NEXT: - - 1.00 - - - - - pmaddwd %xmm0, %xmm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmaddwd (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - pmaxsw %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmaxsw (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - pmaxub %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pmaxub (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - pminsw %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pminsw (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - pminub %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pminub (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - pmovmskb %xmm0, %ecx -# CHECK-NEXT: - - 1.00 - - - - - pmulhuw %xmm0, %xmm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmulhuw (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - pmulhw %xmm0, %xmm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmulhw (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - pmullw %xmm0, %xmm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmullw (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - pmuludq %mm0, %mm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmuludq (%rax), %mm2 -# CHECK-NEXT: - - 1.00 - - - - - pmuludq %xmm0, %xmm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 pmuludq (%rax), %xmm2 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - por %xmm0, %xmm2 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 por (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - psadbw %xmm0, %xmm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 psadbw (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - pshufd $1, %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pshufd $1, (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - pshufhw $1, %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pshufhw $1, (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - pshuflw $1, %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 pshuflw $1, (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - pslld $1, %xmm2 -# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - pslld %xmm0, %xmm2 -# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 pslld (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - pslldq $1, %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - psllq $1, %xmm2 -# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - psllq %xmm0, %xmm2 -# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 psllq (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - psllw $1, %xmm2 -# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - psllw %xmm0, %xmm2 -# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 psllw (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - psrad $1, %xmm2 -# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - psrad %xmm0, %xmm2 -# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 psrad (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - psraw $1, %xmm2 -# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - psraw %xmm0, %xmm2 -# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 psraw (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - psrld $1, %xmm2 -# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - psrld %xmm0, %xmm2 -# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 psrld (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - psrldq $1, %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - psrlq $1, %xmm2 -# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - psrlq %xmm0, %xmm2 -# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 psrlq (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - psrlw $1, %xmm2 -# CHECK-NEXT: - - 1.00 0.50 - 0.50 - - psrlw %xmm0, %xmm2 -# CHECK-NEXT: - - 1.00 0.50 - 0.50 0.50 0.50 psrlw (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - psubb %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psubb (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - psubd %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psubd (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - - - - psubq %mm0, %mm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 psubq (%rax), %mm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - psubq %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psubq (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - psubsb %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psubsb (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - psubsw %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psubsw (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - psubusb %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psubusb (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - psubusw %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psubusw (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - psubw %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 psubw (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - punpckhbw %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 punpckhbw (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - punpckhdq %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 punpckhdq (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - punpckhqdq %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 punpckhqdq (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - punpckhwd %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 punpckhwd (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - punpcklbw %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 punpcklbw (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - punpckldq %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 punpckldq (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - punpcklqdq %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 punpcklqdq (%rax), %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - punpcklwd %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 0.50 0.50 punpcklwd (%rax), %xmm2 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - pxor %xmm0, %xmm2 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 pxor (%rax), %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - shufpd $1, %xmm0, %xmm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 shufpd $1, (%rax), %xmm2 -# CHECK-NEXT: - 21.00 1.00 - - - - - sqrtpd %xmm0, %xmm2 -# CHECK-NEXT: - 21.00 1.00 - - - 0.50 0.50 sqrtpd (%rax), %xmm2 -# CHECK-NEXT: - 21.00 1.00 - - - - - sqrtsd %xmm0, %xmm2 -# CHECK-NEXT: - 21.00 1.00 - - - 0.50 0.50 sqrtsd (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - - - - subpd %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 subpd (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - - - - subsd %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 subsd (%rax), %xmm2 -# CHECK-NEXT: - - 1.00 1.00 - - - - ucomisd %xmm0, %xmm1 -# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 ucomisd (%rax), %xmm1 -# CHECK-NEXT: - - - - - 1.00 - - unpckhpd %xmm0, %xmm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 unpckhpd (%rax), %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - unpcklpd %xmm0, %xmm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 unpcklpd (%rax), %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - xorpd %xmm0, %xmm2 -# CHECK-NEXT: - - - - - 1.00 0.50 0.50 xorpd (%rax), %xmm2 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - addpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - addpd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - addsd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - addsd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - andnpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - andnpd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - andpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - andpd (%rax), %xmm2 +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - clflush (%rax) +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - - - - - - - cmpeqpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.50 - 3.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - cmpeqpd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - - - - - - - cmpeqsd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.50 - 3.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - cmpeqsd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - comisd %xmm0, %xmm1 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - comisd (%rax), %xmm1 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - cvtdq2pd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - cvtdq2pd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - - 2.00 - - - 1.00 - - - - - - - - - - cvtdq2ps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - - 3.00 - - - 1.00 - - - - 0.50 0.50 0.50 0.50 - - cvtdq2ps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - cvtpd2dq %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - cvtpd2dq (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - cvtpd2pi %xmm0, %mm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - cvtpd2pi (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - cvtpd2ps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - cvtpd2ps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - cvtpi2pd %mm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - cvtpi2pd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - cvtps2dq %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - cvtps2dq (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - - 2.00 - - - 1.00 - - - - - - - - - - cvtps2pd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - - 3.00 - - - 1.00 - - - - 0.50 0.50 0.50 0.50 - - cvtps2pd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - cvtsd2si %xmm0, %ecx +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - cvtsd2si %xmm0, %rcx +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - cvtsd2si (%rax), %ecx +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - cvtsd2si (%rax), %rcx +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - cvtsd2ss %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - cvtsd2ss (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - - 3.00 - - - 1.00 - - - - - - - - - - cvtsi2sd %ecx, %xmm2 +# CHECK-NEXT: - - - - - - - - 3.00 - - - 1.00 - - - - - - - - - - cvtsi2sd %rcx, %xmm2 +# CHECK-NEXT: - - - - - - - - 4.00 - - - 1.00 - - - - 0.50 0.50 0.50 0.50 - - cvtsi2sdl (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - - 4.00 - - - 1.00 - - - - 0.50 0.50 0.50 0.50 - - cvtsi2sdl (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - cvtss2sd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - cvtss2sd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - cvttpd2dq %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - cvttpd2dq (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - cvttpd2pi %xmm0, %mm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - cvttpd2pi (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - cvttps2dq %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - cvttps2dq (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - cvttsd2si %xmm0, %ecx +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - cvttsd2si %xmm0, %rcx +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - cvttsd2si (%rax), %ecx +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - cvttsd2si (%rax), %rcx +# CHECK-NEXT: - - - - - - - - - 17.00 - 1.00 - - - - - - - - - - - divpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - - - 18.00 - 1.00 - - - - - 0.50 0.50 0.50 0.50 - - divpd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - - - 17.00 - 1.00 - - - - - - - - - - - divsd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - - - 18.00 - 1.00 - - - - - 0.50 0.50 0.50 0.50 - - divsd (%rax), %xmm2 +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 lfence +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 1.00 1.00 - - 1.00 1.00 maskmovdqu %xmm0, %xmm1 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - - - - - - - maxpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.50 - 3.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - maxpd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - - - - - - - maxsd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.50 - 3.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - maxsd (%rax), %xmm2 +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 mfence +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - - - - - - - minpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.50 - 3.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - minpd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - - - - - - - minsd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.50 - 3.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - minsd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 1.33 1.33 1.33 0.33 0.33 0.33 - - - - - - - - - - movapd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 1.00 1.00 - - 1.00 1.00 movapd %xmm0, (%rax) +# CHECK-NEXT: - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 - - movapd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 3.00 3.00 0.33 0.33 0.33 - - - - - - - - - - movd %eax, %xmm2 +# CHECK-NEXT: - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 - - movd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.00 - - 1.00 - - - - - - - - - - - - movd %xmm0, %ecx +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 0.50 0.50 - - 0.50 0.50 movd %xmm0, (%rax) +# CHECK-NEXT: - - - - - - - 2.00 2.00 2.00 0.33 0.33 0.33 - - - - - - - - - - movdqa %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 1.00 1.00 - - 1.00 1.00 movdqa %xmm0, (%rax) +# CHECK-NEXT: - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 - - movdqa (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.00 2.00 2.00 0.33 0.33 0.33 - - - - - - - - - - movdqu %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 1.00 1.00 - - 1.00 1.00 movdqu %xmm0, (%rax) +# CHECK-NEXT: - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 - - movdqu (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.00 2.00 2.00 0.33 0.33 0.33 - - - - - - - - - - movdq2q %xmm0, %mm2 +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 0.50 0.50 - - 0.50 0.50 movhpd %xmm0, (%rax) +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - movhpd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 0.50 0.50 - - 0.50 0.50 movlpd %xmm0, (%rax) +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - movlpd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.00 - - 1.00 - - - - - - - - - - - - movmskpd %xmm0, %ecx +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 movntil %eax, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 movntiq %rax, (%rax) +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 0.50 0.50 - - 0.50 0.50 movntdq %xmm0, (%rax) +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 1.00 1.00 - - 1.00 1.00 movntpd %xmm0, (%rax) +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - movq %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 3.00 3.00 0.33 0.33 0.33 - - - - - - - - - - movq %rax, %xmm2 +# CHECK-NEXT: - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 - - movq (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.00 - - 1.00 - - - - - - - - - - - - movq %xmm0, %rcx +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 0.50 0.50 - - 0.50 0.50 movq %xmm0, (%rax) +# CHECK-NEXT: - - - - - - - 2.00 2.00 2.00 0.33 0.33 0.33 - - - - - - - - - - movq2dq %mm0, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - movsd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 0.50 0.50 - - 0.50 0.50 movsd %xmm0, (%rax) +# CHECK-NEXT: - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 - - movsd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 1.33 1.33 1.33 0.33 0.33 0.33 - - - - - - - - - - movupd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 1.00 1.00 - - 1.00 1.00 movupd %xmm0, (%rax) +# CHECK-NEXT: - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 - - movupd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - mulpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - mulpd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - mulsd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - mulsd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - orpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - orpd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - packssdw %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - packssdw (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - packsswb %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - packsswb (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - packuswb %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - packuswb (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - paddb %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - paddb (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - paddd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - paddd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - paddq %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - paddq (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - paddq %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - paddq (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - paddsb %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - paddsb (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - paddsw %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - paddsw (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - paddusb %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - paddusb (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - paddusw %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - paddusw (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - paddw %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - paddw (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pand %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pand (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pandn %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pandn (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pavgb %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pavgb (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pavgw %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pavgw (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pcmpeqb %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pcmpeqb (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pcmpeqd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pcmpeqd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pcmpeqw %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pcmpeqw (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pcmpgtb %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pcmpgtb (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pcmpgtd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pcmpgtd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pcmpgtw %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pcmpgtw (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 5.00 - 5.00 0.50 0.50 - - - - - - - - - - - pextrw $1, %xmm0, %ecx +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - - - - - - - pinsrw $1, %eax, %xmm0 +# CHECK-NEXT: - - - - - - - 4.00 - 4.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pinsrw $1, (%rax), %xmm0 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pmaddwd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pmaddwd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pmaxsw %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pmaxsw (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pmaxub %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pmaxub (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pminsw %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pminsw (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pminub %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pminub (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pmovmskb %xmm0, %ecx +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pmulhuw %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pmulhuw (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pmulhw %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pmulhw (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pmullw %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pmullw (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - pmuludq %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pmuludq (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pmuludq %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pmuludq (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - por %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - por (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - psadbw %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psadbw (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pshufd $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pshufd $1, (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pshufhw $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pshufhw $1, (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pshuflw $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pshuflw $1, (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - - - - - - - pslld $1, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pslld %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pslld (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pslldq $1, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - - - - - - - psllq $1, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - psllq %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psllq (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - - - - - - - psllw $1, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - psllw %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psllw (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - - - - - - - psrad $1, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - psrad %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psrad (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - - - - - - - psraw $1, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - psraw %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psraw (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - - - - - - - psrld $1, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - psrld %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psrld (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - psrldq $1, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - - - - - - - psrlq $1, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - psrlq %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psrlq (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - - - - - - - psrlw $1, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - psrlw %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psrlw (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - psubb %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psubb (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - psubd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psubd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 1.50 - 1.50 0.50 0.50 - - - - - - - - - - - psubq %mm0, %mm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psubq (%rax), %mm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - psubq %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psubq (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - psubsb %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psubsb (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - psubsw %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psubsw (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - psubusb %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psubusb (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - psubusw %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psubusw (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - psubw %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - psubw (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - punpckhbw %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - punpckhbw (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - punpckhdq %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - punpckhdq (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - punpckhqdq %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - punpckhqdq (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - punpckhwd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - punpckhwd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - punpcklbw %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - punpcklbw (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - punpckldq %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - punpckldq (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - punpcklqdq %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - punpcklqdq (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - punpcklwd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - punpcklwd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - pxor %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - pxor (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - shufpd $1, %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - shufpd $1, (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - - - 24.00 - 1.00 - - - - - - - - - - - sqrtpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - - - 25.00 - 1.00 - - - - - 0.50 0.50 0.50 0.50 - - sqrtpd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - - - 24.00 - 1.00 - - - - - - - - - - - sqrtsd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - - - 25.00 - 1.00 - - - - - 0.50 0.50 0.50 0.50 - - sqrtsd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - subpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - subpd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - subsd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - subsd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - ucomisd %xmm0, %xmm1 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - ucomisd (%rax), %xmm1 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - unpckhpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - unpckhpd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - unpcklpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - unpcklpd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - xorpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - xorpd (%rax), %xmm2 diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse3.s b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse3.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse3.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse3.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -instruction-tables < %s | FileCheck %s addsubpd %xmm0, %xmm2 addsubpd (%rax), %xmm2 @@ -43,62 +43,77 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 3 1.00 addsubpd %xmm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * addsubpd (%rax), %xmm2 -# CHECK-NEXT: 1 3 1.00 addsubps %xmm0, %xmm2 -# CHECK-NEXT: 2 9 1.00 * addsubps (%rax), %xmm2 -# CHECK-NEXT: 3 5 2.00 haddpd %xmm0, %xmm2 -# CHECK-NEXT: 4 11 2.00 * haddpd (%rax), %xmm2 -# CHECK-NEXT: 3 5 2.00 haddps %xmm0, %xmm2 -# CHECK-NEXT: 4 11 2.00 * haddps (%rax), %xmm2 -# CHECK-NEXT: 3 5 2.00 hsubpd %xmm0, %xmm2 -# CHECK-NEXT: 4 11 2.00 * hsubpd (%rax), %xmm2 -# CHECK-NEXT: 3 5 2.00 hsubps %xmm0, %xmm2 -# CHECK-NEXT: 4 11 2.00 * hsubps (%rax), %xmm2 -# CHECK-NEXT: 1 6 0.50 * lddqu (%rax), %xmm2 -# CHECK-NEXT: 1 100 0.33 U monitor -# CHECK-NEXT: 1 1 1.00 movddup %xmm0, %xmm2 -# CHECK-NEXT: 1 6 0.50 * movddup (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 movshdup %xmm0, %xmm2 -# CHECK-NEXT: 1 6 0.50 * movshdup (%rax), %xmm2 -# CHECK-NEXT: 1 1 1.00 movsldup %xmm0, %xmm2 -# CHECK-NEXT: 1 6 0.50 * movsldup (%rax), %xmm2 -# CHECK-NEXT: 1 100 0.33 * * U mwait +# CHECK-NEXT: 1 4 2.50 addsubpd %xmm0, %xmm2 +# CHECK-NEXT: 1 6 3.00 * addsubpd (%rax), %xmm2 +# CHECK-NEXT: 1 4 2.00 addsubps %xmm0, %xmm2 +# CHECK-NEXT: 1 6 2.50 * addsubps (%rax), %xmm2 +# CHECK-NEXT: 1 5 2.50 haddpd %xmm0, %xmm2 +# CHECK-NEXT: 1 7 3.00 * haddpd (%rax), %xmm2 +# CHECK-NEXT: 1 5 2.50 haddps %xmm0, %xmm2 +# CHECK-NEXT: 1 7 3.00 * haddps (%rax), %xmm2 +# CHECK-NEXT: 1 5 2.50 hsubpd %xmm0, %xmm2 +# CHECK-NEXT: 1 7 3.00 * hsubpd (%rax), %xmm2 +# CHECK-NEXT: 1 5 2.50 hsubps %xmm0, %xmm2 +# CHECK-NEXT: 1 7 3.00 * hsubps (%rax), %xmm2 +# CHECK-NEXT: 1 2 0.50 * lddqu (%rax), %xmm2 +# CHECK-NEXT: 1 100 42.00 U monitor +# CHECK-NEXT: 1 3 2.50 movddup %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * movddup (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 movshdup %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * movshdup (%rax), %xmm2 +# CHECK-NEXT: 1 3 2.50 movsldup %xmm0, %xmm2 +# CHECK-NEXT: 1 5 3.00 * movsldup (%rax), %xmm2 +# CHECK-NEXT: 1 100 42.00 * * U mwait # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - 0.67 12.67 - 19.67 5.00 5.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - 84.00 84.00 84.00 48.83 0.33 48.83 9.33 9.33 0.33 - 0.67 0.67 0.67 5.00 5.00 5.00 5.00 - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - 1.00 - - - - addsubpd %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 addsubpd (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - - - - addsubps %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 addsubps (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - 2.00 - - haddpd %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - 2.00 0.50 0.50 haddpd (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - 2.00 - - haddps %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - 2.00 0.50 0.50 haddps (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - 2.00 - - hsubpd %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - 2.00 0.50 0.50 hsubpd (%rax), %xmm2 -# CHECK-NEXT: - - - 1.00 - 2.00 - - hsubps %xmm0, %xmm2 -# CHECK-NEXT: - - - 1.00 - 2.00 0.50 0.50 hsubps (%rax), %xmm2 -# CHECK-NEXT: - - - - - - 0.50 0.50 lddqu (%rax), %xmm2 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - monitor -# CHECK-NEXT: - - - - - 1.00 - - movddup %xmm0, %xmm2 -# CHECK-NEXT: - - - - - - 0.50 0.50 movddup (%rax), %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - movshdup %xmm0, %xmm2 -# CHECK-NEXT: - - - - - - 0.50 0.50 movshdup (%rax), %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - movsldup %xmm0, %xmm2 -# CHECK-NEXT: - - - - - - 0.50 0.50 movsldup (%rax), %xmm2 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - mwait +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - addsubpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - addsubpd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - addsubps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - addsubps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - haddpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - haddpd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - haddps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - haddps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - hsubpd %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - hsubpd (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - hsubps %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - hsubps (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 0.33 0.33 0.33 0.33 0.33 0.33 - - - - 0.50 0.50 0.50 0.50 - - lddqu (%rax), %xmm2 +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - monitor +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - movddup %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - movddup (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - movshdup %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - movshdup (%rax), %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - movsldup %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - movsldup (%rax), %xmm2 +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - mwait diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse4a.s b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse4a.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse4a.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-sse4a.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -instruction-tables < %s | FileCheck %s extrq %xmm0, %xmm2 extrq $22, $2, %xmm2 @@ -19,32 +19,47 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 1 0.50 extrq %xmm0, %xmm2 -# CHECK-NEXT: 1 1 0.50 extrq $22, $2, %xmm2 -# CHECK-NEXT: 1 1 0.50 insertq %xmm0, %xmm2 -# CHECK-NEXT: 1 1 0.50 insertq $22, $22, %xmm0, %xmm2 -# CHECK-NEXT: 1 1 1.00 * movntsd %xmm0, (%rax) -# CHECK-NEXT: 1 1 1.00 * movntss %xmm0, (%rax) +# CHECK-NEXT: 1 3 2.50 extrq %xmm0, %xmm2 +# CHECK-NEXT: 1 3 2.50 extrq $22, $2, %xmm2 +# CHECK-NEXT: 3 3 2.50 insertq %xmm0, %xmm2 +# CHECK-NEXT: 3 3 2.50 insertq $22, $22, %xmm0, %xmm2 +# CHECK-NEXT: 1 4 1.00 * movntsd %xmm0, (%rax) +# CHECK-NEXT: 1 4 1.00 * movntss %xmm0, (%rax) # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - 2.00 2.00 2.00 1.00 1.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - - - - 10.00 2.00 10.00 2.00 2.00 2.00 - - - - 1.00 1.00 - - 1.00 1.00 # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - 0.50 - 0.50 - - extrq %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - extrq $22, $2, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - insertq %xmm0, %xmm2 -# CHECK-NEXT: - - - 0.50 - 0.50 - - insertq $22, $22, %xmm0, %xmm2 -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movntsd %xmm0, (%rax) -# CHECK-NEXT: - - - - 1.00 - 0.50 0.50 movntss %xmm0, (%rax) +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - extrq %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - extrq $22, $2, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - insertq %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - insertq $22, $22, %xmm0, %xmm2 +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 0.50 0.50 - - 0.50 0.50 movntsd %xmm0, (%rax) +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 0.50 0.50 - - 0.50 0.50 movntss %xmm0, (%rax) diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-x86_32.s b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-x86_32.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-x86_32.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-x86_32.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=i686-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=i686-unknown-unknown -mcpu=barcelona -instruction-tables < %s | FileCheck %s aaa @@ -33,46 +33,61 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 100 0.33 aaa -# CHECK-NEXT: 1 100 0.33 aad -# CHECK-NEXT: 1 100 0.33 aad $7 -# CHECK-NEXT: 1 100 0.33 aam -# CHECK-NEXT: 1 100 0.33 aam $7 -# CHECK-NEXT: 1 100 0.33 aas -# CHECK-NEXT: 1 100 0.33 U bound %bx, (%eax) -# CHECK-NEXT: 1 100 0.33 U bound %ebx, (%eax) -# CHECK-NEXT: 1 100 0.33 daa -# CHECK-NEXT: 1 100 0.33 das -# CHECK-NEXT: 1 100 0.33 U into -# CHECK-NEXT: 3 7 0.67 * leave -# CHECK-NEXT: 1 1 0.33 U salc +# CHECK-NEXT: 13 100 9.00 aaa +# CHECK-NEXT: 13 100 9.00 aad +# CHECK-NEXT: 13 100 9.00 aad $7 +# CHECK-NEXT: 13 100 9.00 aam +# CHECK-NEXT: 13 100 9.00 aam $7 +# CHECK-NEXT: 13 100 9.00 aas +# CHECK-NEXT: 1 100 42.00 U bound %bx, (%eax) +# CHECK-NEXT: 1 100 42.00 U bound %ebx, (%eax) +# CHECK-NEXT: 13 100 9.00 daa +# CHECK-NEXT: 13 100 9.00 das +# CHECK-NEXT: 1 100 42.00 U into +# CHECK-NEXT: 1 2 1.00 * leave +# CHECK-NEXT: 1 2 1.00 U salc # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - 4.67 4.67 - 4.67 0.50 0.50 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - 200.00 200.00 200.00 - - - - - - - 4.33 4.33 4.33 - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aaa -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aad -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aad $7 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aam -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aam $7 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - aas -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - bound %bx, (%eax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - bound %ebx, (%eax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - daa -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - das -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - into -# CHECK-NEXT: - - 0.67 0.67 - 0.67 0.50 0.50 leave -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - salc +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - aaa +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - aad +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - aad $7 +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - aam +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - aam $7 +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - aas +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - bound %bx, (%eax) +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - bound %ebx, (%eax) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - daa +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - das +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - into +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - leave +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - salc diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-x86_64.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-x86_64.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-x86_64.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -instruction-tables < %s | FileCheck %s adcb $0, %al adcb $0, %dil @@ -899,1578 +899,1593 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 2 2 0.67 adcb $0, %al -# CHECK-NEXT: 2 2 0.67 adcb $0, %dil -# CHECK-NEXT: 6 9 1.00 * * adcb $0, (%rax) -# CHECK-NEXT: 2 2 0.67 adcb $7, %al -# CHECK-NEXT: 2 2 0.67 adcb $7, %dil -# CHECK-NEXT: 6 9 1.00 * * adcb $7, (%rax) -# CHECK-NEXT: 2 2 0.67 adcb %sil, %dil -# CHECK-NEXT: 6 9 1.00 * * adcb %sil, (%rax) -# CHECK-NEXT: 3 7 0.67 * adcb (%rax), %dil -# CHECK-NEXT: 2 2 0.67 adcw $0, %ax -# CHECK-NEXT: 2 2 0.67 adcw $0, %di -# CHECK-NEXT: 6 9 1.00 * * adcw $0, (%rax) -# CHECK-NEXT: 2 2 0.67 adcw $511, %ax -# CHECK-NEXT: 2 2 0.67 adcw $511, %di -# CHECK-NEXT: 6 9 1.00 * * adcw $511, (%rax) -# CHECK-NEXT: 2 2 0.67 adcw $7, %di -# CHECK-NEXT: 6 9 1.00 * * adcw $7, (%rax) -# CHECK-NEXT: 2 2 0.67 adcw %si, %di -# CHECK-NEXT: 6 9 1.00 * * adcw %si, (%rax) -# CHECK-NEXT: 3 7 0.67 * adcw (%rax), %di -# CHECK-NEXT: 2 2 0.67 adcl $0, %eax -# CHECK-NEXT: 2 2 0.67 adcl $0, %edi -# CHECK-NEXT: 6 9 1.00 * * adcl $0, (%rax) -# CHECK-NEXT: 2 2 0.67 adcl $665536, %eax -# CHECK-NEXT: 2 2 0.67 adcl $665536, %edi -# CHECK-NEXT: 6 9 1.00 * * adcl $665536, (%rax) -# CHECK-NEXT: 2 2 0.67 adcl $7, %edi -# CHECK-NEXT: 6 9 1.00 * * adcl $7, (%rax) -# CHECK-NEXT: 2 2 0.67 adcl %esi, %edi -# CHECK-NEXT: 6 9 1.00 * * adcl %esi, (%rax) -# CHECK-NEXT: 3 7 0.67 * adcl (%rax), %edi -# CHECK-NEXT: 2 2 0.67 adcq $0, %rax -# CHECK-NEXT: 2 2 0.67 adcq $0, %rdi -# CHECK-NEXT: 6 9 1.00 * * adcq $0, (%rax) -# CHECK-NEXT: 2 2 0.67 adcq $665536, %rax -# CHECK-NEXT: 2 2 0.67 adcq $665536, %rdi -# CHECK-NEXT: 6 9 1.00 * * adcq $665536, (%rax) -# CHECK-NEXT: 2 2 0.67 adcq $7, %rdi -# CHECK-NEXT: 6 9 1.00 * * adcq $7, (%rax) -# CHECK-NEXT: 2 2 0.67 adcq %rsi, %rdi -# CHECK-NEXT: 6 9 1.00 * * adcq %rsi, (%rax) -# CHECK-NEXT: 3 7 0.67 * adcq (%rax), %rdi -# CHECK-NEXT: 1 1 0.33 addb $7, %al -# CHECK-NEXT: 1 1 0.33 addb $7, %dil -# CHECK-NEXT: 3 7 1.00 * * addb $7, (%rax) -# CHECK-NEXT: 1 1 0.33 addb %sil, %dil -# CHECK-NEXT: 3 7 1.00 * * addb %sil, (%rax) -# CHECK-NEXT: 2 6 0.50 * addb (%rax), %dil -# CHECK-NEXT: 1 1 0.33 addw $511, %ax -# CHECK-NEXT: 1 1 0.33 addw $511, %di -# CHECK-NEXT: 3 7 1.00 * * addw $511, (%rax) -# CHECK-NEXT: 1 1 0.33 addw $7, %di -# CHECK-NEXT: 3 7 1.00 * * addw $7, (%rax) -# CHECK-NEXT: 1 1 0.33 addw %si, %di -# CHECK-NEXT: 3 7 1.00 * * addw %si, (%rax) -# CHECK-NEXT: 2 6 0.50 * addw (%rax), %di -# CHECK-NEXT: 1 1 0.33 addl $665536, %eax -# CHECK-NEXT: 1 1 0.33 addl $665536, %edi -# CHECK-NEXT: 3 7 1.00 * * addl $665536, (%rax) -# CHECK-NEXT: 1 1 0.33 addl $7, %edi -# CHECK-NEXT: 3 7 1.00 * * addl $7, (%rax) -# CHECK-NEXT: 1 1 0.33 addl %esi, %edi -# CHECK-NEXT: 3 7 1.00 * * addl %esi, (%rax) -# CHECK-NEXT: 2 6 0.50 * addl (%rax), %edi -# CHECK-NEXT: 1 1 0.33 addq $665536, %rax -# CHECK-NEXT: 1 1 0.33 addq $665536, %rdi -# CHECK-NEXT: 3 7 1.00 * * addq $665536, (%rax) -# CHECK-NEXT: 1 1 0.33 addq $7, %rdi -# CHECK-NEXT: 3 7 1.00 * * addq $7, (%rax) -# CHECK-NEXT: 1 1 0.33 addq %rsi, %rdi -# CHECK-NEXT: 3 7 1.00 * * addq %rsi, (%rax) -# CHECK-NEXT: 2 6 0.50 * addq (%rax), %rdi -# CHECK-NEXT: 1 1 0.33 andb $7, %al -# CHECK-NEXT: 1 1 0.33 andb $7, %dil -# CHECK-NEXT: 3 7 1.00 * * andb $7, (%rax) -# CHECK-NEXT: 1 1 0.33 andb %sil, %dil -# CHECK-NEXT: 3 7 1.00 * * andb %sil, (%rax) -# CHECK-NEXT: 2 6 0.50 * andb (%rax), %dil -# CHECK-NEXT: 1 1 0.33 andw $511, %ax -# CHECK-NEXT: 1 1 0.33 andw $511, %di -# CHECK-NEXT: 3 7 1.00 * * andw $511, (%rax) -# CHECK-NEXT: 1 1 0.33 andw $7, %di -# CHECK-NEXT: 3 7 1.00 * * andw $7, (%rax) -# CHECK-NEXT: 1 1 0.33 andw %si, %di -# CHECK-NEXT: 3 7 1.00 * * andw %si, (%rax) -# CHECK-NEXT: 2 6 0.50 * andw (%rax), %di -# CHECK-NEXT: 1 1 0.33 andl $665536, %eax -# CHECK-NEXT: 1 1 0.33 andl $665536, %edi -# CHECK-NEXT: 3 7 1.00 * * andl $665536, (%rax) -# CHECK-NEXT: 1 1 0.33 andl $7, %edi -# CHECK-NEXT: 3 7 1.00 * * andl $7, (%rax) -# CHECK-NEXT: 1 1 0.33 andl %esi, %edi -# CHECK-NEXT: 3 7 1.00 * * andl %esi, (%rax) -# CHECK-NEXT: 2 6 0.50 * andl (%rax), %edi -# CHECK-NEXT: 1 1 0.33 andq $665536, %rax -# CHECK-NEXT: 1 1 0.33 andq $665536, %rdi -# CHECK-NEXT: 3 7 1.00 * * andq $665536, (%rax) -# CHECK-NEXT: 1 1 0.33 andq $7, %rdi -# CHECK-NEXT: 3 7 1.00 * * andq $7, (%rax) -# CHECK-NEXT: 1 1 0.33 andq %rsi, %rdi -# CHECK-NEXT: 3 7 1.00 * * andq %rsi, (%rax) -# CHECK-NEXT: 2 6 0.50 * andq (%rax), %rdi -# CHECK-NEXT: 1 3 1.00 bsfw %si, %di -# CHECK-NEXT: 1 3 1.00 bsrw %si, %di -# CHECK-NEXT: 2 8 1.00 * bsfw (%rax), %di -# CHECK-NEXT: 2 8 1.00 * bsrw (%rax), %di -# CHECK-NEXT: 1 3 1.00 bsfl %esi, %edi -# CHECK-NEXT: 1 3 1.00 bsrl %esi, %edi -# CHECK-NEXT: 2 8 1.00 * bsfl (%rax), %edi -# CHECK-NEXT: 2 8 1.00 * bsrl (%rax), %edi -# CHECK-NEXT: 1 3 1.00 bsfq %rsi, %rdi -# CHECK-NEXT: 1 3 1.00 bsrq %rsi, %rdi -# CHECK-NEXT: 2 8 1.00 * bsfq (%rax), %rdi -# CHECK-NEXT: 2 8 1.00 * bsrq (%rax), %rdi -# CHECK-NEXT: 1 1 1.00 bswapl %eax -# CHECK-NEXT: 2 2 1.00 bswapq %rax -# CHECK-NEXT: 1 1 0.50 btw %si, %di -# CHECK-NEXT: 1 1 0.50 btcw %si, %di -# CHECK-NEXT: 1 1 0.50 btrw %si, %di -# CHECK-NEXT: 1 1 0.50 btsw %si, %di -# CHECK-NEXT: 6 9 1.00 * btw %si, (%rax) -# CHECK-NEXT: 6 9 1.00 * * btcw %si, (%rax) -# CHECK-NEXT: 6 9 1.00 * * btrw %si, (%rax) -# CHECK-NEXT: 6 9 1.00 * * btsw %si, (%rax) -# CHECK-NEXT: 1 1 0.50 btw $7, %di -# CHECK-NEXT: 1 1 0.50 btcw $7, %di -# CHECK-NEXT: 1 1 0.50 btrw $7, %di -# CHECK-NEXT: 1 1 0.50 btsw $7, %di -# CHECK-NEXT: 2 6 0.50 * btw $7, (%rax) -# CHECK-NEXT: 4 7 1.00 * * btcw $7, (%rax) -# CHECK-NEXT: 4 7 1.00 * * btrw $7, (%rax) -# CHECK-NEXT: 4 7 1.00 * * btsw $7, (%rax) -# CHECK-NEXT: 1 1 0.50 btl %esi, %edi -# CHECK-NEXT: 1 1 0.50 btcl %esi, %edi -# CHECK-NEXT: 1 1 0.50 btrl %esi, %edi -# CHECK-NEXT: 1 1 0.50 btsl %esi, %edi -# CHECK-NEXT: 6 9 1.00 * btl %esi, (%rax) -# CHECK-NEXT: 6 9 1.00 * * btcl %esi, (%rax) -# CHECK-NEXT: 6 9 1.00 * * btrl %esi, (%rax) -# CHECK-NEXT: 6 9 1.00 * * btsl %esi, (%rax) -# CHECK-NEXT: 1 1 0.50 btl $7, %edi -# CHECK-NEXT: 1 1 0.50 btcl $7, %edi -# CHECK-NEXT: 1 1 0.50 btrl $7, %edi -# CHECK-NEXT: 1 1 0.50 btsl $7, %edi -# CHECK-NEXT: 2 6 0.50 * btl $7, (%rax) -# CHECK-NEXT: 4 7 1.00 * * btcl $7, (%rax) -# CHECK-NEXT: 4 7 1.00 * * btrl $7, (%rax) -# CHECK-NEXT: 4 7 1.00 * * btsl $7, (%rax) -# CHECK-NEXT: 1 1 0.50 btq %rsi, %rdi -# CHECK-NEXT: 1 1 0.50 btcq %rsi, %rdi -# CHECK-NEXT: 1 1 0.50 btrq %rsi, %rdi -# CHECK-NEXT: 1 1 0.50 btsq %rsi, %rdi -# CHECK-NEXT: 6 9 1.00 * btq %rsi, (%rax) -# CHECK-NEXT: 6 9 1.00 * * btcq %rsi, (%rax) -# CHECK-NEXT: 6 9 1.00 * * btrq %rsi, (%rax) -# CHECK-NEXT: 6 9 1.00 * * btsq %rsi, (%rax) -# CHECK-NEXT: 1 1 0.50 btq $7, %rdi -# CHECK-NEXT: 1 1 0.50 btcq $7, %rdi -# CHECK-NEXT: 1 1 0.50 btrq $7, %rdi -# CHECK-NEXT: 1 1 0.50 btsq $7, %rdi -# CHECK-NEXT: 2 6 0.50 * btq $7, (%rax) -# CHECK-NEXT: 4 7 1.00 * * btcq $7, (%rax) -# CHECK-NEXT: 4 7 1.00 * * btrq $7, (%rax) -# CHECK-NEXT: 4 7 1.00 * * btsq $7, (%rax) -# CHECK-NEXT: 1 1 0.33 cbtw -# CHECK-NEXT: 1 1 0.33 cwtl -# CHECK-NEXT: 1 1 0.33 cltq -# CHECK-NEXT: 2 2 1.00 cwtd -# CHECK-NEXT: 1 1 0.50 cltd -# CHECK-NEXT: 1 1 0.50 cqto -# CHECK-NEXT: 1 1 0.25 U clc -# CHECK-NEXT: 1 1 0.33 U cld -# CHECK-NEXT: 1 1 0.33 U cmc -# CHECK-NEXT: 1 1 0.33 cmpb $7, %al -# CHECK-NEXT: 1 1 0.33 cmpb $7, %dil -# CHECK-NEXT: 2 6 0.50 * cmpb $7, (%rax) -# CHECK-NEXT: 1 1 0.33 cmpb %sil, %dil -# CHECK-NEXT: 2 6 0.50 * cmpb %sil, (%rax) -# CHECK-NEXT: 2 6 0.50 * cmpb (%rax), %dil -# CHECK-NEXT: 1 1 0.33 cmpw $511, %ax -# CHECK-NEXT: 1 1 0.33 cmpw $511, %di -# CHECK-NEXT: 2 6 0.50 * cmpw $511, (%rax) -# CHECK-NEXT: 1 1 0.33 cmpw $7, %di -# CHECK-NEXT: 2 6 0.50 * cmpw $7, (%rax) -# CHECK-NEXT: 1 1 0.33 cmpw %si, %di -# CHECK-NEXT: 2 6 0.50 * cmpw %si, (%rax) -# CHECK-NEXT: 2 6 0.50 * cmpw (%rax), %di -# CHECK-NEXT: 1 1 0.33 cmpl $665536, %eax -# CHECK-NEXT: 1 1 0.33 cmpl $665536, %edi -# CHECK-NEXT: 2 6 0.50 * cmpl $665536, (%rax) -# CHECK-NEXT: 1 1 0.33 cmpl $7, %edi -# CHECK-NEXT: 2 6 0.50 * cmpl $7, (%rax) -# CHECK-NEXT: 1 1 0.33 cmpl %esi, %edi -# CHECK-NEXT: 2 6 0.50 * cmpl %esi, (%rax) -# CHECK-NEXT: 2 6 0.50 * cmpl (%rax), %edi -# CHECK-NEXT: 1 1 0.33 cmpq $665536, %rax -# CHECK-NEXT: 1 1 0.33 cmpq $665536, %rdi -# CHECK-NEXT: 2 6 0.50 * cmpq $665536, (%rax) -# CHECK-NEXT: 1 1 0.33 cmpq $7, %rdi -# CHECK-NEXT: 2 6 0.50 * cmpq $7, (%rax) -# CHECK-NEXT: 1 1 0.33 cmpq %rsi, %rdi -# CHECK-NEXT: 2 6 0.50 * cmpq %rsi, (%rax) -# CHECK-NEXT: 2 6 0.50 * cmpq (%rax), %rdi -# CHECK-NEXT: 5 8 1.00 U cmpsb %es:(%rdi), (%rsi) -# CHECK-NEXT: 5 8 1.00 U cmpsw %es:(%rdi), (%rsi) -# CHECK-NEXT: 5 8 1.00 U cmpsl %es:(%rdi), (%rsi) -# CHECK-NEXT: 5 8 1.00 U cmpsq %es:(%rdi), (%rsi) -# CHECK-NEXT: 4 5 1.33 cmpxchgb %cl, %bl -# CHECK-NEXT: 6 8 2.00 * * cmpxchgb %cl, (%rbx) -# CHECK-NEXT: 4 5 1.33 cmpxchgw %cx, %bx -# CHECK-NEXT: 6 8 2.00 * * cmpxchgw %cx, (%rbx) -# CHECK-NEXT: 4 5 1.33 cmpxchgl %ecx, %ebx -# CHECK-NEXT: 6 8 2.00 * * cmpxchgl %ecx, (%rbx) -# CHECK-NEXT: 4 5 1.33 cmpxchgq %rcx, %rbx -# CHECK-NEXT: 6 8 2.00 * * cmpxchgq %rcx, (%rbx) -# CHECK-NEXT: 1 100 0.33 U cpuid -# CHECK-NEXT: 1 1 0.33 decb %dil -# CHECK-NEXT: 3 7 1.00 * * decb (%rax) -# CHECK-NEXT: 1 1 0.33 decw %di -# CHECK-NEXT: 3 7 1.00 * * decw (%rax) -# CHECK-NEXT: 1 1 0.33 decl %edi -# CHECK-NEXT: 3 7 1.00 * * decl (%rax) -# CHECK-NEXT: 1 1 0.33 decq %rdi -# CHECK-NEXT: 3 7 1.00 * * decq (%rax) -# CHECK-NEXT: 1 25 10.00 U divb %dil -# CHECK-NEXT: 2 30 10.00 * U divb (%rax) -# CHECK-NEXT: 1 25 10.00 U divw %si -# CHECK-NEXT: 2 30 10.00 * U divw (%rax) -# CHECK-NEXT: 1 25 10.00 U divl %edx -# CHECK-NEXT: 2 30 10.00 * U divl (%rax) -# CHECK-NEXT: 1 25 10.00 U divq %rcx -# CHECK-NEXT: 2 30 10.00 * U divq (%rax) -# CHECK-NEXT: 1 100 0.33 U enter $7, $4095 -# CHECK-NEXT: 1 25 10.00 U idivb %dil -# CHECK-NEXT: 2 30 10.00 * U idivb (%rax) -# CHECK-NEXT: 1 25 10.00 U idivw %si -# CHECK-NEXT: 2 30 10.00 * U idivw (%rax) -# CHECK-NEXT: 1 25 10.00 U idivl %edx -# CHECK-NEXT: 2 30 10.00 * U idivl (%rax) -# CHECK-NEXT: 1 25 10.00 U idivq %rcx -# CHECK-NEXT: 2 30 10.00 * U idivq (%rax) -# CHECK-NEXT: 1 3 1.00 imulb %dil -# CHECK-NEXT: 2 8 1.00 * imulb (%rax) -# CHECK-NEXT: 4 4 1.33 imulw %di -# CHECK-NEXT: 5 9 1.33 * imulw (%rax) -# CHECK-NEXT: 1 3 1.00 imulw %si, %di -# CHECK-NEXT: 2 8 1.00 * imulw (%rax), %di -# CHECK-NEXT: 2 4 1.00 imulw $511, %si, %di -# CHECK-NEXT: 3 8 1.00 * imulw $511, (%rax), %di -# CHECK-NEXT: 2 4 1.00 imulw $7, %si, %di -# CHECK-NEXT: 3 8 1.00 * imulw $7, (%rax), %di -# CHECK-NEXT: 3 4 1.00 imull %edi -# CHECK-NEXT: 4 9 1.00 * imull (%rax) -# CHECK-NEXT: 1 3 1.00 imull %esi, %edi -# CHECK-NEXT: 2 8 1.00 * imull (%rax), %edi -# CHECK-NEXT: 1 3 1.00 imull $665536, %esi, %edi -# CHECK-NEXT: 2 8 1.00 * imull $665536, (%rax), %edi -# CHECK-NEXT: 1 3 1.00 imull $7, %esi, %edi -# CHECK-NEXT: 2 8 1.00 * imull $7, (%rax), %edi -# CHECK-NEXT: 2 4 1.00 imulq %rdi -# CHECK-NEXT: 3 9 1.00 * imulq (%rax) -# CHECK-NEXT: 1 3 1.00 imulq %rsi, %rdi -# CHECK-NEXT: 2 8 1.00 * imulq (%rax), %rdi -# CHECK-NEXT: 1 3 1.00 imulq $665536, %rsi, %rdi -# CHECK-NEXT: 2 8 1.00 * imulq $665536, (%rax), %rdi -# CHECK-NEXT: 1 3 1.00 imulq $7, %rsi, %rdi -# CHECK-NEXT: 2 8 1.00 * imulq $7, (%rax), %rdi -# CHECK-NEXT: 1 100 0.33 U inb $7, %al -# CHECK-NEXT: 1 100 0.33 U inb %dx, %al -# CHECK-NEXT: 1 100 0.33 U inw $7, %ax -# CHECK-NEXT: 1 100 0.33 U inw %dx, %ax -# CHECK-NEXT: 1 100 0.33 U inl $7, %eax -# CHECK-NEXT: 1 100 0.33 U inl %dx, %eax -# CHECK-NEXT: 1 1 0.33 incb %dil -# CHECK-NEXT: 3 7 1.00 * * incb (%rax) -# CHECK-NEXT: 1 1 0.33 incw %di -# CHECK-NEXT: 3 7 1.00 * * incw (%rax) -# CHECK-NEXT: 1 1 0.33 incl %edi -# CHECK-NEXT: 3 7 1.00 * * incl (%rax) -# CHECK-NEXT: 1 1 0.33 incq %rdi -# CHECK-NEXT: 3 7 1.00 * * incq (%rax) -# CHECK-NEXT: 1 100 0.33 U insb %dx, %es:(%rdi) -# CHECK-NEXT: 1 100 0.33 U insw %dx, %es:(%rdi) -# CHECK-NEXT: 1 100 0.33 U insl %dx, %es:(%rdi) -# CHECK-NEXT: 1 100 0.33 * * U int $7 -# CHECK-NEXT: 1 100 0.33 U invlpg (%rax) -# CHECK-NEXT: 1 100 0.33 U invlpga %rax, %ecx -# CHECK-NEXT: 1 1 0.50 lahf -# CHECK-NEXT: 3 7 0.67 * leave -# CHECK-NEXT: 3 7 0.67 U lodsb (%rsi), %al -# CHECK-NEXT: 3 7 0.67 U lodsw (%rsi), %ax -# CHECK-NEXT: 2 6 0.50 U lodsl (%rsi), %eax -# CHECK-NEXT: 2 6 0.50 U lodsq (%rsi), %rax -# CHECK-NEXT: 5 8 1.00 U movsb (%rsi), %es:(%rdi) -# CHECK-NEXT: 5 8 1.00 U movsw (%rsi), %es:(%rdi) -# CHECK-NEXT: 5 8 1.00 U movsl (%rsi), %es:(%rdi) -# CHECK-NEXT: 5 8 1.00 U movsq (%rsi), %es:(%rdi) -# CHECK-NEXT: 1 1 0.33 movsbw %al, %di -# CHECK-NEXT: 1 1 0.33 movzbw %al, %di -# CHECK-NEXT: 1 5 0.50 * movsbw (%rax), %di -# CHECK-NEXT: 1 5 0.50 * movzbw (%rax), %di -# CHECK-NEXT: 1 1 0.33 movsbl %al, %edi -# CHECK-NEXT: 1 1 0.33 movzbl %al, %edi -# CHECK-NEXT: 1 5 0.50 * movsbl (%rax), %edi -# CHECK-NEXT: 1 5 0.50 * movzbl (%rax), %edi -# CHECK-NEXT: 1 1 0.33 movsbq %al, %rdi -# CHECK-NEXT: 1 1 0.33 movzbq %al, %rdi -# CHECK-NEXT: 1 5 0.50 * movsbq (%rax), %rdi -# CHECK-NEXT: 1 5 0.50 * movzbq (%rax), %rdi -# CHECK-NEXT: 1 1 0.33 movswl %ax, %edi -# CHECK-NEXT: 1 1 0.33 movzwl %ax, %edi -# CHECK-NEXT: 1 5 0.50 * movswl (%rax), %edi -# CHECK-NEXT: 1 5 0.50 * movzwl (%rax), %edi -# CHECK-NEXT: 1 1 0.33 movswq %ax, %rdi -# CHECK-NEXT: 1 1 0.33 movzwq %ax, %rdi -# CHECK-NEXT: 1 5 0.50 * movswq (%rax), %rdi -# CHECK-NEXT: 1 5 0.50 * movzwq (%rax), %rdi -# CHECK-NEXT: 1 1 0.33 movslq %eax, %rdi -# CHECK-NEXT: 1 5 0.50 * movslq (%rax), %rdi -# CHECK-NEXT: 1 3 1.00 mulb %dil -# CHECK-NEXT: 2 8 1.00 * mulb (%rax) -# CHECK-NEXT: 4 4 1.33 mulw %si -# CHECK-NEXT: 5 9 1.33 * mulw (%rax) -# CHECK-NEXT: 3 4 1.00 mull %edx -# CHECK-NEXT: 4 9 1.00 * mull (%rax) -# CHECK-NEXT: 2 4 1.00 mulq %rcx -# CHECK-NEXT: 3 9 1.00 * mulq (%rax) -# CHECK-NEXT: 1 1 0.33 negb %dil -# CHECK-NEXT: 3 7 1.00 * * negb (%r8) -# CHECK-NEXT: 1 1 0.33 negw %si -# CHECK-NEXT: 3 7 1.00 * * negw (%r9) -# CHECK-NEXT: 1 1 0.33 negl %edx -# CHECK-NEXT: 3 7 1.00 * * negl (%rax) -# CHECK-NEXT: 1 1 0.33 negq %rcx -# CHECK-NEXT: 3 7 1.00 * * negq (%r10) -# CHECK-NEXT: 1 1 0.25 nop -# CHECK-NEXT: 1 1 0.25 nopw %di -# CHECK-NEXT: 1 1 0.25 nopw (%rcx) -# CHECK-NEXT: 1 1 0.25 nopl %esi -# CHECK-NEXT: 1 1 0.25 nopl (%r8) -# CHECK-NEXT: 1 1 0.25 nopq %rdx -# CHECK-NEXT: 1 1 0.25 nopq (%r9) -# CHECK-NEXT: 1 1 0.33 notb %dil -# CHECK-NEXT: 3 7 1.00 * * notb (%r8) -# CHECK-NEXT: 1 1 0.33 notw %si -# CHECK-NEXT: 3 7 1.00 * * notw (%r9) -# CHECK-NEXT: 1 1 0.33 notl %edx -# CHECK-NEXT: 3 7 1.00 * * notl (%rax) -# CHECK-NEXT: 1 1 0.33 notq %rcx -# CHECK-NEXT: 3 7 1.00 * * notq (%r10) -# CHECK-NEXT: 1 1 0.33 orb $7, %al -# CHECK-NEXT: 1 1 0.33 orb $7, %dil -# CHECK-NEXT: 3 7 1.00 * * orb $7, (%rax) -# CHECK-NEXT: 1 1 0.33 orb %sil, %dil -# CHECK-NEXT: 3 7 1.00 * * orb %sil, (%rax) -# CHECK-NEXT: 2 6 0.50 * orb (%rax), %dil -# CHECK-NEXT: 1 1 0.33 orw $511, %ax -# CHECK-NEXT: 1 1 0.33 orw $511, %di -# CHECK-NEXT: 3 7 1.00 * * orw $511, (%rax) -# CHECK-NEXT: 1 1 0.33 orw $7, %di -# CHECK-NEXT: 3 7 1.00 * * orw $7, (%rax) -# CHECK-NEXT: 1 1 0.33 orw %si, %di -# CHECK-NEXT: 3 7 1.00 * * orw %si, (%rax) -# CHECK-NEXT: 2 6 0.50 * orw (%rax), %di -# CHECK-NEXT: 1 1 0.33 orl $665536, %eax -# CHECK-NEXT: 1 1 0.33 orl $665536, %edi -# CHECK-NEXT: 3 7 1.00 * * orl $665536, (%rax) -# CHECK-NEXT: 1 1 0.33 orl $7, %edi -# CHECK-NEXT: 3 7 1.00 * * orl $7, (%rax) -# CHECK-NEXT: 1 1 0.33 orl %esi, %edi -# CHECK-NEXT: 3 7 1.00 * * orl %esi, (%rax) -# CHECK-NEXT: 2 6 0.50 * orl (%rax), %edi -# CHECK-NEXT: 1 1 0.33 orq $665536, %rax -# CHECK-NEXT: 1 1 0.33 orq $665536, %rdi -# CHECK-NEXT: 3 7 1.00 * * orq $665536, (%rax) -# CHECK-NEXT: 1 1 0.33 orq $7, %rdi -# CHECK-NEXT: 3 7 1.00 * * orq $7, (%rax) -# CHECK-NEXT: 1 1 0.33 orq %rsi, %rdi -# CHECK-NEXT: 3 7 1.00 * * orq %rsi, (%rax) -# CHECK-NEXT: 2 6 0.50 * orq (%rax), %rdi -# CHECK-NEXT: 1 100 0.33 U outb %al, $7 -# CHECK-NEXT: 1 100 0.33 U outb %al, %dx -# CHECK-NEXT: 1 100 0.33 U outw %ax, $7 -# CHECK-NEXT: 1 100 0.33 U outw %ax, %dx -# CHECK-NEXT: 1 100 0.33 U outl %eax, $7 -# CHECK-NEXT: 1 100 0.33 U outl %eax, %dx -# CHECK-NEXT: 1 100 0.33 U outsb (%rsi), %dx -# CHECK-NEXT: 1 100 0.33 U outsw (%rsi), %dx -# CHECK-NEXT: 1 100 0.33 U outsl (%rsi), %dx -# CHECK-NEXT: 4 4 1.33 * * U pause -# CHECK-NEXT: 3 2 1.50 rclb %dil -# CHECK-NEXT: 3 2 1.50 rcrb %dil -# CHECK-NEXT: 11 11 3.50 * rclb (%rax) -# CHECK-NEXT: 11 11 3.50 * rcrb (%rax) -# CHECK-NEXT: 8 5 4.00 rclb $7, %dil -# CHECK-NEXT: 8 5 4.00 rcrb $7, %dil -# CHECK-NEXT: 11 11 3.50 * rclb $7, (%rax) -# CHECK-NEXT: 11 11 3.50 * rcrb $7, (%rax) -# CHECK-NEXT: 8 5 4.00 rclb %cl, %dil -# CHECK-NEXT: 8 5 4.00 rcrb %cl, %dil -# CHECK-NEXT: 11 11 3.50 * rclb %cl, (%rax) -# CHECK-NEXT: 11 11 3.50 * rcrb %cl, (%rax) -# CHECK-NEXT: 3 2 1.50 rclw %di -# CHECK-NEXT: 3 2 1.50 rcrw %di -# CHECK-NEXT: 11 11 3.50 * rclw (%rax) -# CHECK-NEXT: 11 11 3.50 * rcrw (%rax) -# CHECK-NEXT: 8 5 4.00 rclw $7, %di -# CHECK-NEXT: 8 5 4.00 rcrw $7, %di -# CHECK-NEXT: 11 11 3.50 * rclw $7, (%rax) -# CHECK-NEXT: 11 11 3.50 * rcrw $7, (%rax) -# CHECK-NEXT: 8 5 4.00 rclw %cl, %di -# CHECK-NEXT: 8 5 4.00 rcrw %cl, %di -# CHECK-NEXT: 11 11 3.50 * rclw %cl, (%rax) -# CHECK-NEXT: 11 11 3.50 * rcrw %cl, (%rax) -# CHECK-NEXT: 3 2 1.50 rcll %edi -# CHECK-NEXT: 3 2 1.50 rcrl %edi -# CHECK-NEXT: 11 11 3.50 * rcll (%rax) -# CHECK-NEXT: 11 11 3.50 * rcrl (%rax) -# CHECK-NEXT: 8 5 4.00 rcll $7, %edi -# CHECK-NEXT: 8 5 4.00 rcrl $7, %edi -# CHECK-NEXT: 11 11 3.50 * rcll $7, (%rax) -# CHECK-NEXT: 11 11 3.50 * rcrl $7, (%rax) -# CHECK-NEXT: 8 5 4.00 rcll %cl, %edi -# CHECK-NEXT: 8 5 4.00 rcrl %cl, %edi -# CHECK-NEXT: 11 11 3.50 * rcll %cl, (%rax) -# CHECK-NEXT: 11 11 3.50 * rcrl %cl, (%rax) -# CHECK-NEXT: 3 2 1.50 rclq %rdi -# CHECK-NEXT: 3 2 1.50 rcrq %rdi -# CHECK-NEXT: 11 11 3.50 * rclq (%rax) -# CHECK-NEXT: 11 11 3.50 * rcrq (%rax) -# CHECK-NEXT: 8 5 4.00 rclq $7, %rdi -# CHECK-NEXT: 8 5 4.00 rcrq $7, %rdi -# CHECK-NEXT: 11 11 3.50 * rclq $7, (%rax) -# CHECK-NEXT: 11 11 3.50 * rcrq $7, (%rax) -# CHECK-NEXT: 8 5 4.00 rclq %cl, %rdi -# CHECK-NEXT: 8 5 4.00 rcrq %cl, %rdi -# CHECK-NEXT: 11 11 3.50 * rclq %cl, (%rax) -# CHECK-NEXT: 11 11 3.50 * rcrq %cl, (%rax) -# CHECK-NEXT: 1 100 0.33 U rdmsr -# CHECK-NEXT: 1 100 0.33 U rdpmc -# CHECK-NEXT: 1 100 0.33 U rdtsc -# CHECK-NEXT: 1 100 0.33 U rdtscp -# CHECK-NEXT: 2 2 1.00 rolb %dil -# CHECK-NEXT: 2 2 1.00 rorb %dil -# CHECK-NEXT: 5 8 1.00 * * rolb (%rax) -# CHECK-NEXT: 5 8 1.00 * * rorb (%rax) -# CHECK-NEXT: 2 2 1.00 rolb $7, %dil -# CHECK-NEXT: 2 2 1.00 rorb $7, %dil -# CHECK-NEXT: 5 8 1.00 * * rolb $7, (%rax) -# CHECK-NEXT: 5 8 1.00 * * rorb $7, (%rax) -# CHECK-NEXT: 3 3 1.50 rolb %cl, %dil -# CHECK-NEXT: 3 3 1.50 rorb %cl, %dil -# CHECK-NEXT: 6 9 1.50 * * rolb %cl, (%rax) -# CHECK-NEXT: 6 9 1.50 * * rorb %cl, (%rax) -# CHECK-NEXT: 2 2 1.00 rolw %di -# CHECK-NEXT: 2 2 1.00 rorw %di -# CHECK-NEXT: 5 8 1.00 * * rolw (%rax) -# CHECK-NEXT: 5 8 1.00 * * rorw (%rax) -# CHECK-NEXT: 2 2 1.00 rolw $7, %di -# CHECK-NEXT: 2 2 1.00 rorw $7, %di -# CHECK-NEXT: 5 8 1.00 * * rolw $7, (%rax) -# CHECK-NEXT: 5 8 1.00 * * rorw $7, (%rax) -# CHECK-NEXT: 3 3 1.50 rolw %cl, %di -# CHECK-NEXT: 3 3 1.50 rorw %cl, %di -# CHECK-NEXT: 6 9 1.50 * * rolw %cl, (%rax) -# CHECK-NEXT: 6 9 1.50 * * rorw %cl, (%rax) -# CHECK-NEXT: 2 2 1.00 roll %edi -# CHECK-NEXT: 2 2 1.00 rorl %edi -# CHECK-NEXT: 5 8 1.00 * * roll (%rax) -# CHECK-NEXT: 5 8 1.00 * * rorl (%rax) -# CHECK-NEXT: 2 2 1.00 roll $7, %edi -# CHECK-NEXT: 2 2 1.00 rorl $7, %edi -# CHECK-NEXT: 5 8 1.00 * * roll $7, (%rax) -# CHECK-NEXT: 5 8 1.00 * * rorl $7, (%rax) -# CHECK-NEXT: 3 3 1.50 roll %cl, %edi -# CHECK-NEXT: 3 3 1.50 rorl %cl, %edi -# CHECK-NEXT: 6 9 1.50 * * roll %cl, (%rax) -# CHECK-NEXT: 6 9 1.50 * * rorl %cl, (%rax) -# CHECK-NEXT: 2 2 1.00 rolq %rdi -# CHECK-NEXT: 2 2 1.00 rorq %rdi -# CHECK-NEXT: 5 8 1.00 * * rolq (%rax) -# CHECK-NEXT: 5 8 1.00 * * rorq (%rax) -# CHECK-NEXT: 2 2 1.00 rolq $7, %rdi -# CHECK-NEXT: 2 2 1.00 rorq $7, %rdi -# CHECK-NEXT: 5 8 1.00 * * rolq $7, (%rax) -# CHECK-NEXT: 5 8 1.00 * * rorq $7, (%rax) -# CHECK-NEXT: 3 3 1.50 rolq %cl, %rdi -# CHECK-NEXT: 3 3 1.50 rorq %cl, %rdi -# CHECK-NEXT: 6 9 1.50 * * rolq %cl, (%rax) -# CHECK-NEXT: 6 9 1.50 * * rorq %cl, (%rax) -# CHECK-NEXT: 1 1 0.50 sahf -# CHECK-NEXT: 1 1 0.50 sarb %dil -# CHECK-NEXT: 1 1 0.50 shlb %dil -# CHECK-NEXT: 1 1 0.50 shrb %dil -# CHECK-NEXT: 4 7 1.00 * * sarb (%rax) -# CHECK-NEXT: 4 7 1.00 * * shlb (%rax) -# CHECK-NEXT: 4 7 1.00 * * shrb (%rax) -# CHECK-NEXT: 1 1 0.50 sarb $7, %dil -# CHECK-NEXT: 1 1 0.50 shlb $7, %dil -# CHECK-NEXT: 1 1 0.50 shrb $7, %dil -# CHECK-NEXT: 4 7 1.00 * * sarb $7, (%rax) -# CHECK-NEXT: 4 7 1.00 * * shlb $7, (%rax) -# CHECK-NEXT: 4 7 1.00 * * shrb $7, (%rax) -# CHECK-NEXT: 3 3 1.50 sarb %cl, %dil -# CHECK-NEXT: 3 3 1.50 shlb %cl, %dil -# CHECK-NEXT: 3 3 1.50 shrb %cl, %dil -# CHECK-NEXT: 6 9 1.50 * * sarb %cl, (%rax) -# CHECK-NEXT: 6 9 1.50 * * shlb %cl, (%rax) -# CHECK-NEXT: 6 9 1.50 * * shrb %cl, (%rax) -# CHECK-NEXT: 1 1 0.50 sarw %di -# CHECK-NEXT: 1 1 0.50 shlw %di -# CHECK-NEXT: 1 1 0.50 shrw %di -# CHECK-NEXT: 4 7 1.00 * * sarw (%rax) -# CHECK-NEXT: 4 7 1.00 * * shlw (%rax) -# CHECK-NEXT: 4 7 1.00 * * shrw (%rax) -# CHECK-NEXT: 1 1 0.50 sarw $7, %di -# CHECK-NEXT: 1 1 0.50 shlw $7, %di -# CHECK-NEXT: 1 1 0.50 shrw $7, %di -# CHECK-NEXT: 4 7 1.00 * * sarw $7, (%rax) -# CHECK-NEXT: 4 7 1.00 * * shlw $7, (%rax) -# CHECK-NEXT: 4 7 1.00 * * shrw $7, (%rax) -# CHECK-NEXT: 3 3 1.50 sarw %cl, %di -# CHECK-NEXT: 3 3 1.50 shlw %cl, %di -# CHECK-NEXT: 3 3 1.50 shrw %cl, %di -# CHECK-NEXT: 6 9 1.50 * * sarw %cl, (%rax) -# CHECK-NEXT: 6 9 1.50 * * shlw %cl, (%rax) -# CHECK-NEXT: 6 9 1.50 * * shrw %cl, (%rax) -# CHECK-NEXT: 1 1 0.50 sarl %edi -# CHECK-NEXT: 1 1 0.50 shll %edi -# CHECK-NEXT: 1 1 0.50 shrl %edi -# CHECK-NEXT: 4 7 1.00 * * sarl (%rax) -# CHECK-NEXT: 4 7 1.00 * * shll (%rax) -# CHECK-NEXT: 4 7 1.00 * * shrl (%rax) -# CHECK-NEXT: 1 1 0.50 sarl $7, %edi -# CHECK-NEXT: 1 1 0.50 shll $7, %edi -# CHECK-NEXT: 1 1 0.50 shrl $7, %edi -# CHECK-NEXT: 4 7 1.00 * * sarl $7, (%rax) -# CHECK-NEXT: 4 7 1.00 * * shll $7, (%rax) -# CHECK-NEXT: 4 7 1.00 * * shrl $7, (%rax) -# CHECK-NEXT: 3 3 1.50 sarl %cl, %edi -# CHECK-NEXT: 3 3 1.50 shll %cl, %edi -# CHECK-NEXT: 3 3 1.50 shrl %cl, %edi -# CHECK-NEXT: 6 9 1.50 * * sarl %cl, (%rax) -# CHECK-NEXT: 6 9 1.50 * * shll %cl, (%rax) -# CHECK-NEXT: 6 9 1.50 * * shrl %cl, (%rax) -# CHECK-NEXT: 1 1 0.50 sarq %rdi -# CHECK-NEXT: 1 1 0.50 shlq %rdi -# CHECK-NEXT: 1 1 0.50 shrq %rdi -# CHECK-NEXT: 4 7 1.00 * * sarq (%rax) -# CHECK-NEXT: 4 7 1.00 * * shlq (%rax) -# CHECK-NEXT: 4 7 1.00 * * shrq (%rax) -# CHECK-NEXT: 1 1 0.50 sarq $7, %rdi -# CHECK-NEXT: 1 1 0.50 shlq $7, %rdi -# CHECK-NEXT: 1 1 0.50 shrq $7, %rdi -# CHECK-NEXT: 4 7 1.00 * * sarq $7, (%rax) -# CHECK-NEXT: 4 7 1.00 * * shlq $7, (%rax) -# CHECK-NEXT: 4 7 1.00 * * shrq $7, (%rax) -# CHECK-NEXT: 3 3 1.50 sarq %cl, %rdi -# CHECK-NEXT: 3 3 1.50 shlq %cl, %rdi -# CHECK-NEXT: 3 3 1.50 shrq %cl, %rdi -# CHECK-NEXT: 6 9 1.50 * * sarq %cl, (%rax) -# CHECK-NEXT: 6 9 1.50 * * shlq %cl, (%rax) -# CHECK-NEXT: 6 9 1.50 * * shrq %cl, (%rax) -# CHECK-NEXT: 2 2 0.67 sbbb $0, %al -# CHECK-NEXT: 2 2 0.67 sbbb $0, %dil -# CHECK-NEXT: 6 9 1.00 * * sbbb $0, (%rax) -# CHECK-NEXT: 2 2 0.67 sbbb $7, %al -# CHECK-NEXT: 2 2 0.67 sbbb $7, %dil -# CHECK-NEXT: 6 9 1.00 * * sbbb $7, (%rax) -# CHECK-NEXT: 2 2 0.67 sbbb %sil, %dil -# CHECK-NEXT: 6 9 1.00 * * sbbb %sil, (%rax) -# CHECK-NEXT: 3 7 0.67 * sbbb (%rax), %dil -# CHECK-NEXT: 2 2 0.67 sbbw $0, %ax -# CHECK-NEXT: 2 2 0.67 sbbw $0, %di -# CHECK-NEXT: 6 9 1.00 * * sbbw $0, (%rax) -# CHECK-NEXT: 2 2 0.67 sbbw $511, %ax -# CHECK-NEXT: 2 2 0.67 sbbw $511, %di -# CHECK-NEXT: 6 9 1.00 * * sbbw $511, (%rax) -# CHECK-NEXT: 2 2 0.67 sbbw $7, %di -# CHECK-NEXT: 6 9 1.00 * * sbbw $7, (%rax) -# CHECK-NEXT: 2 2 0.67 sbbw %si, %di -# CHECK-NEXT: 6 9 1.00 * * sbbw %si, (%rax) -# CHECK-NEXT: 3 7 0.67 * sbbw (%rax), %di -# CHECK-NEXT: 2 2 0.67 sbbl $0, %eax -# CHECK-NEXT: 2 2 0.67 sbbl $0, %edi -# CHECK-NEXT: 6 9 1.00 * * sbbl $0, (%rax) -# CHECK-NEXT: 2 2 0.67 sbbl $665536, %eax -# CHECK-NEXT: 2 2 0.67 sbbl $665536, %edi -# CHECK-NEXT: 6 9 1.00 * * sbbl $665536, (%rax) -# CHECK-NEXT: 2 2 0.67 sbbl $7, %edi -# CHECK-NEXT: 6 9 1.00 * * sbbl $7, (%rax) -# CHECK-NEXT: 2 2 0.67 sbbl %esi, %edi -# CHECK-NEXT: 6 9 1.00 * * sbbl %esi, (%rax) -# CHECK-NEXT: 3 7 0.67 * sbbl (%rax), %edi -# CHECK-NEXT: 2 2 0.67 sbbq $0, %rax -# CHECK-NEXT: 2 2 0.67 sbbq $0, %rdi -# CHECK-NEXT: 6 9 1.00 * * sbbq $0, (%rax) -# CHECK-NEXT: 2 2 0.67 sbbq $665536, %rax -# CHECK-NEXT: 2 2 0.67 sbbq $665536, %rdi -# CHECK-NEXT: 6 9 1.00 * * sbbq $665536, (%rax) -# CHECK-NEXT: 2 2 0.67 sbbq $7, %rdi -# CHECK-NEXT: 6 9 1.00 * * sbbq $7, (%rax) -# CHECK-NEXT: 2 2 0.67 sbbq %rsi, %rdi -# CHECK-NEXT: 6 9 1.00 * * sbbq %rsi, (%rax) -# CHECK-NEXT: 3 7 0.67 * sbbq (%rax), %rdi -# CHECK-NEXT: 2 2 0.67 U scasb %es:(%rdi), %al -# CHECK-NEXT: 2 2 0.67 U scasw %es:(%rdi), %ax -# CHECK-NEXT: 2 2 0.67 U scasl %es:(%rdi), %eax -# CHECK-NEXT: 2 2 0.67 U scasq %es:(%rdi), %rax -# CHECK-NEXT: 1 1 0.50 seto %al -# CHECK-NEXT: 3 2 1.00 * seto (%rax) -# CHECK-NEXT: 1 1 0.50 setno %al -# CHECK-NEXT: 3 2 1.00 * setno (%rax) -# CHECK-NEXT: 1 1 0.50 setb %al -# CHECK-NEXT: 3 2 1.00 * setb (%rax) -# CHECK-NEXT: 1 1 0.50 setae %al -# CHECK-NEXT: 3 2 1.00 * setae (%rax) -# CHECK-NEXT: 1 1 0.50 sete %al -# CHECK-NEXT: 3 2 1.00 * sete (%rax) -# CHECK-NEXT: 1 1 0.50 setne %al -# CHECK-NEXT: 3 2 1.00 * setne (%rax) -# CHECK-NEXT: 2 2 1.00 seta %al -# CHECK-NEXT: 4 3 1.00 * seta (%rax) -# CHECK-NEXT: 2 2 1.00 setbe %al -# CHECK-NEXT: 4 3 1.00 * setbe (%rax) -# CHECK-NEXT: 1 1 0.50 sets %al -# CHECK-NEXT: 3 2 1.00 * sets (%rax) -# CHECK-NEXT: 1 1 0.50 setns %al -# CHECK-NEXT: 3 2 1.00 * setns (%rax) -# CHECK-NEXT: 1 1 0.50 setp %al -# CHECK-NEXT: 3 2 1.00 * setp (%rax) -# CHECK-NEXT: 1 1 0.50 setnp %al -# CHECK-NEXT: 3 2 1.00 * setnp (%rax) -# CHECK-NEXT: 1 1 0.50 setl %al -# CHECK-NEXT: 3 2 1.00 * setl (%rax) -# CHECK-NEXT: 1 1 0.50 setge %al -# CHECK-NEXT: 3 2 1.00 * setge (%rax) -# CHECK-NEXT: 1 1 0.50 setg %al -# CHECK-NEXT: 3 2 1.00 * setg (%rax) -# CHECK-NEXT: 1 1 0.50 setle %al -# CHECK-NEXT: 3 2 1.00 * setle (%rax) -# CHECK-NEXT: 4 4 1.50 shldw %cl, %si, %di -# CHECK-NEXT: 4 4 1.50 shrdw %cl, %si, %di -# CHECK-NEXT: 7 10 1.50 * * shldw %cl, %si, (%rax) -# CHECK-NEXT: 7 10 1.50 * * shrdw %cl, %si, (%rax) -# CHECK-NEXT: 2 2 0.67 shldw $7, %si, %di -# CHECK-NEXT: 2 2 0.67 shrdw $7, %si, %di -# CHECK-NEXT: 5 8 1.00 * * shldw $7, %si, (%rax) -# CHECK-NEXT: 5 8 1.00 * * shrdw $7, %si, (%rax) -# CHECK-NEXT: 4 4 1.50 shldl %cl, %esi, %edi -# CHECK-NEXT: 4 4 1.50 shrdl %cl, %esi, %edi -# CHECK-NEXT: 7 10 1.50 * * shldl %cl, %esi, (%rax) -# CHECK-NEXT: 7 10 1.50 * * shrdl %cl, %esi, (%rax) -# CHECK-NEXT: 2 2 0.67 shldl $7, %esi, %edi -# CHECK-NEXT: 2 2 0.67 shrdl $7, %esi, %edi -# CHECK-NEXT: 5 8 1.00 * * shldl $7, %esi, (%rax) -# CHECK-NEXT: 5 8 1.00 * * shrdl $7, %esi, (%rax) -# CHECK-NEXT: 4 4 1.50 shldq %cl, %rsi, %rdi -# CHECK-NEXT: 4 4 1.50 shrdq %cl, %rsi, %rdi -# CHECK-NEXT: 7 10 1.50 * * shldq %cl, %rsi, (%rax) -# CHECK-NEXT: 7 10 1.50 * * shrdq %cl, %rsi, (%rax) -# CHECK-NEXT: 2 2 0.67 shldq $7, %rsi, %rdi -# CHECK-NEXT: 2 2 0.67 shrdq $7, %rsi, %rdi -# CHECK-NEXT: 5 8 1.00 * * shldq $7, %rsi, (%rax) -# CHECK-NEXT: 5 8 1.00 * * shrdq $7, %rsi, (%rax) -# CHECK-NEXT: 1 1 0.33 U stc -# CHECK-NEXT: 1 1 0.33 U std -# CHECK-NEXT: 3 5 1.00 U stosb %al, %es:(%rdi) -# CHECK-NEXT: 3 5 1.00 U stosw %ax, %es:(%rdi) -# CHECK-NEXT: 3 5 1.00 U stosl %eax, %es:(%rdi) -# CHECK-NEXT: 3 5 1.00 U stosq %rax, %es:(%rdi) -# CHECK-NEXT: 1 1 0.33 subb $7, %al -# CHECK-NEXT: 1 1 0.33 subb $7, %dil -# CHECK-NEXT: 3 7 1.00 * * subb $7, (%rax) -# CHECK-NEXT: 1 1 0.33 subb %sil, %dil -# CHECK-NEXT: 3 7 1.00 * * subb %sil, (%rax) -# CHECK-NEXT: 2 6 0.50 * subb (%rax), %dil -# CHECK-NEXT: 1 1 0.33 subw $511, %ax -# CHECK-NEXT: 1 1 0.33 subw $511, %di -# CHECK-NEXT: 3 7 1.00 * * subw $511, (%rax) -# CHECK-NEXT: 1 1 0.33 subw $7, %di -# CHECK-NEXT: 3 7 1.00 * * subw $7, (%rax) -# CHECK-NEXT: 1 1 0.33 subw %si, %di -# CHECK-NEXT: 3 7 1.00 * * subw %si, (%rax) -# CHECK-NEXT: 2 6 0.50 * subw (%rax), %di -# CHECK-NEXT: 1 1 0.33 subl $665536, %eax -# CHECK-NEXT: 1 1 0.33 subl $665536, %edi -# CHECK-NEXT: 3 7 1.00 * * subl $665536, (%rax) -# CHECK-NEXT: 1 1 0.33 subl $7, %edi -# CHECK-NEXT: 3 7 1.00 * * subl $7, (%rax) -# CHECK-NEXT: 1 1 0.33 subl %esi, %edi -# CHECK-NEXT: 3 7 1.00 * * subl %esi, (%rax) -# CHECK-NEXT: 2 6 0.50 * subl (%rax), %edi -# CHECK-NEXT: 1 1 0.33 subq $665536, %rax -# CHECK-NEXT: 1 1 0.33 subq $665536, %rdi -# CHECK-NEXT: 3 7 1.00 * * subq $665536, (%rax) -# CHECK-NEXT: 1 1 0.33 subq $7, %rdi -# CHECK-NEXT: 3 7 1.00 * * subq $7, (%rax) -# CHECK-NEXT: 1 1 0.33 subq %rsi, %rdi -# CHECK-NEXT: 3 7 1.00 * * subq %rsi, (%rax) -# CHECK-NEXT: 2 6 0.50 * subq (%rax), %rdi -# CHECK-NEXT: 1 1 0.33 testb $7, %al -# CHECK-NEXT: 1 1 0.33 testb $7, %dil -# CHECK-NEXT: 2 6 0.50 * testb $7, (%rax) -# CHECK-NEXT: 1 1 0.33 testb %sil, %dil -# CHECK-NEXT: 2 6 0.50 * testb %sil, (%rax) -# CHECK-NEXT: 1 1 0.33 testw $511, %ax -# CHECK-NEXT: 1 1 0.33 testw $511, %di -# CHECK-NEXT: 2 6 0.50 * testw $511, (%rax) -# CHECK-NEXT: 1 1 0.33 testw $7, %di -# CHECK-NEXT: 2 6 0.50 * testw $7, (%rax) -# CHECK-NEXT: 1 1 0.33 testw %si, %di -# CHECK-NEXT: 2 6 0.50 * testw %si, (%rax) -# CHECK-NEXT: 1 1 0.33 testl $665536, %eax -# CHECK-NEXT: 1 1 0.33 testl $665536, %edi -# CHECK-NEXT: 2 6 0.50 * testl $665536, (%rax) -# CHECK-NEXT: 1 1 0.33 testl $7, %edi -# CHECK-NEXT: 2 6 0.50 * testl $7, (%rax) -# CHECK-NEXT: 1 1 0.33 testl %esi, %edi -# CHECK-NEXT: 2 6 0.50 * testl %esi, (%rax) -# CHECK-NEXT: 1 1 0.33 testq $665536, %rax -# CHECK-NEXT: 1 1 0.33 testq $665536, %rdi -# CHECK-NEXT: 2 6 0.50 * testq $665536, (%rax) -# CHECK-NEXT: 1 1 0.33 testq $7, %rdi -# CHECK-NEXT: 2 6 0.50 * testq $7, (%rax) -# CHECK-NEXT: 1 1 0.33 testq %rsi, %rdi -# CHECK-NEXT: 2 6 0.50 * testq %rsi, (%rax) -# CHECK-NEXT: 1 100 0.33 * U ud2 -# CHECK-NEXT: 1 100 0.33 U wrmsr -# CHECK-NEXT: 3 2 1.00 xaddb %bl, %cl -# CHECK-NEXT: 5 8 1.00 * * xaddb %bl, (%rcx) -# CHECK-NEXT: 3 2 1.00 xaddw %bx, %cx -# CHECK-NEXT: 5 8 1.00 * * xaddw %ax, (%rbx) -# CHECK-NEXT: 3 2 1.00 xaddl %ebx, %ecx -# CHECK-NEXT: 5 8 1.00 * * xaddl %eax, (%rbx) -# CHECK-NEXT: 3 2 1.00 xaddq %rbx, %rcx -# CHECK-NEXT: 5 8 1.00 * * xaddq %rax, (%rbx) -# CHECK-NEXT: 3 2 1.00 xchgb %bl, %cl -# CHECK-NEXT: 3 6 1.00 * * xchgb %bl, (%rbx) -# CHECK-NEXT: 3 2 1.00 xchgw %bx, %ax -# CHECK-NEXT: 3 2 1.00 xchgw %bx, %cx -# CHECK-NEXT: 3 6 1.00 * * xchgw %ax, (%rbx) -# CHECK-NEXT: 3 2 1.00 xchgl %ebx, %eax -# CHECK-NEXT: 3 2 1.00 xchgl %ebx, %ecx -# CHECK-NEXT: 3 6 1.00 * * xchgl %eax, (%rbx) -# CHECK-NEXT: 3 2 1.00 xchgq %rbx, %rax -# CHECK-NEXT: 3 2 1.00 xchgq %rbx, %rcx -# CHECK-NEXT: 3 6 1.00 * * xchgq %rax, (%rbx) -# CHECK-NEXT: 1 5 0.50 * xlatb -# CHECK-NEXT: 1 1 0.33 xorb $7, %al -# CHECK-NEXT: 1 1 0.33 xorb $7, %dil -# CHECK-NEXT: 3 7 1.00 * * xorb $7, (%rax) -# CHECK-NEXT: 1 1 0.33 xorb %sil, %dil -# CHECK-NEXT: 3 7 1.00 * * xorb %sil, (%rax) -# CHECK-NEXT: 2 6 0.50 * xorb (%rax), %dil -# CHECK-NEXT: 1 1 0.33 xorw $511, %ax -# CHECK-NEXT: 1 1 0.33 xorw $511, %di -# CHECK-NEXT: 3 7 1.00 * * xorw $511, (%rax) -# CHECK-NEXT: 1 1 0.33 xorw $7, %di -# CHECK-NEXT: 3 7 1.00 * * xorw $7, (%rax) -# CHECK-NEXT: 1 1 0.33 xorw %si, %di -# CHECK-NEXT: 3 7 1.00 * * xorw %si, (%rax) -# CHECK-NEXT: 2 6 0.50 * xorw (%rax), %di -# CHECK-NEXT: 1 1 0.33 xorl $665536, %eax -# CHECK-NEXT: 1 1 0.33 xorl $665536, %edi -# CHECK-NEXT: 3 7 1.00 * * xorl $665536, (%rax) -# CHECK-NEXT: 1 1 0.33 xorl $7, %edi -# CHECK-NEXT: 3 7 1.00 * * xorl $7, (%rax) -# CHECK-NEXT: 1 1 0.33 xorl %esi, %edi -# CHECK-NEXT: 3 7 1.00 * * xorl %esi, (%rax) -# CHECK-NEXT: 2 6 0.50 * xorl (%rax), %edi -# CHECK-NEXT: 1 1 0.33 xorq $665536, %rax -# CHECK-NEXT: 1 1 0.33 xorq $665536, %rdi -# CHECK-NEXT: 3 7 1.00 * * xorq $665536, (%rax) -# CHECK-NEXT: 1 1 0.33 xorq $7, %rdi -# CHECK-NEXT: 3 7 1.00 * * xorq $7, (%rax) -# CHECK-NEXT: 1 1 0.33 xorq %rsi, %rdi -# CHECK-NEXT: 3 7 1.00 * * xorq %rsi, (%rax) -# CHECK-NEXT: 2 6 0.50 * xorq (%rax), %rdi +# CHECK-NEXT: 1 2 1.00 adcb $0, %al +# CHECK-NEXT: 1 2 1.00 adcb $0, %dil +# CHECK-NEXT: 1 6 1.00 * * adcb $0, (%rax) +# CHECK-NEXT: 1 2 1.00 adcb $7, %al +# CHECK-NEXT: 1 2 1.00 adcb $7, %dil +# CHECK-NEXT: 1 6 1.00 * * adcb $7, (%rax) +# CHECK-NEXT: 1 2 1.00 adcb %sil, %dil +# CHECK-NEXT: 1 6 1.00 * * adcb %sil, (%rax) +# CHECK-NEXT: 1 5 1.00 * adcb (%rax), %dil +# CHECK-NEXT: 1 2 1.00 adcw $0, %ax +# CHECK-NEXT: 1 2 1.00 adcw $0, %di +# CHECK-NEXT: 1 6 1.00 * * adcw $0, (%rax) +# CHECK-NEXT: 1 2 1.00 adcw $511, %ax +# CHECK-NEXT: 1 2 1.00 adcw $511, %di +# CHECK-NEXT: 1 6 1.00 * * adcw $511, (%rax) +# CHECK-NEXT: 1 2 1.00 adcw $7, %di +# CHECK-NEXT: 1 6 1.00 * * adcw $7, (%rax) +# CHECK-NEXT: 1 2 1.00 adcw %si, %di +# CHECK-NEXT: 1 6 1.00 * * adcw %si, (%rax) +# CHECK-NEXT: 1 5 1.00 * adcw (%rax), %di +# CHECK-NEXT: 1 2 1.00 adcl $0, %eax +# CHECK-NEXT: 1 2 1.00 adcl $0, %edi +# CHECK-NEXT: 1 6 1.00 * * adcl $0, (%rax) +# CHECK-NEXT: 1 2 1.00 adcl $665536, %eax +# CHECK-NEXT: 1 2 1.00 adcl $665536, %edi +# CHECK-NEXT: 1 6 1.00 * * adcl $665536, (%rax) +# CHECK-NEXT: 1 2 1.00 adcl $7, %edi +# CHECK-NEXT: 1 6 1.00 * * adcl $7, (%rax) +# CHECK-NEXT: 1 2 1.00 adcl %esi, %edi +# CHECK-NEXT: 1 6 1.00 * * adcl %esi, (%rax) +# CHECK-NEXT: 1 5 1.00 * adcl (%rax), %edi +# CHECK-NEXT: 1 2 1.00 adcq $0, %rax +# CHECK-NEXT: 1 2 1.00 adcq $0, %rdi +# CHECK-NEXT: 1 6 1.00 * * adcq $0, (%rax) +# CHECK-NEXT: 1 2 1.00 adcq $665536, %rax +# CHECK-NEXT: 1 2 1.00 adcq $665536, %rdi +# CHECK-NEXT: 1 6 1.00 * * adcq $665536, (%rax) +# CHECK-NEXT: 1 2 1.00 adcq $7, %rdi +# CHECK-NEXT: 1 6 1.00 * * adcq $7, (%rax) +# CHECK-NEXT: 1 2 1.00 adcq %rsi, %rdi +# CHECK-NEXT: 1 6 1.00 * * adcq %rsi, (%rax) +# CHECK-NEXT: 1 5 1.00 * adcq (%rax), %rdi +# CHECK-NEXT: 1 2 1.00 addb $7, %al +# CHECK-NEXT: 1 2 1.00 addb $7, %dil +# CHECK-NEXT: 1 6 1.00 * * addb $7, (%rax) +# CHECK-NEXT: 1 2 1.00 addb %sil, %dil +# CHECK-NEXT: 1 6 1.00 * * addb %sil, (%rax) +# CHECK-NEXT: 1 5 1.00 * addb (%rax), %dil +# CHECK-NEXT: 1 2 1.00 addw $511, %ax +# CHECK-NEXT: 1 2 1.00 addw $511, %di +# CHECK-NEXT: 1 6 1.00 * * addw $511, (%rax) +# CHECK-NEXT: 1 2 1.00 addw $7, %di +# CHECK-NEXT: 1 6 1.00 * * addw $7, (%rax) +# CHECK-NEXT: 1 2 1.00 addw %si, %di +# CHECK-NEXT: 1 6 1.00 * * addw %si, (%rax) +# CHECK-NEXT: 1 5 1.00 * addw (%rax), %di +# CHECK-NEXT: 1 2 1.00 addl $665536, %eax +# CHECK-NEXT: 1 2 1.00 addl $665536, %edi +# CHECK-NEXT: 1 6 1.00 * * addl $665536, (%rax) +# CHECK-NEXT: 1 2 1.00 addl $7, %edi +# CHECK-NEXT: 1 6 1.00 * * addl $7, (%rax) +# CHECK-NEXT: 1 2 1.00 addl %esi, %edi +# CHECK-NEXT: 1 6 1.00 * * addl %esi, (%rax) +# CHECK-NEXT: 1 5 1.00 * addl (%rax), %edi +# CHECK-NEXT: 1 2 1.00 addq $665536, %rax +# CHECK-NEXT: 1 2 1.00 addq $665536, %rdi +# CHECK-NEXT: 1 6 1.00 * * addq $665536, (%rax) +# CHECK-NEXT: 1 2 1.00 addq $7, %rdi +# CHECK-NEXT: 1 6 1.00 * * addq $7, (%rax) +# CHECK-NEXT: 1 2 1.00 addq %rsi, %rdi +# CHECK-NEXT: 1 6 1.00 * * addq %rsi, (%rax) +# CHECK-NEXT: 1 5 1.00 * addq (%rax), %rdi +# CHECK-NEXT: 1 2 1.00 andb $7, %al +# CHECK-NEXT: 1 2 1.00 andb $7, %dil +# CHECK-NEXT: 1 6 1.00 * * andb $7, (%rax) +# CHECK-NEXT: 1 2 1.00 andb %sil, %dil +# CHECK-NEXT: 1 6 1.00 * * andb %sil, (%rax) +# CHECK-NEXT: 1 5 1.00 * andb (%rax), %dil +# CHECK-NEXT: 1 2 1.00 andw $511, %ax +# CHECK-NEXT: 1 2 1.00 andw $511, %di +# CHECK-NEXT: 1 6 1.00 * * andw $511, (%rax) +# CHECK-NEXT: 1 2 1.00 andw $7, %di +# CHECK-NEXT: 1 6 1.00 * * andw $7, (%rax) +# CHECK-NEXT: 1 2 1.00 andw %si, %di +# CHECK-NEXT: 1 6 1.00 * * andw %si, (%rax) +# CHECK-NEXT: 1 5 1.00 * andw (%rax), %di +# CHECK-NEXT: 1 2 1.00 andl $665536, %eax +# CHECK-NEXT: 1 2 1.00 andl $665536, %edi +# CHECK-NEXT: 1 6 1.00 * * andl $665536, (%rax) +# CHECK-NEXT: 1 2 1.00 andl $7, %edi +# CHECK-NEXT: 1 6 1.00 * * andl $7, (%rax) +# CHECK-NEXT: 1 2 1.00 andl %esi, %edi +# CHECK-NEXT: 1 6 1.00 * * andl %esi, (%rax) +# CHECK-NEXT: 1 5 1.00 * andl (%rax), %edi +# CHECK-NEXT: 1 2 1.00 andq $665536, %rax +# CHECK-NEXT: 1 2 1.00 andq $665536, %rdi +# CHECK-NEXT: 1 6 1.00 * * andq $665536, (%rax) +# CHECK-NEXT: 1 2 1.00 andq $7, %rdi +# CHECK-NEXT: 1 6 1.00 * * andq $7, (%rax) +# CHECK-NEXT: 1 2 1.00 andq %rsi, %rdi +# CHECK-NEXT: 1 6 1.00 * * andq %rsi, (%rax) +# CHECK-NEXT: 1 5 1.00 * andq (%rax), %rdi +# CHECK-NEXT: 6 4 3.00 bsfw %si, %di +# CHECK-NEXT: 7 4 3.00 bsrw %si, %di +# CHECK-NEXT: 7 7 3.00 * bsfw (%rax), %di +# CHECK-NEXT: 8 7 3.00 * bsrw (%rax), %di +# CHECK-NEXT: 6 4 3.00 bsfl %esi, %edi +# CHECK-NEXT: 7 4 3.00 bsrl %esi, %edi +# CHECK-NEXT: 7 7 3.00 * bsfl (%rax), %edi +# CHECK-NEXT: 8 7 3.00 * bsrl (%rax), %edi +# CHECK-NEXT: 6 4 3.00 bsfq %rsi, %rdi +# CHECK-NEXT: 7 4 3.00 bsrq %rsi, %rdi +# CHECK-NEXT: 7 7 3.00 * bsfq (%rax), %rdi +# CHECK-NEXT: 8 7 3.00 * bsrq (%rax), %rdi +# CHECK-NEXT: 1 2 1.33 bswapl %eax +# CHECK-NEXT: 1 2 1.33 bswapq %rax +# CHECK-NEXT: 1 1 1.67 btw %si, %di +# CHECK-NEXT: 2 3 2.00 btcw %si, %di +# CHECK-NEXT: 2 3 2.00 btrw %si, %di +# CHECK-NEXT: 2 3 2.00 btsw %si, %di +# CHECK-NEXT: 5 7 3.33 * btw %si, (%rax) +# CHECK-NEXT: 8 10 4.00 * * btcw %si, (%rax) +# CHECK-NEXT: 8 10 4.00 * * btrw %si, (%rax) +# CHECK-NEXT: 8 10 4.00 * * btsw %si, (%rax) +# CHECK-NEXT: 1 1 1.67 btw $7, %di +# CHECK-NEXT: 2 3 2.00 btcw $7, %di +# CHECK-NEXT: 2 3 2.00 btrw $7, %di +# CHECK-NEXT: 2 3 2.00 btsw $7, %di +# CHECK-NEXT: 1 7 4.00 * btw $7, (%rax) +# CHECK-NEXT: 4 10 5.00 * * btcw $7, (%rax) +# CHECK-NEXT: 4 10 5.00 * * btrw $7, (%rax) +# CHECK-NEXT: 4 10 5.00 * * btsw $7, (%rax) +# CHECK-NEXT: 1 1 1.67 btl %esi, %edi +# CHECK-NEXT: 2 3 2.00 btcl %esi, %edi +# CHECK-NEXT: 2 3 2.00 btrl %esi, %edi +# CHECK-NEXT: 2 3 2.00 btsl %esi, %edi +# CHECK-NEXT: 5 7 3.33 * btl %esi, (%rax) +# CHECK-NEXT: 8 10 4.00 * * btcl %esi, (%rax) +# CHECK-NEXT: 8 10 4.00 * * btrl %esi, (%rax) +# CHECK-NEXT: 8 10 4.00 * * btsl %esi, (%rax) +# CHECK-NEXT: 1 1 1.67 btl $7, %edi +# CHECK-NEXT: 2 3 2.00 btcl $7, %edi +# CHECK-NEXT: 2 3 2.00 btrl $7, %edi +# CHECK-NEXT: 2 3 2.00 btsl $7, %edi +# CHECK-NEXT: 1 7 4.00 * btl $7, (%rax) +# CHECK-NEXT: 4 10 5.00 * * btcl $7, (%rax) +# CHECK-NEXT: 4 10 5.00 * * btrl $7, (%rax) +# CHECK-NEXT: 4 10 5.00 * * btsl $7, (%rax) +# CHECK-NEXT: 1 1 1.67 btq %rsi, %rdi +# CHECK-NEXT: 2 3 2.00 btcq %rsi, %rdi +# CHECK-NEXT: 2 3 2.00 btrq %rsi, %rdi +# CHECK-NEXT: 2 3 2.00 btsq %rsi, %rdi +# CHECK-NEXT: 5 7 3.33 * btq %rsi, (%rax) +# CHECK-NEXT: 8 10 4.00 * * btcq %rsi, (%rax) +# CHECK-NEXT: 8 10 4.00 * * btrq %rsi, (%rax) +# CHECK-NEXT: 8 10 4.00 * * btsq %rsi, (%rax) +# CHECK-NEXT: 1 1 1.67 btq $7, %rdi +# CHECK-NEXT: 2 3 2.00 btcq $7, %rdi +# CHECK-NEXT: 2 3 2.00 btrq $7, %rdi +# CHECK-NEXT: 2 3 2.00 btsq $7, %rdi +# CHECK-NEXT: 1 7 4.00 * btq $7, (%rax) +# CHECK-NEXT: 4 10 5.00 * * btcq $7, (%rax) +# CHECK-NEXT: 4 10 5.00 * * btrq $7, (%rax) +# CHECK-NEXT: 4 10 5.00 * * btsq $7, (%rax) +# CHECK-NEXT: 1 2 1.00 cbtw +# CHECK-NEXT: 1 2 1.00 cwtl +# CHECK-NEXT: 1 2 1.00 cltq +# CHECK-NEXT: 1 2 1.00 cwtd +# CHECK-NEXT: 1 2 1.00 cltd +# CHECK-NEXT: 1 2 1.00 cqto +# CHECK-NEXT: 1 2 1.00 U clc +# CHECK-NEXT: 1 2 1.00 U cld +# CHECK-NEXT: 1 2 1.00 U cmc +# CHECK-NEXT: 1 2 1.00 cmpb $7, %al +# CHECK-NEXT: 1 2 1.00 cmpb $7, %dil +# CHECK-NEXT: 1 5 1.00 * cmpb $7, (%rax) +# CHECK-NEXT: 1 2 1.00 cmpb %sil, %dil +# CHECK-NEXT: 1 5 1.00 * cmpb %sil, (%rax) +# CHECK-NEXT: 1 5 1.00 * cmpb (%rax), %dil +# CHECK-NEXT: 1 2 1.00 cmpw $511, %ax +# CHECK-NEXT: 1 2 1.00 cmpw $511, %di +# CHECK-NEXT: 1 5 1.00 * cmpw $511, (%rax) +# CHECK-NEXT: 1 2 1.00 cmpw $7, %di +# CHECK-NEXT: 1 5 1.00 * cmpw $7, (%rax) +# CHECK-NEXT: 1 2 1.00 cmpw %si, %di +# CHECK-NEXT: 1 5 1.00 * cmpw %si, (%rax) +# CHECK-NEXT: 1 5 1.00 * cmpw (%rax), %di +# CHECK-NEXT: 1 2 1.00 cmpl $665536, %eax +# CHECK-NEXT: 1 2 1.00 cmpl $665536, %edi +# CHECK-NEXT: 1 5 1.00 * cmpl $665536, (%rax) +# CHECK-NEXT: 1 2 1.00 cmpl $7, %edi +# CHECK-NEXT: 1 5 1.00 * cmpl $7, (%rax) +# CHECK-NEXT: 1 2 1.00 cmpl %esi, %edi +# CHECK-NEXT: 1 5 1.00 * cmpl %esi, (%rax) +# CHECK-NEXT: 1 5 1.00 * cmpl (%rax), %edi +# CHECK-NEXT: 1 2 1.00 cmpq $665536, %rax +# CHECK-NEXT: 1 2 1.00 cmpq $665536, %rdi +# CHECK-NEXT: 1 5 1.00 * cmpq $665536, (%rax) +# CHECK-NEXT: 1 2 1.00 cmpq $7, %rdi +# CHECK-NEXT: 1 5 1.00 * cmpq $7, (%rax) +# CHECK-NEXT: 1 2 1.00 cmpq %rsi, %rdi +# CHECK-NEXT: 1 5 1.00 * cmpq %rsi, (%rax) +# CHECK-NEXT: 1 5 1.00 * cmpq (%rax), %rdi +# CHECK-NEXT: 13 100 9.00 U cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: 13 100 9.00 U cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: 13 100 9.00 U cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: 13 100 9.00 U cmpsq %es:(%rdi), (%rsi) +# CHECK-NEXT: 5 3 2.33 cmpxchgb %cl, %bl +# CHECK-NEXT: 6 5 24.33 * * cmpxchgb %cl, (%rbx) +# CHECK-NEXT: 5 3 2.33 cmpxchgw %cx, %bx +# CHECK-NEXT: 6 5 24.33 * * cmpxchgw %cx, (%rbx) +# CHECK-NEXT: 5 3 2.33 cmpxchgl %ecx, %ebx +# CHECK-NEXT: 6 5 24.33 * * cmpxchgl %ecx, (%rbx) +# CHECK-NEXT: 5 3 2.33 cmpxchgq %rcx, %rbx +# CHECK-NEXT: 6 5 24.33 * * cmpxchgq %rcx, (%rbx) +# CHECK-NEXT: 1 100 42.00 U cpuid +# CHECK-NEXT: 1 2 1.00 decb %dil +# CHECK-NEXT: 1 6 1.00 * * decb (%rax) +# CHECK-NEXT: 1 2 1.00 decw %di +# CHECK-NEXT: 1 6 1.00 * * decw (%rax) +# CHECK-NEXT: 1 2 1.00 decl %edi +# CHECK-NEXT: 1 6 1.00 * * decl (%rax) +# CHECK-NEXT: 1 2 1.00 decq %rdi +# CHECK-NEXT: 1 6 1.00 * * decq (%rax) +# CHECK-NEXT: 36 17 17.00 U divb %dil +# CHECK-NEXT: 36 20 17.00 * U divb (%rax) +# CHECK-NEXT: 40 18 18.00 U divw %si +# CHECK-NEXT: 40 21 18.00 * U divw (%rax) +# CHECK-NEXT: 40 18 18.00 U divl %edx +# CHECK-NEXT: 40 21 18.00 * U divl (%rax) +# CHECK-NEXT: 40 18 18.00 U divq %rcx +# CHECK-NEXT: 40 21 18.00 * U divq (%rax) +# CHECK-NEXT: 13 100 9.00 U enter $7, $4095 +# CHECK-NEXT: 44 18 18.00 U idivb %dil +# CHECK-NEXT: 44 21 18.00 * U idivb (%rax) +# CHECK-NEXT: 50 25 25.00 U idivw %si +# CHECK-NEXT: 50 28 25.00 * U idivw (%rax) +# CHECK-NEXT: 50 25 25.00 U idivl %edx +# CHECK-NEXT: 50 28 25.00 * U idivl (%rax) +# CHECK-NEXT: 50 25 25.00 U idivq %rcx +# CHECK-NEXT: 50 28 25.00 * U idivq (%rax) +# CHECK-NEXT: 1 3 3.00 imulb %dil +# CHECK-NEXT: 1 6 3.00 * imulb (%rax) +# CHECK-NEXT: 3 3 3.00 imulw %di +# CHECK-NEXT: 3 6 3.00 * imulw (%rax) +# CHECK-NEXT: 1 3 3.00 imulw %si, %di +# CHECK-NEXT: 1 6 3.00 * imulw (%rax), %di +# CHECK-NEXT: 2 4 3.00 imulw $511, %si, %di +# CHECK-NEXT: 3 7 3.00 * imulw $511, (%rax), %di +# CHECK-NEXT: 2 4 3.00 imulw $7, %si, %di +# CHECK-NEXT: 3 7 3.00 * imulw $7, (%rax), %di +# CHECK-NEXT: 2 3 3.00 imull %edi +# CHECK-NEXT: 2 6 3.00 * imull (%rax) +# CHECK-NEXT: 1 3 2.00 imull %esi, %edi +# CHECK-NEXT: 1 6 2.00 * imull (%rax), %edi +# CHECK-NEXT: 1 3 3.00 imull $665536, %esi, %edi +# CHECK-NEXT: 3 6 3.00 * imull $665536, (%rax), %edi +# CHECK-NEXT: 1 3 3.00 imull $7, %esi, %edi +# CHECK-NEXT: 3 6 3.00 * imull $7, (%rax), %edi +# CHECK-NEXT: 2 4 4.00 imulq %rdi +# CHECK-NEXT: 2 7 4.00 * imulq (%rax) +# CHECK-NEXT: 1 4 2.00 imulq %rsi, %rdi +# CHECK-NEXT: 1 7 2.00 * imulq (%rax), %rdi +# CHECK-NEXT: 1 4 4.00 imulq $665536, %rsi, %rdi +# CHECK-NEXT: 3 7 4.00 * imulq $665536, (%rax), %rdi +# CHECK-NEXT: 1 4 4.00 imulq $7, %rsi, %rdi +# CHECK-NEXT: 3 7 4.00 * imulq $7, (%rax), %rdi +# CHECK-NEXT: 1 100 42.00 U inb $7, %al +# CHECK-NEXT: 1 100 42.00 U inb %dx, %al +# CHECK-NEXT: 1 100 42.00 U inw $7, %ax +# CHECK-NEXT: 1 100 42.00 U inw %dx, %ax +# CHECK-NEXT: 1 100 42.00 U inl $7, %eax +# CHECK-NEXT: 1 100 42.00 U inl %dx, %eax +# CHECK-NEXT: 1 2 1.00 incb %dil +# CHECK-NEXT: 1 6 1.00 * * incb (%rax) +# CHECK-NEXT: 1 2 1.00 incw %di +# CHECK-NEXT: 1 6 1.00 * * incw (%rax) +# CHECK-NEXT: 1 2 1.00 incl %edi +# CHECK-NEXT: 1 6 1.00 * * incl (%rax) +# CHECK-NEXT: 1 2 1.00 incq %rdi +# CHECK-NEXT: 1 6 1.00 * * incq (%rax) +# CHECK-NEXT: 1 100 42.00 U insb %dx, %es:(%rdi) +# CHECK-NEXT: 1 100 42.00 U insw %dx, %es:(%rdi) +# CHECK-NEXT: 1 100 42.00 U insl %dx, %es:(%rdi) +# CHECK-NEXT: 1 100 42.00 * * U int $7 +# CHECK-NEXT: 1 100 42.00 U invlpg (%rax) +# CHECK-NEXT: 1 100 42.00 U invlpga %rax, %ecx +# CHECK-NEXT: 4 1 2.00 lahf +# CHECK-NEXT: 1 2 1.00 * leave +# CHECK-NEXT: 13 100 9.00 U lodsb (%rsi), %al +# CHECK-NEXT: 13 100 9.00 U lodsw (%rsi), %ax +# CHECK-NEXT: 13 100 9.00 U lodsl (%rsi), %eax +# CHECK-NEXT: 13 100 9.00 U lodsq (%rsi), %rax +# CHECK-NEXT: 13 100 9.00 U movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: 13 100 9.00 U movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: 13 100 9.00 U movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: 13 100 9.00 U movsq (%rsi), %es:(%rdi) +# CHECK-NEXT: 1 2 1.00 movsbw %al, %di +# CHECK-NEXT: 1 2 1.00 movzbw %al, %di +# CHECK-NEXT: 1 5 1.00 * movsbw (%rax), %di +# CHECK-NEXT: 1 5 1.00 * movzbw (%rax), %di +# CHECK-NEXT: 1 2 1.00 movsbl %al, %edi +# CHECK-NEXT: 1 2 1.00 movzbl %al, %edi +# CHECK-NEXT: 1 5 1.00 * movsbl (%rax), %edi +# CHECK-NEXT: 1 5 1.00 * movzbl (%rax), %edi +# CHECK-NEXT: 1 2 1.00 movsbq %al, %rdi +# CHECK-NEXT: 1 2 1.00 movzbq %al, %rdi +# CHECK-NEXT: 1 5 1.00 * movsbq (%rax), %rdi +# CHECK-NEXT: 1 5 1.00 * movzbq (%rax), %rdi +# CHECK-NEXT: 1 2 1.00 movswl %ax, %edi +# CHECK-NEXT: 1 2 1.00 movzwl %ax, %edi +# CHECK-NEXT: 1 5 1.00 * movswl (%rax), %edi +# CHECK-NEXT: 1 5 1.00 * movzwl (%rax), %edi +# CHECK-NEXT: 1 2 1.00 movswq %ax, %rdi +# CHECK-NEXT: 1 2 1.00 movzwq %ax, %rdi +# CHECK-NEXT: 1 5 1.00 * movswq (%rax), %rdi +# CHECK-NEXT: 1 5 1.00 * movzwq (%rax), %rdi +# CHECK-NEXT: 1 2 1.00 movslq %eax, %rdi +# CHECK-NEXT: 1 5 1.00 * movslq (%rax), %rdi +# CHECK-NEXT: 1 3 3.00 mulb %dil +# CHECK-NEXT: 1 6 3.00 * mulb (%rax) +# CHECK-NEXT: 3 3 3.00 mulw %si +# CHECK-NEXT: 3 6 3.00 * mulw (%rax) +# CHECK-NEXT: 2 3 3.00 mull %edx +# CHECK-NEXT: 2 6 3.00 * mull (%rax) +# CHECK-NEXT: 2 4 4.00 mulq %rcx +# CHECK-NEXT: 2 7 4.00 * mulq (%rax) +# CHECK-NEXT: 1 2 1.00 negb %dil +# CHECK-NEXT: 1 6 1.00 * * negb (%r8) +# CHECK-NEXT: 1 2 1.00 negw %si +# CHECK-NEXT: 1 6 1.00 * * negw (%r9) +# CHECK-NEXT: 1 2 1.00 negl %edx +# CHECK-NEXT: 1 6 1.00 * * negl (%rax) +# CHECK-NEXT: 1 2 1.00 negq %rcx +# CHECK-NEXT: 1 6 1.00 * * negq (%r10) +# CHECK-NEXT: 1 0 0.33 nop +# CHECK-NEXT: 1 0 0.33 nopw %di +# CHECK-NEXT: 1 0 0.33 nopw (%rcx) +# CHECK-NEXT: 1 0 0.33 nopl %esi +# CHECK-NEXT: 1 0 0.33 nopl (%r8) +# CHECK-NEXT: 1 0 0.33 nopq %rdx +# CHECK-NEXT: 1 0 0.33 nopq (%r9) +# CHECK-NEXT: 1 2 1.00 notb %dil +# CHECK-NEXT: 1 6 1.00 * * notb (%r8) +# CHECK-NEXT: 1 2 1.00 notw %si +# CHECK-NEXT: 1 6 1.00 * * notw (%r9) +# CHECK-NEXT: 1 2 1.00 notl %edx +# CHECK-NEXT: 1 6 1.00 * * notl (%rax) +# CHECK-NEXT: 1 2 1.00 notq %rcx +# CHECK-NEXT: 1 6 1.00 * * notq (%r10) +# CHECK-NEXT: 1 2 1.00 orb $7, %al +# CHECK-NEXT: 1 2 1.00 orb $7, %dil +# CHECK-NEXT: 1 6 1.00 * * orb $7, (%rax) +# CHECK-NEXT: 1 2 1.00 orb %sil, %dil +# CHECK-NEXT: 1 6 1.00 * * orb %sil, (%rax) +# CHECK-NEXT: 1 5 1.00 * orb (%rax), %dil +# CHECK-NEXT: 1 2 1.00 orw $511, %ax +# CHECK-NEXT: 1 2 1.00 orw $511, %di +# CHECK-NEXT: 1 6 1.00 * * orw $511, (%rax) +# CHECK-NEXT: 1 2 1.00 orw $7, %di +# CHECK-NEXT: 1 6 1.00 * * orw $7, (%rax) +# CHECK-NEXT: 1 2 1.00 orw %si, %di +# CHECK-NEXT: 1 6 1.00 * * orw %si, (%rax) +# CHECK-NEXT: 1 5 1.00 * orw (%rax), %di +# CHECK-NEXT: 1 2 1.00 orl $665536, %eax +# CHECK-NEXT: 1 2 1.00 orl $665536, %edi +# CHECK-NEXT: 1 6 1.00 * * orl $665536, (%rax) +# CHECK-NEXT: 1 2 1.00 orl $7, %edi +# CHECK-NEXT: 1 6 1.00 * * orl $7, (%rax) +# CHECK-NEXT: 1 2 1.00 orl %esi, %edi +# CHECK-NEXT: 1 6 1.00 * * orl %esi, (%rax) +# CHECK-NEXT: 1 5 1.00 * orl (%rax), %edi +# CHECK-NEXT: 1 2 1.00 orq $665536, %rax +# CHECK-NEXT: 1 2 1.00 orq $665536, %rdi +# CHECK-NEXT: 1 6 1.00 * * orq $665536, (%rax) +# CHECK-NEXT: 1 2 1.00 orq $7, %rdi +# CHECK-NEXT: 1 6 1.00 * * orq $7, (%rax) +# CHECK-NEXT: 1 2 1.00 orq %rsi, %rdi +# CHECK-NEXT: 1 6 1.00 * * orq %rsi, (%rax) +# CHECK-NEXT: 1 5 1.00 * orq (%rax), %rdi +# CHECK-NEXT: 1 100 42.00 U outb %al, $7 +# CHECK-NEXT: 1 100 42.00 U outb %al, %dx +# CHECK-NEXT: 1 100 42.00 U outw %ax, $7 +# CHECK-NEXT: 1 100 42.00 U outw %ax, %dx +# CHECK-NEXT: 1 100 42.00 U outl %eax, $7 +# CHECK-NEXT: 1 100 42.00 U outl %eax, %dx +# CHECK-NEXT: 1 100 42.00 U outsb (%rsi), %dx +# CHECK-NEXT: 1 100 42.00 U outsw (%rsi), %dx +# CHECK-NEXT: 1 100 42.00 U outsl (%rsi), %dx +# CHECK-NEXT: 1 0 0.33 * * U pause +# CHECK-NEXT: 1 2 2.00 rclb %dil +# CHECK-NEXT: 1 2 2.00 rcrb %dil +# CHECK-NEXT: 9 5 2.00 * rclb (%rax) +# CHECK-NEXT: 9 5 2.00 * rcrb (%rax) +# CHECK-NEXT: 1 2 2.00 rclb $7, %dil +# CHECK-NEXT: 1 2 2.00 rcrb $7, %dil +# CHECK-NEXT: 9 5 2.00 * rclb $7, (%rax) +# CHECK-NEXT: 9 5 2.00 * rcrb $7, (%rax) +# CHECK-NEXT: 9 1 1.33 rclb %cl, %dil +# CHECK-NEXT: 9 1 1.33 rcrb %cl, %dil +# CHECK-NEXT: 9 4 1.33 * rclb %cl, (%rax) +# CHECK-NEXT: 9 4 1.33 * rcrb %cl, (%rax) +# CHECK-NEXT: 1 2 2.00 rclw %di +# CHECK-NEXT: 1 2 2.00 rcrw %di +# CHECK-NEXT: 9 5 2.00 * rclw (%rax) +# CHECK-NEXT: 9 5 2.00 * rcrw (%rax) +# CHECK-NEXT: 1 2 2.00 rclw $7, %di +# CHECK-NEXT: 1 2 2.00 rcrw $7, %di +# CHECK-NEXT: 9 5 2.00 * rclw $7, (%rax) +# CHECK-NEXT: 9 5 2.00 * rcrw $7, (%rax) +# CHECK-NEXT: 9 1 1.33 rclw %cl, %di +# CHECK-NEXT: 9 1 1.33 rcrw %cl, %di +# CHECK-NEXT: 9 4 1.33 * rclw %cl, (%rax) +# CHECK-NEXT: 9 4 1.33 * rcrw %cl, (%rax) +# CHECK-NEXT: 1 2 2.00 rcll %edi +# CHECK-NEXT: 1 2 2.00 rcrl %edi +# CHECK-NEXT: 9 5 2.00 * rcll (%rax) +# CHECK-NEXT: 9 5 2.00 * rcrl (%rax) +# CHECK-NEXT: 1 2 2.00 rcll $7, %edi +# CHECK-NEXT: 1 2 2.00 rcrl $7, %edi +# CHECK-NEXT: 9 5 2.00 * rcll $7, (%rax) +# CHECK-NEXT: 9 5 2.00 * rcrl $7, (%rax) +# CHECK-NEXT: 9 1 1.33 rcll %cl, %edi +# CHECK-NEXT: 9 1 1.33 rcrl %cl, %edi +# CHECK-NEXT: 9 4 1.33 * rcll %cl, (%rax) +# CHECK-NEXT: 9 4 1.33 * rcrl %cl, (%rax) +# CHECK-NEXT: 1 2 2.00 rclq %rdi +# CHECK-NEXT: 1 2 2.00 rcrq %rdi +# CHECK-NEXT: 9 5 2.00 * rclq (%rax) +# CHECK-NEXT: 9 5 2.00 * rcrq (%rax) +# CHECK-NEXT: 1 2 2.00 rclq $7, %rdi +# CHECK-NEXT: 1 2 2.00 rcrq $7, %rdi +# CHECK-NEXT: 9 5 2.00 * rclq $7, (%rax) +# CHECK-NEXT: 9 5 2.00 * rcrq $7, (%rax) +# CHECK-NEXT: 9 1 1.33 rclq %cl, %rdi +# CHECK-NEXT: 9 1 1.33 rcrq %cl, %rdi +# CHECK-NEXT: 9 4 1.33 * rclq %cl, (%rax) +# CHECK-NEXT: 9 4 1.33 * rcrq %cl, (%rax) +# CHECK-NEXT: 1 100 42.00 U rdmsr +# CHECK-NEXT: 1 100 42.00 U rdpmc +# CHECK-NEXT: 1 100 42.00 U rdtsc +# CHECK-NEXT: 1 100 42.00 U rdtscp +# CHECK-NEXT: 1 2 2.00 rolb %dil +# CHECK-NEXT: 1 2 2.00 rorb %dil +# CHECK-NEXT: 9 5 2.00 * * rolb (%rax) +# CHECK-NEXT: 9 5 2.00 * * rorb (%rax) +# CHECK-NEXT: 1 2 2.00 rolb $7, %dil +# CHECK-NEXT: 1 2 2.00 rorb $7, %dil +# CHECK-NEXT: 9 5 2.00 * * rolb $7, (%rax) +# CHECK-NEXT: 9 5 2.00 * * rorb $7, (%rax) +# CHECK-NEXT: 9 1 1.33 rolb %cl, %dil +# CHECK-NEXT: 9 1 1.33 rorb %cl, %dil +# CHECK-NEXT: 9 4 1.33 * * rolb %cl, (%rax) +# CHECK-NEXT: 9 4 1.33 * * rorb %cl, (%rax) +# CHECK-NEXT: 1 2 2.00 rolw %di +# CHECK-NEXT: 1 2 2.00 rorw %di +# CHECK-NEXT: 9 5 2.00 * * rolw (%rax) +# CHECK-NEXT: 9 5 2.00 * * rorw (%rax) +# CHECK-NEXT: 1 2 2.00 rolw $7, %di +# CHECK-NEXT: 1 2 2.00 rorw $7, %di +# CHECK-NEXT: 9 5 2.00 * * rolw $7, (%rax) +# CHECK-NEXT: 9 5 2.00 * * rorw $7, (%rax) +# CHECK-NEXT: 9 1 1.33 rolw %cl, %di +# CHECK-NEXT: 9 1 1.33 rorw %cl, %di +# CHECK-NEXT: 9 4 1.33 * * rolw %cl, (%rax) +# CHECK-NEXT: 9 4 1.33 * * rorw %cl, (%rax) +# CHECK-NEXT: 1 2 2.00 roll %edi +# CHECK-NEXT: 1 2 2.00 rorl %edi +# CHECK-NEXT: 9 5 2.00 * * roll (%rax) +# CHECK-NEXT: 9 5 2.00 * * rorl (%rax) +# CHECK-NEXT: 1 2 2.00 roll $7, %edi +# CHECK-NEXT: 1 2 2.00 rorl $7, %edi +# CHECK-NEXT: 9 5 2.00 * * roll $7, (%rax) +# CHECK-NEXT: 9 5 2.00 * * rorl $7, (%rax) +# CHECK-NEXT: 9 1 1.33 roll %cl, %edi +# CHECK-NEXT: 9 1 1.33 rorl %cl, %edi +# CHECK-NEXT: 9 4 1.33 * * roll %cl, (%rax) +# CHECK-NEXT: 9 4 1.33 * * rorl %cl, (%rax) +# CHECK-NEXT: 1 2 2.00 rolq %rdi +# CHECK-NEXT: 1 2 2.00 rorq %rdi +# CHECK-NEXT: 9 5 2.00 * * rolq (%rax) +# CHECK-NEXT: 9 5 2.00 * * rorq (%rax) +# CHECK-NEXT: 1 2 2.00 rolq $7, %rdi +# CHECK-NEXT: 1 2 2.00 rorq $7, %rdi +# CHECK-NEXT: 9 5 2.00 * * rolq $7, (%rax) +# CHECK-NEXT: 9 5 2.00 * * rorq $7, (%rax) +# CHECK-NEXT: 9 1 1.33 rolq %cl, %rdi +# CHECK-NEXT: 9 1 1.33 rorq %cl, %rdi +# CHECK-NEXT: 9 4 1.33 * * rolq %cl, (%rax) +# CHECK-NEXT: 9 4 1.33 * * rorq %cl, (%rax) +# CHECK-NEXT: 4 1 2.00 sahf +# CHECK-NEXT: 1 2 2.00 sarb %dil +# CHECK-NEXT: 1 2 2.00 shlb %dil +# CHECK-NEXT: 1 2 2.00 shrb %dil +# CHECK-NEXT: 1 5 2.00 * * sarb (%rax) +# CHECK-NEXT: 1 5 2.00 * * shlb (%rax) +# CHECK-NEXT: 1 5 2.00 * * shrb (%rax) +# CHECK-NEXT: 1 2 2.00 sarb $7, %dil +# CHECK-NEXT: 1 2 2.00 shlb $7, %dil +# CHECK-NEXT: 1 2 2.00 shrb $7, %dil +# CHECK-NEXT: 1 5 2.00 * * sarb $7, (%rax) +# CHECK-NEXT: 1 5 2.00 * * shlb $7, (%rax) +# CHECK-NEXT: 1 5 2.00 * * shrb $7, (%rax) +# CHECK-NEXT: 1 2 1.33 sarb %cl, %dil +# CHECK-NEXT: 1 2 1.33 shlb %cl, %dil +# CHECK-NEXT: 1 2 1.33 shrb %cl, %dil +# CHECK-NEXT: 1 5 1.33 * * sarb %cl, (%rax) +# CHECK-NEXT: 1 5 1.33 * * shlb %cl, (%rax) +# CHECK-NEXT: 1 5 1.33 * * shrb %cl, (%rax) +# CHECK-NEXT: 1 2 2.00 sarw %di +# CHECK-NEXT: 1 2 2.00 shlw %di +# CHECK-NEXT: 1 2 2.00 shrw %di +# CHECK-NEXT: 1 5 2.00 * * sarw (%rax) +# CHECK-NEXT: 1 5 2.00 * * shlw (%rax) +# CHECK-NEXT: 1 5 2.00 * * shrw (%rax) +# CHECK-NEXT: 1 2 2.00 sarw $7, %di +# CHECK-NEXT: 1 2 2.00 shlw $7, %di +# CHECK-NEXT: 1 2 2.00 shrw $7, %di +# CHECK-NEXT: 1 5 2.00 * * sarw $7, (%rax) +# CHECK-NEXT: 1 5 2.00 * * shlw $7, (%rax) +# CHECK-NEXT: 1 5 2.00 * * shrw $7, (%rax) +# CHECK-NEXT: 1 2 1.33 sarw %cl, %di +# CHECK-NEXT: 1 2 1.33 shlw %cl, %di +# CHECK-NEXT: 1 2 1.33 shrw %cl, %di +# CHECK-NEXT: 1 5 1.33 * * sarw %cl, (%rax) +# CHECK-NEXT: 1 5 1.33 * * shlw %cl, (%rax) +# CHECK-NEXT: 1 5 1.33 * * shrw %cl, (%rax) +# CHECK-NEXT: 1 2 2.00 sarl %edi +# CHECK-NEXT: 1 2 2.00 shll %edi +# CHECK-NEXT: 1 2 2.00 shrl %edi +# CHECK-NEXT: 1 5 2.00 * * sarl (%rax) +# CHECK-NEXT: 1 5 2.00 * * shll (%rax) +# CHECK-NEXT: 1 5 2.00 * * shrl (%rax) +# CHECK-NEXT: 1 2 2.00 sarl $7, %edi +# CHECK-NEXT: 1 2 2.00 shll $7, %edi +# CHECK-NEXT: 1 2 2.00 shrl $7, %edi +# CHECK-NEXT: 1 5 2.00 * * sarl $7, (%rax) +# CHECK-NEXT: 1 5 2.00 * * shll $7, (%rax) +# CHECK-NEXT: 1 5 2.00 * * shrl $7, (%rax) +# CHECK-NEXT: 1 2 1.33 sarl %cl, %edi +# CHECK-NEXT: 1 2 1.33 shll %cl, %edi +# CHECK-NEXT: 1 2 1.33 shrl %cl, %edi +# CHECK-NEXT: 1 5 1.33 * * sarl %cl, (%rax) +# CHECK-NEXT: 1 5 1.33 * * shll %cl, (%rax) +# CHECK-NEXT: 1 5 1.33 * * shrl %cl, (%rax) +# CHECK-NEXT: 1 2 2.00 sarq %rdi +# CHECK-NEXT: 1 2 2.00 shlq %rdi +# CHECK-NEXT: 1 2 2.00 shrq %rdi +# CHECK-NEXT: 1 5 2.00 * * sarq (%rax) +# CHECK-NEXT: 1 5 2.00 * * shlq (%rax) +# CHECK-NEXT: 1 5 2.00 * * shrq (%rax) +# CHECK-NEXT: 1 2 2.00 sarq $7, %rdi +# CHECK-NEXT: 1 2 2.00 shlq $7, %rdi +# CHECK-NEXT: 1 2 2.00 shrq $7, %rdi +# CHECK-NEXT: 1 5 2.00 * * sarq $7, (%rax) +# CHECK-NEXT: 1 5 2.00 * * shlq $7, (%rax) +# CHECK-NEXT: 1 5 2.00 * * shrq $7, (%rax) +# CHECK-NEXT: 1 2 1.33 sarq %cl, %rdi +# CHECK-NEXT: 1 2 1.33 shlq %cl, %rdi +# CHECK-NEXT: 1 2 1.33 shrq %cl, %rdi +# CHECK-NEXT: 1 5 1.33 * * sarq %cl, (%rax) +# CHECK-NEXT: 1 5 1.33 * * shlq %cl, (%rax) +# CHECK-NEXT: 1 5 1.33 * * shrq %cl, (%rax) +# CHECK-NEXT: 1 2 1.00 sbbb $0, %al +# CHECK-NEXT: 1 2 1.00 sbbb $0, %dil +# CHECK-NEXT: 1 6 1.00 * * sbbb $0, (%rax) +# CHECK-NEXT: 1 2 1.00 sbbb $7, %al +# CHECK-NEXT: 1 2 1.00 sbbb $7, %dil +# CHECK-NEXT: 1 6 1.00 * * sbbb $7, (%rax) +# CHECK-NEXT: 1 2 1.00 sbbb %sil, %dil +# CHECK-NEXT: 1 6 1.00 * * sbbb %sil, (%rax) +# CHECK-NEXT: 1 5 1.00 * sbbb (%rax), %dil +# CHECK-NEXT: 1 2 1.00 sbbw $0, %ax +# CHECK-NEXT: 1 2 1.00 sbbw $0, %di +# CHECK-NEXT: 1 6 1.00 * * sbbw $0, (%rax) +# CHECK-NEXT: 1 2 1.00 sbbw $511, %ax +# CHECK-NEXT: 1 2 1.00 sbbw $511, %di +# CHECK-NEXT: 1 6 1.00 * * sbbw $511, (%rax) +# CHECK-NEXT: 1 2 1.00 sbbw $7, %di +# CHECK-NEXT: 1 6 1.00 * * sbbw $7, (%rax) +# CHECK-NEXT: 1 2 1.00 sbbw %si, %di +# CHECK-NEXT: 1 6 1.00 * * sbbw %si, (%rax) +# CHECK-NEXT: 1 5 1.00 * sbbw (%rax), %di +# CHECK-NEXT: 1 2 1.00 sbbl $0, %eax +# CHECK-NEXT: 1 2 1.00 sbbl $0, %edi +# CHECK-NEXT: 1 6 1.00 * * sbbl $0, (%rax) +# CHECK-NEXT: 1 2 1.00 sbbl $665536, %eax +# CHECK-NEXT: 1 2 1.00 sbbl $665536, %edi +# CHECK-NEXT: 1 6 1.00 * * sbbl $665536, (%rax) +# CHECK-NEXT: 1 2 1.00 sbbl $7, %edi +# CHECK-NEXT: 1 6 1.00 * * sbbl $7, (%rax) +# CHECK-NEXT: 1 2 1.00 sbbl %esi, %edi +# CHECK-NEXT: 1 6 1.00 * * sbbl %esi, (%rax) +# CHECK-NEXT: 1 5 1.00 * sbbl (%rax), %edi +# CHECK-NEXT: 1 2 1.00 sbbq $0, %rax +# CHECK-NEXT: 1 2 1.00 sbbq $0, %rdi +# CHECK-NEXT: 1 6 1.00 * * sbbq $0, (%rax) +# CHECK-NEXT: 1 2 1.00 sbbq $665536, %rax +# CHECK-NEXT: 1 2 1.00 sbbq $665536, %rdi +# CHECK-NEXT: 1 6 1.00 * * sbbq $665536, (%rax) +# CHECK-NEXT: 1 2 1.00 sbbq $7, %rdi +# CHECK-NEXT: 1 6 1.00 * * sbbq $7, (%rax) +# CHECK-NEXT: 1 2 1.00 sbbq %rsi, %rdi +# CHECK-NEXT: 1 6 1.00 * * sbbq %rsi, (%rax) +# CHECK-NEXT: 1 5 1.00 * sbbq (%rax), %rdi +# CHECK-NEXT: 13 100 9.00 U scasb %es:(%rdi), %al +# CHECK-NEXT: 13 100 9.00 U scasw %es:(%rdi), %ax +# CHECK-NEXT: 13 100 9.00 U scasl %es:(%rdi), %eax +# CHECK-NEXT: 13 100 9.00 U scasq %es:(%rdi), %rax +# CHECK-NEXT: 1 1 2.00 seto %al +# CHECK-NEXT: 1 3 2.00 * seto (%rax) +# CHECK-NEXT: 1 1 2.00 setno %al +# CHECK-NEXT: 1 3 2.00 * setno (%rax) +# CHECK-NEXT: 1 1 2.00 setb %al +# CHECK-NEXT: 1 3 2.00 * setb (%rax) +# CHECK-NEXT: 1 1 2.00 setae %al +# CHECK-NEXT: 1 3 2.00 * setae (%rax) +# CHECK-NEXT: 1 1 2.00 sete %al +# CHECK-NEXT: 1 3 2.00 * sete (%rax) +# CHECK-NEXT: 1 1 2.00 setne %al +# CHECK-NEXT: 1 3 2.00 * setne (%rax) +# CHECK-NEXT: 1 1 2.00 seta %al +# CHECK-NEXT: 1 3 2.00 * seta (%rax) +# CHECK-NEXT: 1 1 2.00 setbe %al +# CHECK-NEXT: 1 3 2.00 * setbe (%rax) +# CHECK-NEXT: 1 1 2.00 sets %al +# CHECK-NEXT: 1 3 2.00 * sets (%rax) +# CHECK-NEXT: 1 1 2.00 setns %al +# CHECK-NEXT: 1 3 2.00 * setns (%rax) +# CHECK-NEXT: 1 1 2.00 setp %al +# CHECK-NEXT: 1 3 2.00 * setp (%rax) +# CHECK-NEXT: 1 1 2.00 setnp %al +# CHECK-NEXT: 1 3 2.00 * setnp (%rax) +# CHECK-NEXT: 1 1 2.00 setl %al +# CHECK-NEXT: 1 3 2.00 * setl (%rax) +# CHECK-NEXT: 1 1 2.00 setge %al +# CHECK-NEXT: 1 3 2.00 * setge (%rax) +# CHECK-NEXT: 1 1 2.00 setg %al +# CHECK-NEXT: 1 3 2.00 * setg (%rax) +# CHECK-NEXT: 1 1 2.00 setle %al +# CHECK-NEXT: 1 3 2.00 * setle (%rax) +# CHECK-NEXT: 7 3 3.00 shldw %cl, %si, %di +# CHECK-NEXT: 7 3 3.00 shrdw %cl, %si, %di +# CHECK-NEXT: 8 6 4.00 * * shldw %cl, %si, (%rax) +# CHECK-NEXT: 8 6 4.00 * * shrdw %cl, %si, (%rax) +# CHECK-NEXT: 6 3 2.67 shldw $7, %si, %di +# CHECK-NEXT: 6 3 2.67 shrdw $7, %si, %di +# CHECK-NEXT: 8 6 4.33 * * shldw $7, %si, (%rax) +# CHECK-NEXT: 8 6 4.33 * * shrdw $7, %si, (%rax) +# CHECK-NEXT: 7 3 3.00 shldl %cl, %esi, %edi +# CHECK-NEXT: 7 3 3.00 shrdl %cl, %esi, %edi +# CHECK-NEXT: 8 6 4.00 * * shldl %cl, %esi, (%rax) +# CHECK-NEXT: 8 6 4.00 * * shrdl %cl, %esi, (%rax) +# CHECK-NEXT: 6 3 2.67 shldl $7, %esi, %edi +# CHECK-NEXT: 6 3 2.67 shrdl $7, %esi, %edi +# CHECK-NEXT: 8 6 4.33 * * shldl $7, %esi, (%rax) +# CHECK-NEXT: 8 6 4.33 * * shrdl $7, %esi, (%rax) +# CHECK-NEXT: 7 3 3.00 shldq %cl, %rsi, %rdi +# CHECK-NEXT: 7 3 3.00 shrdq %cl, %rsi, %rdi +# CHECK-NEXT: 8 6 4.00 * * shldq %cl, %rsi, (%rax) +# CHECK-NEXT: 8 6 4.00 * * shrdq %cl, %rsi, (%rax) +# CHECK-NEXT: 6 3 2.67 shldq $7, %rsi, %rdi +# CHECK-NEXT: 6 3 2.67 shrdq $7, %rsi, %rdi +# CHECK-NEXT: 8 6 4.33 * * shldq $7, %rsi, (%rax) +# CHECK-NEXT: 8 6 4.33 * * shrdq $7, %rsi, (%rax) +# CHECK-NEXT: 1 2 1.00 U stc +# CHECK-NEXT: 1 2 1.00 U std +# CHECK-NEXT: 13 100 9.00 U stosb %al, %es:(%rdi) +# CHECK-NEXT: 13 100 9.00 U stosw %ax, %es:(%rdi) +# CHECK-NEXT: 13 100 9.00 U stosl %eax, %es:(%rdi) +# CHECK-NEXT: 13 100 9.00 U stosq %rax, %es:(%rdi) +# CHECK-NEXT: 1 2 1.00 subb $7, %al +# CHECK-NEXT: 1 2 1.00 subb $7, %dil +# CHECK-NEXT: 1 6 1.00 * * subb $7, (%rax) +# CHECK-NEXT: 1 2 1.00 subb %sil, %dil +# CHECK-NEXT: 1 6 1.00 * * subb %sil, (%rax) +# CHECK-NEXT: 1 5 1.00 * subb (%rax), %dil +# CHECK-NEXT: 1 2 1.00 subw $511, %ax +# CHECK-NEXT: 1 2 1.00 subw $511, %di +# CHECK-NEXT: 1 6 1.00 * * subw $511, (%rax) +# CHECK-NEXT: 1 2 1.00 subw $7, %di +# CHECK-NEXT: 1 6 1.00 * * subw $7, (%rax) +# CHECK-NEXT: 1 2 1.00 subw %si, %di +# CHECK-NEXT: 1 6 1.00 * * subw %si, (%rax) +# CHECK-NEXT: 1 5 1.00 * subw (%rax), %di +# CHECK-NEXT: 1 2 1.00 subl $665536, %eax +# CHECK-NEXT: 1 2 1.00 subl $665536, %edi +# CHECK-NEXT: 1 6 1.00 * * subl $665536, (%rax) +# CHECK-NEXT: 1 2 1.00 subl $7, %edi +# CHECK-NEXT: 1 6 1.00 * * subl $7, (%rax) +# CHECK-NEXT: 1 2 1.00 subl %esi, %edi +# CHECK-NEXT: 1 6 1.00 * * subl %esi, (%rax) +# CHECK-NEXT: 1 5 1.00 * subl (%rax), %edi +# CHECK-NEXT: 1 2 1.00 subq $665536, %rax +# CHECK-NEXT: 1 2 1.00 subq $665536, %rdi +# CHECK-NEXT: 1 6 1.00 * * subq $665536, (%rax) +# CHECK-NEXT: 1 2 1.00 subq $7, %rdi +# CHECK-NEXT: 1 6 1.00 * * subq $7, (%rax) +# CHECK-NEXT: 1 2 1.00 subq %rsi, %rdi +# CHECK-NEXT: 1 6 1.00 * * subq %rsi, (%rax) +# CHECK-NEXT: 1 5 1.00 * subq (%rax), %rdi +# CHECK-NEXT: 1 2 1.00 testb $7, %al +# CHECK-NEXT: 1 2 1.00 testb $7, %dil +# CHECK-NEXT: 1 5 1.00 * testb $7, (%rax) +# CHECK-NEXT: 1 2 1.00 testb %sil, %dil +# CHECK-NEXT: 1 5 1.00 * testb %sil, (%rax) +# CHECK-NEXT: 1 2 1.00 testw $511, %ax +# CHECK-NEXT: 1 2 1.00 testw $511, %di +# CHECK-NEXT: 1 5 1.00 * testw $511, (%rax) +# CHECK-NEXT: 1 2 1.00 testw $7, %di +# CHECK-NEXT: 1 5 1.00 * testw $7, (%rax) +# CHECK-NEXT: 1 2 1.00 testw %si, %di +# CHECK-NEXT: 1 5 1.00 * testw %si, (%rax) +# CHECK-NEXT: 1 2 1.00 testl $665536, %eax +# CHECK-NEXT: 1 2 1.00 testl $665536, %edi +# CHECK-NEXT: 1 5 1.00 * testl $665536, (%rax) +# CHECK-NEXT: 1 2 1.00 testl $7, %edi +# CHECK-NEXT: 1 5 1.00 * testl $7, (%rax) +# CHECK-NEXT: 1 2 1.00 testl %esi, %edi +# CHECK-NEXT: 1 5 1.00 * testl %esi, (%rax) +# CHECK-NEXT: 1 2 1.00 testq $665536, %rax +# CHECK-NEXT: 1 2 1.00 testq $665536, %rdi +# CHECK-NEXT: 1 5 1.00 * testq $665536, (%rax) +# CHECK-NEXT: 1 2 1.00 testq $7, %rdi +# CHECK-NEXT: 1 5 1.00 * testq $7, (%rax) +# CHECK-NEXT: 1 2 1.00 testq %rsi, %rdi +# CHECK-NEXT: 1 5 1.00 * testq %rsi, (%rax) +# CHECK-NEXT: 1 100 42.00 * U ud2 +# CHECK-NEXT: 1 100 42.00 U wrmsr +# CHECK-NEXT: 3 1 1.67 xaddb %bl, %cl +# CHECK-NEXT: 1 5 1.00 * * xaddb %bl, (%rcx) +# CHECK-NEXT: 3 1 1.67 xaddw %bx, %cx +# CHECK-NEXT: 1 5 1.00 * * xaddw %ax, (%rbx) +# CHECK-NEXT: 3 1 1.67 xaddl %ebx, %ecx +# CHECK-NEXT: 1 5 1.00 * * xaddl %eax, (%rbx) +# CHECK-NEXT: 3 1 1.67 xaddq %rbx, %rcx +# CHECK-NEXT: 1 5 1.00 * * xaddq %rax, (%rbx) +# CHECK-NEXT: 3 1 1.67 xchgb %bl, %cl +# CHECK-NEXT: 1 5 1.00 * * xchgb %bl, (%rbx) +# CHECK-NEXT: 3 1 1.67 xchgw %bx, %ax +# CHECK-NEXT: 3 1 1.67 xchgw %bx, %cx +# CHECK-NEXT: 1 5 1.00 * * xchgw %ax, (%rbx) +# CHECK-NEXT: 3 1 1.67 xchgl %ebx, %eax +# CHECK-NEXT: 3 1 1.67 xchgl %ebx, %ecx +# CHECK-NEXT: 1 5 1.00 * * xchgl %eax, (%rbx) +# CHECK-NEXT: 3 1 1.67 xchgq %rbx, %rax +# CHECK-NEXT: 3 1 1.67 xchgq %rbx, %rcx +# CHECK-NEXT: 1 5 1.00 * * xchgq %rax, (%rbx) +# CHECK-NEXT: 1 4 0.50 * xlatb +# CHECK-NEXT: 1 2 1.00 xorb $7, %al +# CHECK-NEXT: 1 2 1.00 xorb $7, %dil +# CHECK-NEXT: 1 6 1.00 * * xorb $7, (%rax) +# CHECK-NEXT: 1 2 1.00 xorb %sil, %dil +# CHECK-NEXT: 1 6 1.00 * * xorb %sil, (%rax) +# CHECK-NEXT: 1 5 1.00 * xorb (%rax), %dil +# CHECK-NEXT: 1 2 1.00 xorw $511, %ax +# CHECK-NEXT: 1 2 1.00 xorw $511, %di +# CHECK-NEXT: 1 6 1.00 * * xorw $511, (%rax) +# CHECK-NEXT: 1 2 1.00 xorw $7, %di +# CHECK-NEXT: 1 6 1.00 * * xorw $7, (%rax) +# CHECK-NEXT: 1 2 1.00 xorw %si, %di +# CHECK-NEXT: 1 6 1.00 * * xorw %si, (%rax) +# CHECK-NEXT: 1 5 1.00 * xorw (%rax), %di +# CHECK-NEXT: 1 2 1.00 xorl $665536, %eax +# CHECK-NEXT: 1 2 1.00 xorl $665536, %edi +# CHECK-NEXT: 1 6 1.00 * * xorl $665536, (%rax) +# CHECK-NEXT: 1 2 1.00 xorl $7, %edi +# CHECK-NEXT: 1 6 1.00 * * xorl $7, (%rax) +# CHECK-NEXT: 1 2 1.00 xorl %esi, %edi +# CHECK-NEXT: 1 6 1.00 * * xorl %esi, (%rax) +# CHECK-NEXT: 1 5 1.00 * xorl (%rax), %edi +# CHECK-NEXT: 1 2 1.00 xorq $665536, %rax +# CHECK-NEXT: 1 2 1.00 xorq $665536, %rdi +# CHECK-NEXT: 1 6 1.00 * * xorq $665536, (%rax) +# CHECK-NEXT: 1 2 1.00 xorq $7, %rdi +# CHECK-NEXT: 1 6 1.00 * * xorq $7, (%rax) +# CHECK-NEXT: 1 2 1.00 xorq %rsi, %rdi +# CHECK-NEXT: 1 6 1.00 * * xorq %rsi, (%rax) +# CHECK-NEXT: 1 5 1.00 * xorq (%rax), %rdi # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: 160.00 - 596.50 238.00 230.00 596.50 324.50 324.50 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - 198.33 181.33 181.33 2823.00 2823.00 2823.00 - - - - - - 106.00 352.67 318.67 318.67 280.50 280.50 165.00 165.00 115.50 115.50 # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcb $0, %al -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcb $0, %dil -# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcb $0, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcb $7, %al -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcb $7, %dil -# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcb $7, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcb %sil, %dil -# CHECK-NEXT: - - 1.33 0.33 1.00 1.33 1.00 1.00 adcb %sil, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 adcb (%rax), %dil -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcw $0, %ax -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcw $0, %di -# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcw $0, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcw $511, %ax -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcw $511, %di -# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcw $511, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcw $7, %di -# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcw $7, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcw %si, %di -# CHECK-NEXT: - - 1.33 0.33 1.00 1.33 1.00 1.00 adcw %si, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 adcw (%rax), %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcl $0, %eax -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcl $0, %edi -# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcl $0, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcl $665536, %eax -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcl $665536, %edi -# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcl $665536, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcl $7, %edi -# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcl $7, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcl %esi, %edi -# CHECK-NEXT: - - 1.33 0.33 1.00 1.33 1.00 1.00 adcl %esi, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 adcl (%rax), %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcq $0, %rax -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcq $0, %rdi -# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcq $0, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcq $665536, %rax -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcq $665536, %rdi -# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcq $665536, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcq $7, %rdi -# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 adcq $7, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - adcq %rsi, %rdi -# CHECK-NEXT: - - 1.33 0.33 1.00 1.33 1.00 1.00 adcq %rsi, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 adcq (%rax), %rdi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addb $7, %al -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addb $7, %dil -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addb $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addb %sil, %dil -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addb %sil, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 addb (%rax), %dil -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addw $511, %ax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addw $511, %di -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addw $511, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addw $7, %di -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addw $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addw %si, %di -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addw %si, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 addw (%rax), %di -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addl $665536, %eax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addl $665536, %edi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addl $665536, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addl $7, %edi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addl $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addl %esi, %edi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addl %esi, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 addl (%rax), %edi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addq $665536, %rax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addq $665536, %rdi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addq $665536, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addq $7, %rdi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addq $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - addq %rsi, %rdi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 addq %rsi, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 addq (%rax), %rdi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andb $7, %al -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andb $7, %dil -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andb $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andb %sil, %dil -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andb %sil, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 andb (%rax), %dil -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andw $511, %ax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andw $511, %di -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andw $511, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andw $7, %di -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andw $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andw %si, %di -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andw %si, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 andw (%rax), %di -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andl $665536, %eax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andl $665536, %edi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andl $665536, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andl $7, %edi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andl $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andl %esi, %edi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andl %esi, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 andl (%rax), %edi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andq $665536, %rax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andq $665536, %rdi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andq $665536, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andq $7, %rdi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andq $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - andq %rsi, %rdi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 andq %rsi, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 andq (%rax), %rdi -# CHECK-NEXT: - - - 1.00 - - - - bsfw %si, %di -# CHECK-NEXT: - - - 1.00 - - - - bsrw %si, %di -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 bsfw (%rax), %di -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 bsrw (%rax), %di -# CHECK-NEXT: - - - 1.00 - - - - bsfl %esi, %edi -# CHECK-NEXT: - - - 1.00 - - - - bsrl %esi, %edi -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 bsfl (%rax), %edi -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 bsrl (%rax), %edi -# CHECK-NEXT: - - - 1.00 - - - - bsfq %rsi, %rdi -# CHECK-NEXT: - - - 1.00 - - - - bsrq %rsi, %rdi -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 bsfq (%rax), %rdi -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 bsrq (%rax), %rdi -# CHECK-NEXT: - - - 1.00 - - - - bswapl %eax -# CHECK-NEXT: - - 0.50 1.00 - 0.50 - - bswapq %rax -# CHECK-NEXT: - - 0.50 - - 0.50 - - btw %si, %di -# CHECK-NEXT: - - 0.50 - - 0.50 - - btcw %si, %di -# CHECK-NEXT: - - 0.50 - - 0.50 - - btrw %si, %di -# CHECK-NEXT: - - 0.50 - - 0.50 - - btsw %si, %di -# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btw %si, (%rax) -# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btcw %si, (%rax) -# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btrw %si, (%rax) -# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btsw %si, (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - btw $7, %di -# CHECK-NEXT: - - 0.50 - - 0.50 - - btcw $7, %di -# CHECK-NEXT: - - 0.50 - - 0.50 - - btrw $7, %di -# CHECK-NEXT: - - 0.50 - - 0.50 - - btsw $7, %di -# CHECK-NEXT: - - 0.50 - - 0.50 0.50 0.50 btw $7, (%rax) -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btcw $7, (%rax) -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btrw $7, (%rax) -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btsw $7, (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - btl %esi, %edi -# CHECK-NEXT: - - 0.50 - - 0.50 - - btcl %esi, %edi -# CHECK-NEXT: - - 0.50 - - 0.50 - - btrl %esi, %edi -# CHECK-NEXT: - - 0.50 - - 0.50 - - btsl %esi, %edi -# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btl %esi, (%rax) -# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btcl %esi, (%rax) -# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btrl %esi, (%rax) -# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btsl %esi, (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - btl $7, %edi -# CHECK-NEXT: - - 0.50 - - 0.50 - - btcl $7, %edi -# CHECK-NEXT: - - 0.50 - - 0.50 - - btrl $7, %edi -# CHECK-NEXT: - - 0.50 - - 0.50 - - btsl $7, %edi -# CHECK-NEXT: - - 0.50 - - 0.50 0.50 0.50 btl $7, (%rax) -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btcl $7, (%rax) -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btrl $7, (%rax) -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btsl $7, (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - btq %rsi, %rdi -# CHECK-NEXT: - - 0.50 - - 0.50 - - btcq %rsi, %rdi -# CHECK-NEXT: - - 0.50 - - 0.50 - - btrq %rsi, %rdi -# CHECK-NEXT: - - 0.50 - - 0.50 - - btsq %rsi, %rdi -# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btq %rsi, (%rax) -# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btcq %rsi, (%rax) -# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btrq %rsi, (%rax) -# CHECK-NEXT: - - 0.83 0.33 1.00 1.83 1.00 1.00 btsq %rsi, (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - btq $7, %rdi -# CHECK-NEXT: - - 0.50 - - 0.50 - - btcq $7, %rdi -# CHECK-NEXT: - - 0.50 - - 0.50 - - btrq $7, %rdi -# CHECK-NEXT: - - 0.50 - - 0.50 - - btsq $7, %rdi -# CHECK-NEXT: - - 0.50 - - 0.50 0.50 0.50 btq $7, (%rax) -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btcq $7, (%rax) -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btrq $7, (%rax) -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 btsq $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cbtw -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cwtl -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cltq -# CHECK-NEXT: - - 1.33 0.33 - 0.33 - - cwtd -# CHECK-NEXT: - - 0.50 - - 0.50 - - cltd -# CHECK-NEXT: - - 0.50 - - 0.50 - - cqto -# CHECK-NEXT: - - - - - - - - clc -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cld -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmc -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpb $7, %al -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpb $7, %dil -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpb $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpb %sil, %dil -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpb %sil, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpb (%rax), %dil -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpw $511, %ax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpw $511, %di -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpw $511, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpw $7, %di -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpw $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpw %si, %di -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpw %si, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpw (%rax), %di -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpl $665536, %eax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpl $665536, %edi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpl $665536, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpl $7, %edi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpl $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpl %esi, %edi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpl %esi, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpl (%rax), %edi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpq $665536, %rax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpq $665536, %rdi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpq $665536, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpq $7, %rdi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpq $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cmpq %rsi, %rdi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpq %rsi, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 cmpq (%rax), %rdi -# CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsb %es:(%rdi), (%rsi) -# CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsw %es:(%rdi), (%rsi) -# CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsl %es:(%rdi), (%rsi) -# CHECK-NEXT: - - 1.00 1.00 - 1.00 1.00 1.00 cmpsq %es:(%rdi), (%rsi) -# CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgb %cl, %bl -# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgb %cl, (%rbx) -# CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgw %cx, %bx -# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgw %cx, (%rbx) -# CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgl %ecx, %ebx -# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgl %ecx, (%rbx) -# CHECK-NEXT: - - 1.50 1.00 - 1.50 - - cmpxchgq %rcx, %rbx -# CHECK-NEXT: - - 0.33 0.33 1.00 2.33 1.00 1.00 cmpxchgq %rcx, (%rbx) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - cpuid -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - decb %dil -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 decb (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - decw %di -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 decw (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - decl %edi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 decl (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - decq %rdi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 decq (%rax) -# CHECK-NEXT: 10.00 - 1.00 - - - - - divb %dil -# CHECK-NEXT: 10.00 - 1.00 - - - 0.50 0.50 divb (%rax) -# CHECK-NEXT: 10.00 - 1.00 - - - - - divw %si -# CHECK-NEXT: 10.00 - 1.00 - - - 0.50 0.50 divw (%rax) -# CHECK-NEXT: 10.00 - 1.00 - - - - - divl %edx -# CHECK-NEXT: 10.00 - 1.00 - - - 0.50 0.50 divl (%rax) -# CHECK-NEXT: 10.00 - 1.00 - - - - - divq %rcx -# CHECK-NEXT: 10.00 - 1.00 - - - 0.50 0.50 divq (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - enter $7, $4095 -# CHECK-NEXT: 10.00 - 1.00 - - - - - idivb %dil -# CHECK-NEXT: 10.00 - 1.00 - - - 0.50 0.50 idivb (%rax) -# CHECK-NEXT: 10.00 - 1.00 - - - - - idivw %si -# CHECK-NEXT: 10.00 - 1.00 - - - 0.50 0.50 idivw (%rax) -# CHECK-NEXT: 10.00 - 1.00 - - - - - idivl %edx -# CHECK-NEXT: 10.00 - 1.00 - - - 0.50 0.50 idivl (%rax) -# CHECK-NEXT: 10.00 - 1.00 - - - - - idivq %rcx -# CHECK-NEXT: 10.00 - 1.00 - - - 0.50 0.50 idivq (%rax) -# CHECK-NEXT: - - - 1.00 - - - - imulb %dil -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 imulb (%rax) -# CHECK-NEXT: - - 1.17 1.67 - 1.17 - - imulw %di -# CHECK-NEXT: - - 1.17 1.67 - 1.17 0.50 0.50 imulw (%rax) -# CHECK-NEXT: - - - 1.00 - - - - imulw %si, %di -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 imulw (%rax), %di -# CHECK-NEXT: - - 0.33 1.33 - 0.33 - - imulw $511, %si, %di -# CHECK-NEXT: - - 0.33 1.33 - 0.33 0.50 0.50 imulw $511, (%rax), %di -# CHECK-NEXT: - - 0.33 1.33 - 0.33 - - imulw $7, %si, %di -# CHECK-NEXT: - - 0.33 1.33 - 0.33 0.50 0.50 imulw $7, (%rax), %di -# CHECK-NEXT: - - 0.83 1.33 - 0.83 - - imull %edi -# CHECK-NEXT: - - 0.83 1.33 - 0.83 0.50 0.50 imull (%rax) -# CHECK-NEXT: - - - 1.00 - - - - imull %esi, %edi -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 imull (%rax), %edi -# CHECK-NEXT: - - - 1.00 - - - - imull $665536, %esi, %edi -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 imull $665536, (%rax), %edi -# CHECK-NEXT: - - - 1.00 - - - - imull $7, %esi, %edi -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 imull $7, (%rax), %edi -# CHECK-NEXT: - - 1.00 1.00 - - - - imulq %rdi -# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 imulq (%rax) -# CHECK-NEXT: - - - 1.00 - - - - imulq %rsi, %rdi -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 imulq (%rax), %rdi -# CHECK-NEXT: - - - 1.00 - - - - imulq $665536, %rsi, %rdi -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 imulq $665536, (%rax), %rdi -# CHECK-NEXT: - - - 1.00 - - - - imulq $7, %rsi, %rdi -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 imulq $7, (%rax), %rdi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - inb $7, %al -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - inb %dx, %al -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - inw $7, %ax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - inw %dx, %ax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - inl $7, %eax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - inl %dx, %eax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - incb %dil -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 incb (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - incw %di -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 incw (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - incl %edi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 incl (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - incq %rdi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 incq (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - insb %dx, %es:(%rdi) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - insw %dx, %es:(%rdi) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - insl %dx, %es:(%rdi) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - int $7 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - invlpg (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - invlpga %rax, %ecx -# CHECK-NEXT: - - 0.50 - - 0.50 - - lahf -# CHECK-NEXT: - - 0.67 0.67 - 0.67 0.50 0.50 leave -# CHECK-NEXT: - - 0.67 0.67 - 0.67 0.50 0.50 lodsb (%rsi), %al -# CHECK-NEXT: - - 0.67 0.67 - 0.67 0.50 0.50 lodsw (%rsi), %ax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 lodsl (%rsi), %eax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 lodsq (%rsi), %rax -# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 movsb (%rsi), %es:(%rdi) -# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 movsw (%rsi), %es:(%rdi) -# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 movsl (%rsi), %es:(%rdi) -# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 movsq (%rsi), %es:(%rdi) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movsbw %al, %di -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movzbw %al, %di -# CHECK-NEXT: - - - - - - 0.50 0.50 movsbw (%rax), %di -# CHECK-NEXT: - - - - - - 0.50 0.50 movzbw (%rax), %di -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movsbl %al, %edi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movzbl %al, %edi -# CHECK-NEXT: - - - - - - 0.50 0.50 movsbl (%rax), %edi -# CHECK-NEXT: - - - - - - 0.50 0.50 movzbl (%rax), %edi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movsbq %al, %rdi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movzbq %al, %rdi -# CHECK-NEXT: - - - - - - 0.50 0.50 movsbq (%rax), %rdi -# CHECK-NEXT: - - - - - - 0.50 0.50 movzbq (%rax), %rdi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movswl %ax, %edi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movzwl %ax, %edi -# CHECK-NEXT: - - - - - - 0.50 0.50 movswl (%rax), %edi -# CHECK-NEXT: - - - - - - 0.50 0.50 movzwl (%rax), %edi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movswq %ax, %rdi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movzwq %ax, %rdi -# CHECK-NEXT: - - - - - - 0.50 0.50 movswq (%rax), %rdi -# CHECK-NEXT: - - - - - - 0.50 0.50 movzwq (%rax), %rdi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - movslq %eax, %rdi -# CHECK-NEXT: - - - - - - 0.50 0.50 movslq (%rax), %rdi -# CHECK-NEXT: - - - 1.00 - - - - mulb %dil -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 mulb (%rax) -# CHECK-NEXT: - - 1.17 1.67 - 1.17 - - mulw %si -# CHECK-NEXT: - - 1.17 1.67 - 1.17 0.50 0.50 mulw (%rax) -# CHECK-NEXT: - - 0.83 1.33 - 0.83 - - mull %edx -# CHECK-NEXT: - - 0.83 1.33 - 0.83 0.50 0.50 mull (%rax) -# CHECK-NEXT: - - 1.00 1.00 - - - - mulq %rcx -# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 mulq (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - negb %dil -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 negb (%r8) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - negw %si -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 negw (%r9) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - negl %edx -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 negl (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - negq %rcx -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 negq (%r10) -# CHECK-NEXT: - - - - - - - - nop -# CHECK-NEXT: - - - - - - - - nopw %di -# CHECK-NEXT: - - - - - - - - nopw (%rcx) -# CHECK-NEXT: - - - - - - - - nopl %esi -# CHECK-NEXT: - - - - - - - - nopl (%r8) -# CHECK-NEXT: - - - - - - - - nopq %rdx -# CHECK-NEXT: - - - - - - - - nopq (%r9) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - notb %dil -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 notb (%r8) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - notw %si -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 notw (%r9) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - notl %edx -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 notl (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - notq %rcx -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 notq (%r10) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orb $7, %al -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orb $7, %dil -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orb $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orb %sil, %dil -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orb %sil, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 orb (%rax), %dil -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orw $511, %ax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orw $511, %di -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orw $511, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orw $7, %di -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orw $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orw %si, %di -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orw %si, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 orw (%rax), %di -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orl $665536, %eax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orl $665536, %edi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orl $665536, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orl $7, %edi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orl $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orl %esi, %edi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orl %esi, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 orl (%rax), %edi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orq $665536, %rax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orq $665536, %rdi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orq $665536, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orq $7, %rdi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orq $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - orq %rsi, %rdi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 orq %rsi, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 orq (%rax), %rdi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outb %al, $7 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outb %al, %dx -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outw %ax, $7 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outw %ax, %dx -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outl %eax, $7 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outl %eax, %dx -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outsb (%rsi), %dx -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outsw (%rsi), %dx -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - outsl (%rsi), %dx -# CHECK-NEXT: - - 1.00 1.00 - 2.00 - - pause -# CHECK-NEXT: - - 1.50 - - 1.50 - - rclb %dil -# CHECK-NEXT: - - 1.50 - - 1.50 - - rcrb %dil -# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclb (%rax) -# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrb (%rax) -# CHECK-NEXT: - - 4.00 - - 4.00 - - rclb $7, %dil -# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrb $7, %dil -# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclb $7, (%rax) -# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrb $7, (%rax) -# CHECK-NEXT: - - 4.00 - - 4.00 - - rclb %cl, %dil -# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrb %cl, %dil -# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclb %cl, (%rax) -# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrb %cl, (%rax) -# CHECK-NEXT: - - 1.50 - - 1.50 - - rclw %di -# CHECK-NEXT: - - 1.50 - - 1.50 - - rcrw %di -# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclw (%rax) -# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrw (%rax) -# CHECK-NEXT: - - 4.00 - - 4.00 - - rclw $7, %di -# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrw $7, %di -# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclw $7, (%rax) -# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrw $7, (%rax) -# CHECK-NEXT: - - 4.00 - - 4.00 - - rclw %cl, %di -# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrw %cl, %di -# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclw %cl, (%rax) -# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrw %cl, (%rax) -# CHECK-NEXT: - - 1.50 - - 1.50 - - rcll %edi -# CHECK-NEXT: - - 1.50 - - 1.50 - - rcrl %edi -# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcll (%rax) -# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrl (%rax) -# CHECK-NEXT: - - 4.00 - - 4.00 - - rcll $7, %edi -# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrl $7, %edi -# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcll $7, (%rax) -# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrl $7, (%rax) -# CHECK-NEXT: - - 4.00 - - 4.00 - - rcll %cl, %edi -# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrl %cl, %edi -# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcll %cl, (%rax) -# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrl %cl, (%rax) -# CHECK-NEXT: - - 1.50 - - 1.50 - - rclq %rdi -# CHECK-NEXT: - - 1.50 - - 1.50 - - rcrq %rdi -# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclq (%rax) -# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrq (%rax) -# CHECK-NEXT: - - 4.00 - - 4.00 - - rclq $7, %rdi -# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrq $7, %rdi -# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclq $7, (%rax) -# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrq $7, (%rax) -# CHECK-NEXT: - - 4.00 - - 4.00 - - rclq %cl, %rdi -# CHECK-NEXT: - - 4.00 - - 4.00 - - rcrq %cl, %rdi -# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rclq %cl, (%rax) -# CHECK-NEXT: - - 3.50 - - 3.50 2.00 2.00 rcrq %cl, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - rdmsr -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - rdpmc -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - rdtsc -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - rdtscp -# CHECK-NEXT: - - 1.00 - - 1.00 - - rolb %dil -# CHECK-NEXT: - - 1.00 - - 1.00 - - rorb %dil -# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rolb (%rax) -# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rorb (%rax) -# CHECK-NEXT: - - 1.00 - - 1.00 - - rolb $7, %dil -# CHECK-NEXT: - - 1.00 - - 1.00 - - rorb $7, %dil -# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rolb $7, (%rax) -# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rorb $7, (%rax) -# CHECK-NEXT: - - 1.50 - - 1.50 - - rolb %cl, %dil -# CHECK-NEXT: - - 1.50 - - 1.50 - - rorb %cl, %dil -# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 rolb %cl, (%rax) -# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 rorb %cl, (%rax) -# CHECK-NEXT: - - 1.00 - - 1.00 - - rolw %di -# CHECK-NEXT: - - 1.00 - - 1.00 - - rorw %di -# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rolw (%rax) -# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rorw (%rax) -# CHECK-NEXT: - - 1.00 - - 1.00 - - rolw $7, %di -# CHECK-NEXT: - - 1.00 - - 1.00 - - rorw $7, %di -# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rolw $7, (%rax) -# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rorw $7, (%rax) -# CHECK-NEXT: - - 1.50 - - 1.50 - - rolw %cl, %di -# CHECK-NEXT: - - 1.50 - - 1.50 - - rorw %cl, %di -# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 rolw %cl, (%rax) -# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 rorw %cl, (%rax) -# CHECK-NEXT: - - 1.00 - - 1.00 - - roll %edi -# CHECK-NEXT: - - 1.00 - - 1.00 - - rorl %edi -# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 roll (%rax) -# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rorl (%rax) -# CHECK-NEXT: - - 1.00 - - 1.00 - - roll $7, %edi -# CHECK-NEXT: - - 1.00 - - 1.00 - - rorl $7, %edi -# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 roll $7, (%rax) -# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rorl $7, (%rax) -# CHECK-NEXT: - - 1.50 - - 1.50 - - roll %cl, %edi -# CHECK-NEXT: - - 1.50 - - 1.50 - - rorl %cl, %edi -# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 roll %cl, (%rax) -# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 rorl %cl, (%rax) -# CHECK-NEXT: - - 1.00 - - 1.00 - - rolq %rdi -# CHECK-NEXT: - - 1.00 - - 1.00 - - rorq %rdi -# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rolq (%rax) -# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rorq (%rax) -# CHECK-NEXT: - - 1.00 - - 1.00 - - rolq $7, %rdi -# CHECK-NEXT: - - 1.00 - - 1.00 - - rorq $7, %rdi -# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rolq $7, (%rax) -# CHECK-NEXT: - - 1.00 - 1.00 1.00 1.00 1.00 rorq $7, (%rax) -# CHECK-NEXT: - - 1.50 - - 1.50 - - rolq %cl, %rdi -# CHECK-NEXT: - - 1.50 - - 1.50 - - rorq %cl, %rdi -# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 rolq %cl, (%rax) -# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 rorq %cl, (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - sahf -# CHECK-NEXT: - - 0.50 - - 0.50 - - sarb %dil -# CHECK-NEXT: - - 0.50 - - 0.50 - - shlb %dil -# CHECK-NEXT: - - 0.50 - - 0.50 - - shrb %dil -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 sarb (%rax) -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shlb (%rax) -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shrb (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - sarb $7, %dil -# CHECK-NEXT: - - 0.50 - - 0.50 - - shlb $7, %dil -# CHECK-NEXT: - - 0.50 - - 0.50 - - shrb $7, %dil -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 sarb $7, (%rax) -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shlb $7, (%rax) -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shrb $7, (%rax) -# CHECK-NEXT: - - 1.50 - - 1.50 - - sarb %cl, %dil -# CHECK-NEXT: - - 1.50 - - 1.50 - - shlb %cl, %dil -# CHECK-NEXT: - - 1.50 - - 1.50 - - shrb %cl, %dil -# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 sarb %cl, (%rax) -# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 shlb %cl, (%rax) -# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 shrb %cl, (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - sarw %di -# CHECK-NEXT: - - 0.50 - - 0.50 - - shlw %di -# CHECK-NEXT: - - 0.50 - - 0.50 - - shrw %di -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 sarw (%rax) -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shlw (%rax) -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shrw (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - sarw $7, %di -# CHECK-NEXT: - - 0.50 - - 0.50 - - shlw $7, %di -# CHECK-NEXT: - - 0.50 - - 0.50 - - shrw $7, %di -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 sarw $7, (%rax) -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shlw $7, (%rax) -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shrw $7, (%rax) -# CHECK-NEXT: - - 1.50 - - 1.50 - - sarw %cl, %di -# CHECK-NEXT: - - 1.50 - - 1.50 - - shlw %cl, %di -# CHECK-NEXT: - - 1.50 - - 1.50 - - shrw %cl, %di -# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 sarw %cl, (%rax) -# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 shlw %cl, (%rax) -# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 shrw %cl, (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - sarl %edi -# CHECK-NEXT: - - 0.50 - - 0.50 - - shll %edi -# CHECK-NEXT: - - 0.50 - - 0.50 - - shrl %edi -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 sarl (%rax) -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shll (%rax) -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shrl (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - sarl $7, %edi -# CHECK-NEXT: - - 0.50 - - 0.50 - - shll $7, %edi -# CHECK-NEXT: - - 0.50 - - 0.50 - - shrl $7, %edi -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 sarl $7, (%rax) -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shll $7, (%rax) -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shrl $7, (%rax) -# CHECK-NEXT: - - 1.50 - - 1.50 - - sarl %cl, %edi -# CHECK-NEXT: - - 1.50 - - 1.50 - - shll %cl, %edi -# CHECK-NEXT: - - 1.50 - - 1.50 - - shrl %cl, %edi -# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 sarl %cl, (%rax) -# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 shll %cl, (%rax) -# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 shrl %cl, (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - sarq %rdi -# CHECK-NEXT: - - 0.50 - - 0.50 - - shlq %rdi -# CHECK-NEXT: - - 0.50 - - 0.50 - - shrq %rdi -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 sarq (%rax) -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shlq (%rax) -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shrq (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - sarq $7, %rdi -# CHECK-NEXT: - - 0.50 - - 0.50 - - shlq $7, %rdi -# CHECK-NEXT: - - 0.50 - - 0.50 - - shrq $7, %rdi -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 sarq $7, (%rax) -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shlq $7, (%rax) -# CHECK-NEXT: - - 0.50 - 1.00 0.50 1.00 1.00 shrq $7, (%rax) -# CHECK-NEXT: - - 1.50 - - 1.50 - - sarq %cl, %rdi -# CHECK-NEXT: - - 1.50 - - 1.50 - - shlq %cl, %rdi -# CHECK-NEXT: - - 1.50 - - 1.50 - - shrq %cl, %rdi -# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 sarq %cl, (%rax) -# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 shlq %cl, (%rax) -# CHECK-NEXT: - - 1.50 - 1.00 1.50 1.00 1.00 shrq %cl, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbb $0, %al -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbb $0, %dil -# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbb $0, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbb $7, %al -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbb $7, %dil -# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbb $7, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbb %sil, %dil -# CHECK-NEXT: - - 1.33 0.33 1.00 1.33 1.00 1.00 sbbb %sil, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 sbbb (%rax), %dil -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbw $0, %ax -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbw $0, %di -# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbw $0, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbw $511, %ax -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbw $511, %di -# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbw $511, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbw $7, %di -# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbw $7, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbw %si, %di -# CHECK-NEXT: - - 1.33 0.33 1.00 1.33 1.00 1.00 sbbw %si, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 sbbw (%rax), %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbl $0, %eax -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbl $0, %edi -# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbl $0, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbl $665536, %eax -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbl $665536, %edi -# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbl $665536, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbl $7, %edi -# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbl $7, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbl %esi, %edi -# CHECK-NEXT: - - 1.33 0.33 1.00 1.33 1.00 1.00 sbbl %esi, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 sbbl (%rax), %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbq $0, %rax -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbq $0, %rdi -# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbq $0, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbq $665536, %rax -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbq $665536, %rdi -# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbq $665536, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbq $7, %rdi -# CHECK-NEXT: - - 1.00 1.00 1.00 1.00 1.00 1.00 sbbq $7, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - sbbq %rsi, %rdi -# CHECK-NEXT: - - 1.33 0.33 1.00 1.33 1.00 1.00 sbbq %rsi, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 0.50 0.50 sbbq (%rax), %rdi -# CHECK-NEXT: - - 0.67 0.67 - 0.67 - - scasb %es:(%rdi), %al -# CHECK-NEXT: - - 0.67 0.67 - 0.67 - - scasw %es:(%rdi), %ax -# CHECK-NEXT: - - 0.67 0.67 - 0.67 - - scasl %es:(%rdi), %eax -# CHECK-NEXT: - - 0.67 0.67 - 0.67 - - scasq %es:(%rdi), %rax -# CHECK-NEXT: - - 0.50 - - 0.50 - - seto %al -# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 seto (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - setno %al -# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setno (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - setb %al -# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setb (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - setae %al -# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setae (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - sete %al -# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 sete (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - setne %al -# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setne (%rax) -# CHECK-NEXT: - - 1.00 - - 1.00 - - seta %al -# CHECK-NEXT: - - 1.00 - 1.00 1.00 0.50 0.50 seta (%rax) -# CHECK-NEXT: - - 1.00 - - 1.00 - - setbe %al -# CHECK-NEXT: - - 1.00 - 1.00 1.00 0.50 0.50 setbe (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - sets %al -# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 sets (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - setns %al -# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setns (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - setp %al -# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setp (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - setnp %al -# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setnp (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - setl %al -# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setl (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - setge %al -# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setge (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - setg %al -# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setg (%rax) -# CHECK-NEXT: - - 0.50 - - 0.50 - - setle %al -# CHECK-NEXT: - - 0.50 - 1.00 0.50 0.50 0.50 setle (%rax) -# CHECK-NEXT: - - 1.83 0.33 - 1.83 - - shldw %cl, %si, %di -# CHECK-NEXT: - - 1.83 0.33 - 1.83 - - shrdw %cl, %si, %di -# CHECK-NEXT: - - 1.83 0.33 1.00 1.83 1.00 1.00 shldw %cl, %si, (%rax) -# CHECK-NEXT: - - 1.83 0.33 1.00 1.83 1.00 1.00 shrdw %cl, %si, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - shldw $7, %si, %di -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - shrdw $7, %si, %di -# CHECK-NEXT: - - 0.83 0.33 1.00 0.83 1.00 1.00 shldw $7, %si, (%rax) -# CHECK-NEXT: - - 0.83 0.33 1.00 0.83 1.00 1.00 shrdw $7, %si, (%rax) -# CHECK-NEXT: - - 1.83 0.33 - 1.83 - - shldl %cl, %esi, %edi -# CHECK-NEXT: - - 1.83 0.33 - 1.83 - - shrdl %cl, %esi, %edi -# CHECK-NEXT: - - 1.83 0.33 1.00 1.83 1.00 1.00 shldl %cl, %esi, (%rax) -# CHECK-NEXT: - - 1.83 0.33 1.00 1.83 1.00 1.00 shrdl %cl, %esi, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - shldl $7, %esi, %edi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - shrdl $7, %esi, %edi -# CHECK-NEXT: - - 0.83 0.33 1.00 0.83 1.00 1.00 shldl $7, %esi, (%rax) -# CHECK-NEXT: - - 0.83 0.33 1.00 0.83 1.00 1.00 shrdl $7, %esi, (%rax) -# CHECK-NEXT: - - 1.83 0.33 - 1.83 - - shldq %cl, %rsi, %rdi -# CHECK-NEXT: - - 1.83 0.33 - 1.83 - - shrdq %cl, %rsi, %rdi -# CHECK-NEXT: - - 1.83 0.33 1.00 1.83 1.00 1.00 shldq %cl, %rsi, (%rax) -# CHECK-NEXT: - - 1.83 0.33 1.00 1.83 1.00 1.00 shrdq %cl, %rsi, (%rax) -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - shldq $7, %rsi, %rdi -# CHECK-NEXT: - - 0.83 0.33 - 0.83 - - shrdq $7, %rsi, %rdi -# CHECK-NEXT: - - 0.83 0.33 1.00 0.83 1.00 1.00 shldq $7, %rsi, (%rax) -# CHECK-NEXT: - - 0.83 0.33 1.00 0.83 1.00 1.00 shrdq $7, %rsi, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - stc -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - std -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 0.50 0.50 stosb %al, %es:(%rdi) -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 0.50 0.50 stosw %ax, %es:(%rdi) -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 0.50 0.50 stosl %eax, %es:(%rdi) -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 0.50 0.50 stosq %rax, %es:(%rdi) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subb $7, %al -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subb $7, %dil -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subb $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subb %sil, %dil -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subb %sil, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 subb (%rax), %dil -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subw $511, %ax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subw $511, %di -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subw $511, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subw $7, %di -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subw $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subw %si, %di -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subw %si, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 subw (%rax), %di -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subl $665536, %eax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subl $665536, %edi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subl $665536, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subl $7, %edi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subl $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subl %esi, %edi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subl %esi, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 subl (%rax), %edi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subq $665536, %rax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subq $665536, %rdi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subq $665536, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subq $7, %rdi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subq $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - subq %rsi, %rdi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 subq %rsi, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 subq (%rax), %rdi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testb $7, %al -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testb $7, %dil -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testb $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testb %sil, %dil -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testb %sil, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testw $511, %ax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testw $511, %di -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testw $511, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testw $7, %di -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testw $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testw %si, %di -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testw %si, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testl $665536, %eax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testl $665536, %edi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testl $665536, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testl $7, %edi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testl $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testl %esi, %edi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testl %esi, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testq $665536, %rax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testq $665536, %rdi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testq $665536, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testq $7, %rdi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testq $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - testq %rsi, %rdi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 testq %rsi, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - ud2 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - wrmsr -# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xaddb %bl, %cl -# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 xaddb %bl, (%rcx) -# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xaddw %bx, %cx -# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 xaddw %ax, (%rbx) -# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xaddl %ebx, %ecx -# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 xaddl %eax, (%rbx) -# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xaddq %rbx, %rcx -# CHECK-NEXT: - - 0.67 0.67 1.00 0.67 1.00 1.00 xaddq %rax, (%rbx) -# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xchgb %bl, %cl -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xchgb %bl, (%rbx) -# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xchgw %bx, %ax -# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xchgw %bx, %cx -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xchgw %ax, (%rbx) -# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xchgl %ebx, %eax -# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xchgl %ebx, %ecx -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xchgl %eax, (%rbx) -# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xchgq %rbx, %rax -# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - xchgq %rbx, %rcx -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xchgq %rax, (%rbx) -# CHECK-NEXT: - - - - - - 0.50 0.50 xlatb -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorb $7, %al -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorb $7, %dil -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorb $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorb %sil, %dil -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorb %sil, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 xorb (%rax), %dil -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorw $511, %ax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorw $511, %di -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorw $511, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorw $7, %di -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorw $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorw %si, %di -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorw %si, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 xorw (%rax), %di -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorl $665536, %eax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorl $665536, %edi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorl $665536, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorl $7, %edi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorl $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorl %esi, %edi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorl %esi, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 xorl (%rax), %edi -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorq $665536, %rax -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorq $665536, %rdi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorq $665536, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorq $7, %rdi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorq $7, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - xorq %rsi, %rdi -# CHECK-NEXT: - - 0.33 0.33 1.00 0.33 1.00 1.00 xorq %rsi, (%rax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 0.50 0.50 xorq (%rax), %rdi +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - adcb $0, %al +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - adcb $0, %dil +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 adcb $0, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - adcb $7, %al +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - adcb $7, %dil +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 adcb $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - adcb %sil, %dil +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 adcb %sil, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - adcb (%rax), %dil +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - adcw $0, %ax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - adcw $0, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 adcw $0, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - adcw $511, %ax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - adcw $511, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 adcw $511, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - adcw $7, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 adcw $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - adcw %si, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 adcw %si, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - adcw (%rax), %di +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - adcl $0, %eax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - adcl $0, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 adcl $0, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - adcl $665536, %eax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - adcl $665536, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 adcl $665536, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - adcl $7, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 adcl $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - adcl %esi, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 adcl %esi, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - adcl (%rax), %edi +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - adcq $0, %rax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - adcq $0, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 adcq $0, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - adcq $665536, %rax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - adcq $665536, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 adcq $665536, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - adcq $7, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 adcq $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - adcq %rsi, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 adcq %rsi, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - adcq (%rax), %rdi +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - addb $7, %al +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - addb $7, %dil +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 addb $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - addb %sil, %dil +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 addb %sil, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - addb (%rax), %dil +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - addw $511, %ax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - addw $511, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 addw $511, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - addw $7, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 addw $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - addw %si, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 addw %si, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - addw (%rax), %di +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - addl $665536, %eax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - addl $665536, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 addl $665536, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - addl $7, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 addl $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - addl %esi, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 addl %esi, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - addl (%rax), %edi +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - addq $665536, %rax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - addq $665536, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 addq $665536, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - addq $7, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 addq $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - addq %rsi, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 addq %rsi, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - addq (%rax), %rdi +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - andb $7, %al +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - andb $7, %dil +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 andb $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - andb %sil, %dil +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 andb %sil, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - andb (%rax), %dil +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - andw $511, %ax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - andw $511, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 andw $511, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - andw $7, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 andw $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - andw %si, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 andw %si, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - andw (%rax), %di +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - andl $665536, %eax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - andl $665536, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 andl $665536, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - andl $7, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 andl $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - andl %esi, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 andl %esi, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - andl (%rax), %edi +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - andq $665536, %rax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - andq $665536, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 andq $665536, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - andq $7, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 andq $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - andq %rsi, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 andq %rsi, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - andq (%rax), %rdi +# CHECK-NEXT: - - - - 3.00 3.00 3.00 - - - - - - - 0.33 0.33 0.33 - - - - - - bsfw %si, %di +# CHECK-NEXT: - - - - 3.00 3.00 3.00 - - - - - - - 0.33 0.33 0.33 - - - - - - bsrw %si, %di +# CHECK-NEXT: - 0.33 0.33 0.33 3.00 3.00 3.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - bsfw (%rax), %di +# CHECK-NEXT: - 0.33 0.33 0.33 3.00 3.00 3.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - bsrw (%rax), %di +# CHECK-NEXT: - - - - 3.00 3.00 3.00 - - - - - - - 0.33 0.33 0.33 - - - - - - bsfl %esi, %edi +# CHECK-NEXT: - - - - 3.00 3.00 3.00 - - - - - - - 0.33 0.33 0.33 - - - - - - bsrl %esi, %edi +# CHECK-NEXT: - 0.33 0.33 0.33 3.00 3.00 3.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - bsfl (%rax), %edi +# CHECK-NEXT: - 0.33 0.33 0.33 3.00 3.00 3.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - bsrl (%rax), %edi +# CHECK-NEXT: - - - - 3.00 3.00 3.00 - - - - - - - 0.33 0.33 0.33 - - - - - - bsfq %rsi, %rdi +# CHECK-NEXT: - - - - 3.00 3.00 3.00 - - - - - - - 0.33 0.33 0.33 - - - - - - bsrq %rsi, %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 3.00 3.00 3.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - bsfq (%rax), %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 3.00 3.00 3.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - bsrq (%rax), %rdi +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - bswapl %eax +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - bswapq %rax +# CHECK-NEXT: - - - - 1.67 1.67 1.67 - - - - - - - 0.33 0.33 0.33 - - - - - - btw %si, %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - btcw %si, %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - btrw %si, %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - btsw %si, %di +# CHECK-NEXT: - 0.33 0.33 0.33 3.33 3.33 3.33 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - btw %si, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 4.00 4.00 4.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 btcw %si, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 4.00 4.00 4.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 btrw %si, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 4.00 4.00 4.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 btsw %si, (%rax) +# CHECK-NEXT: - - - - 1.67 1.67 1.67 - - - - - - - 0.33 0.33 0.33 - - - - - - btw $7, %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - btcw $7, %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - btrw $7, %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - btsw $7, %di +# CHECK-NEXT: - 0.33 0.33 0.33 4.00 4.00 4.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - btw $7, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 5.00 5.00 5.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 btcw $7, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 5.00 5.00 5.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 btrw $7, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 5.00 5.00 5.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 btsw $7, (%rax) +# CHECK-NEXT: - - - - 1.67 1.67 1.67 - - - - - - - 0.33 0.33 0.33 - - - - - - btl %esi, %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - btcl %esi, %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - btrl %esi, %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - btsl %esi, %edi +# CHECK-NEXT: - 0.33 0.33 0.33 3.33 3.33 3.33 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - btl %esi, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 4.00 4.00 4.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 btcl %esi, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 4.00 4.00 4.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 btrl %esi, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 4.00 4.00 4.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 btsl %esi, (%rax) +# CHECK-NEXT: - - - - 1.67 1.67 1.67 - - - - - - - 0.33 0.33 0.33 - - - - - - btl $7, %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - btcl $7, %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - btrl $7, %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - btsl $7, %edi +# CHECK-NEXT: - 0.33 0.33 0.33 4.00 4.00 4.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - btl $7, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 5.00 5.00 5.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 btcl $7, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 5.00 5.00 5.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 btrl $7, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 5.00 5.00 5.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 btsl $7, (%rax) +# CHECK-NEXT: - - - - 1.67 1.67 1.67 - - - - - - - 0.33 0.33 0.33 - - - - - - btq %rsi, %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - btcq %rsi, %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - btrq %rsi, %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - btsq %rsi, %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 3.33 3.33 3.33 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - btq %rsi, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 4.00 4.00 4.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 btcq %rsi, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 4.00 4.00 4.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 btrq %rsi, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 4.00 4.00 4.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 btsq %rsi, (%rax) +# CHECK-NEXT: - - - - 1.67 1.67 1.67 - - - - - - - 0.33 0.33 0.33 - - - - - - btq $7, %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - btcq $7, %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - btrq $7, %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - btsq $7, %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 4.00 4.00 4.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - btq $7, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 5.00 5.00 5.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 btcq $7, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 5.00 5.00 5.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 btrq $7, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 5.00 5.00 5.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 btsq $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cbtw +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cwtl +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cltq +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cwtd +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cltd +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cqto +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - clc +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cld +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmc +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmpb $7, %al +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmpb $7, %dil +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmpb $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmpb %sil, %dil +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmpb %sil, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmpb (%rax), %dil +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmpw $511, %ax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmpw $511, %di +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmpw $511, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmpw $7, %di +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmpw $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmpw %si, %di +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmpw %si, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmpw (%rax), %di +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmpl $665536, %eax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmpl $665536, %edi +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmpl $665536, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmpl $7, %edi +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmpl $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmpl %esi, %edi +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmpl %esi, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmpl (%rax), %edi +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmpq $665536, %rax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmpq $665536, %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmpq $665536, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmpq $7, %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmpq $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmpq %rsi, %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmpq %rsi, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - cmpq (%rax), %rdi +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmpsb %es:(%rdi), (%rsi) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmpsw %es:(%rdi), (%rsi) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmpsl %es:(%rdi), (%rsi) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cmpsq %es:(%rdi), (%rsi) +# CHECK-NEXT: - - - - 2.33 2.33 2.33 - - - - - - - 0.33 0.33 0.33 - - - - - - cmpxchgb %cl, %bl +# CHECK-NEXT: - 0.67 0.67 0.67 24.33 24.33 24.33 - - - - - - - 0.33 0.33 0.33 1.00 1.00 0.50 0.50 0.50 0.50 cmpxchgb %cl, (%rbx) +# CHECK-NEXT: - - - - 2.33 2.33 2.33 - - - - - - - 0.33 0.33 0.33 - - - - - - cmpxchgw %cx, %bx +# CHECK-NEXT: - 0.67 0.67 0.67 24.33 24.33 24.33 - - - - - - - 0.33 0.33 0.33 1.00 1.00 0.50 0.50 0.50 0.50 cmpxchgw %cx, (%rbx) +# CHECK-NEXT: - - - - 2.33 2.33 2.33 - - - - - - - 0.33 0.33 0.33 - - - - - - cmpxchgl %ecx, %ebx +# CHECK-NEXT: - 0.67 0.67 0.67 24.33 24.33 24.33 - - - - - - - 0.33 0.33 0.33 1.00 1.00 0.50 0.50 0.50 0.50 cmpxchgl %ecx, (%rbx) +# CHECK-NEXT: - - - - 2.33 2.33 2.33 - - - - - - - 0.33 0.33 0.33 - - - - - - cmpxchgq %rcx, %rbx +# CHECK-NEXT: - 0.67 0.67 0.67 24.33 24.33 24.33 - - - - - - - 0.33 0.33 0.33 1.00 1.00 0.50 0.50 0.50 0.50 cmpxchgq %rcx, (%rbx) +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - cpuid +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - decb %dil +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 decb (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - decw %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 decw (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - decl %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 decl (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - decq %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 decq (%rax) +# CHECK-NEXT: - - - - 17.00 17.00 17.00 - - - - - - - 0.33 0.33 0.33 - - - - - - divb %dil +# CHECK-NEXT: - 0.33 0.33 0.33 17.00 17.00 17.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - divb (%rax) +# CHECK-NEXT: - - - - 18.00 18.00 18.00 - - - - - - - 0.33 0.33 0.33 - - - - - - divw %si +# CHECK-NEXT: - 0.33 0.33 0.33 18.00 18.00 18.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - divw (%rax) +# CHECK-NEXT: - - - - 18.00 18.00 18.00 - - - - - - - 0.33 0.33 0.33 - - - - - - divl %edx +# CHECK-NEXT: - 0.33 0.33 0.33 18.00 18.00 18.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - divl (%rax) +# CHECK-NEXT: - - - - 18.00 18.00 18.00 - - - - - - - 0.33 0.33 0.33 - - - - - - divq %rcx +# CHECK-NEXT: - 0.33 0.33 0.33 18.00 18.00 18.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - divq (%rax) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - enter $7, $4095 +# CHECK-NEXT: - - - - 18.00 18.00 18.00 - - - - - - - 0.33 0.33 0.33 - - - - - - idivb %dil +# CHECK-NEXT: - 0.33 0.33 0.33 18.00 18.00 18.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - idivb (%rax) +# CHECK-NEXT: - - - - 25.00 25.00 25.00 - - - - - - - 0.33 0.33 0.33 - - - - - - idivw %si +# CHECK-NEXT: - 0.33 0.33 0.33 25.00 25.00 25.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - idivw (%rax) +# CHECK-NEXT: - - - - 25.00 25.00 25.00 - - - - - - - 0.33 0.33 0.33 - - - - - - idivl %edx +# CHECK-NEXT: - 0.33 0.33 0.33 25.00 25.00 25.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - idivl (%rax) +# CHECK-NEXT: - - - - 25.00 25.00 25.00 - - - - - - - 0.33 0.33 0.33 - - - - - - idivq %rcx +# CHECK-NEXT: - 0.33 0.33 0.33 25.00 25.00 25.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - idivq (%rax) +# CHECK-NEXT: - - - - - - - - - - - - - 3.00 1.00 - - - - - - - - imulb %dil +# CHECK-NEXT: - 1.00 - - - - - - - - - - - 3.00 1.00 - - 0.50 0.50 0.50 0.50 - - imulb (%rax) +# CHECK-NEXT: - - - - - - - - - - - - - 3.00 1.00 - - - - - - - - imulw %di +# CHECK-NEXT: - 1.00 - - - - - - - - - - - 3.00 1.00 - - 0.50 0.50 0.50 0.50 - - imulw (%rax) +# CHECK-NEXT: - - - - - - - - - - - - - 3.00 1.00 - - - - - - - - imulw %si, %di +# CHECK-NEXT: - 1.00 - - - - - - - - - - - 3.00 1.00 - - 0.50 0.50 0.50 0.50 - - imulw (%rax), %di +# CHECK-NEXT: - - - - - - - - - - - - - 3.00 1.00 - - - - - - - - imulw $511, %si, %di +# CHECK-NEXT: - 1.00 - - - - - - - - - - - 3.00 1.00 - - 0.50 0.50 0.50 0.50 - - imulw $511, (%rax), %di +# CHECK-NEXT: - - - - - - - - - - - - - 3.00 1.00 - - - - - - - - imulw $7, %si, %di +# CHECK-NEXT: - 1.00 - - - - - - - - - - - 3.00 1.00 - - 0.50 0.50 0.50 0.50 - - imulw $7, (%rax), %di +# CHECK-NEXT: - - - - - - - - - - - - - 3.00 1.00 - - - - - - - - imull %edi +# CHECK-NEXT: - 1.00 - - - - - - - - - - - 3.00 1.00 - - 0.50 0.50 0.50 0.50 - - imull (%rax) +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 1.00 - - - - - - - - imull %esi, %edi +# CHECK-NEXT: - 1.00 - - - - - - - - - - - 2.00 1.00 - - 0.50 0.50 0.50 0.50 - - imull (%rax), %edi +# CHECK-NEXT: - - - - - - - - - - - - - 3.00 1.00 - - - - - - - - imull $665536, %esi, %edi +# CHECK-NEXT: - 1.00 - - - - - - - - - - - 3.00 1.00 - - 0.50 0.50 0.50 0.50 - - imull $665536, (%rax), %edi +# CHECK-NEXT: - - - - - - - - - - - - - 3.00 1.00 - - - - - - - - imull $7, %esi, %edi +# CHECK-NEXT: - 1.00 - - - - - - - - - - - 3.00 1.00 - - 0.50 0.50 0.50 0.50 - - imull $7, (%rax), %edi +# CHECK-NEXT: - - - - - - - - - - - - - 4.00 1.00 - - - - - - - - imulq %rdi +# CHECK-NEXT: - 1.00 - - - - - - - - - - - 4.00 1.00 - - 0.50 0.50 0.50 0.50 - - imulq (%rax) +# CHECK-NEXT: - - - - - - - - - - - - - 2.00 1.00 - - - - - - - - imulq %rsi, %rdi +# CHECK-NEXT: - 1.00 - - - - - - - - - - - 2.00 1.00 - - 0.50 0.50 0.50 0.50 - - imulq (%rax), %rdi +# CHECK-NEXT: - - - - - - - - - - - - - 4.00 1.00 - - - - - - - - imulq $665536, %rsi, %rdi +# CHECK-NEXT: - 1.00 - - - - - - - - - - - 4.00 1.00 - - 0.50 0.50 0.50 0.50 - - imulq $665536, (%rax), %rdi +# CHECK-NEXT: - - - - - - - - - - - - - 4.00 1.00 - - - - - - - - imulq $7, %rsi, %rdi +# CHECK-NEXT: - 1.00 - - - - - - - - - - - 4.00 1.00 - - 0.50 0.50 0.50 0.50 - - imulq $7, (%rax), %rdi +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - inb $7, %al +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - inb %dx, %al +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - inw $7, %ax +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - inw %dx, %ax +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - inl $7, %eax +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - inl %dx, %eax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - incb %dil +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 incb (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - incw %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 incw (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - incl %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 incl (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - incq %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 incq (%rax) +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - insb %dx, %es:(%rdi) +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - insw %dx, %es:(%rdi) +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - insl %dx, %es:(%rdi) +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - int $7 +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - invlpg (%rax) +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - invlpga %rax, %ecx +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - lahf +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - leave +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - lodsb (%rsi), %al +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - lodsw (%rsi), %ax +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - lodsl (%rsi), %eax +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - lodsq (%rsi), %rax +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - movsb (%rsi), %es:(%rdi) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - movsw (%rsi), %es:(%rdi) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - movsl (%rsi), %es:(%rdi) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - movsq (%rsi), %es:(%rdi) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - movsbw %al, %di +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - movzbw %al, %di +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - movsbw (%rax), %di +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - movzbw (%rax), %di +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - movsbl %al, %edi +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - movzbl %al, %edi +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - movsbl (%rax), %edi +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - movzbl (%rax), %edi +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - movsbq %al, %rdi +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - movzbq %al, %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - movsbq (%rax), %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - movzbq (%rax), %rdi +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - movswl %ax, %edi +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - movzwl %ax, %edi +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - movswl (%rax), %edi +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - movzwl (%rax), %edi +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - movswq %ax, %rdi +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - movzwq %ax, %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - movswq (%rax), %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - movzwq (%rax), %rdi +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - movslq %eax, %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - movslq (%rax), %rdi +# CHECK-NEXT: - - - - - - - - - - - - - 3.00 1.00 - - - - - - - - mulb %dil +# CHECK-NEXT: - 1.00 - - - - - - - - - - - 3.00 1.00 - - 0.50 0.50 0.50 0.50 - - mulb (%rax) +# CHECK-NEXT: - - - - - - - - - - - - - 3.00 1.00 - - - - - - - - mulw %si +# CHECK-NEXT: - 1.00 - - - - - - - - - - - 3.00 1.00 - - 0.50 0.50 0.50 0.50 - - mulw (%rax) +# CHECK-NEXT: - - - - - - - - - - - - - 3.00 1.00 - - - - - - - - mull %edx +# CHECK-NEXT: - 1.00 - - - - - - - - - - - 3.00 1.00 - - 0.50 0.50 0.50 0.50 - - mull (%rax) +# CHECK-NEXT: - - - - - - - - - - - - - 4.00 1.00 - - - - - - - - mulq %rcx +# CHECK-NEXT: - 1.00 - - - - - - - - - - - 4.00 1.00 - - 0.50 0.50 0.50 0.50 - - mulq (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - negb %dil +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 negb (%r8) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - negw %si +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 negw (%r9) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - negl %edx +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 negl (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - negq %rcx +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 negq (%r10) +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - 0.33 0.33 0.33 - - - - - - nop +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - 0.33 0.33 0.33 - - - - - - nopw %di +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - 0.33 0.33 0.33 - - - - - - nopw (%rcx) +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - 0.33 0.33 0.33 - - - - - - nopl %esi +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - 0.33 0.33 0.33 - - - - - - nopl (%r8) +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - 0.33 0.33 0.33 - - - - - - nopq %rdx +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - 0.33 0.33 0.33 - - - - - - nopq (%r9) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - notb %dil +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 notb (%r8) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - notw %si +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 notw (%r9) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - notl %edx +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 notl (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - notq %rcx +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 notq (%r10) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - orb $7, %al +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - orb $7, %dil +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 orb $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - orb %sil, %dil +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 orb %sil, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - orb (%rax), %dil +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - orw $511, %ax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - orw $511, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 orw $511, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - orw $7, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 orw $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - orw %si, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 orw %si, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - orw (%rax), %di +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - orl $665536, %eax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - orl $665536, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 orl $665536, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - orl $7, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 orl $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - orl %esi, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 orl %esi, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - orl (%rax), %edi +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - orq $665536, %rax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - orq $665536, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 orq $665536, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - orq $7, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 orq $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - orq %rsi, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 orq %rsi, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - orq (%rax), %rdi +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - outb %al, $7 +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - outb %al, %dx +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - outw %ax, $7 +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - outw %ax, %dx +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - outl %eax, $7 +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - outl %eax, %dx +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - outsb (%rsi), %dx +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - outsw (%rsi), %dx +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - outsl (%rsi), %dx +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - 0.33 0.33 0.33 - - - - - - pause +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rclb %dil +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rcrb %dil +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rclb (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rcrb (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rclb $7, %dil +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rcrb $7, %dil +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rclb $7, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rcrb $7, (%rax) +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - rclb %cl, %dil +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - rcrb %cl, %dil +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rclb %cl, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rcrb %cl, (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rclw %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rcrw %di +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rclw (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rcrw (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rclw $7, %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rcrw $7, %di +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rclw $7, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rcrw $7, (%rax) +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - rclw %cl, %di +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - rcrw %cl, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rclw %cl, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rcrw %cl, (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rcll %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rcrl %edi +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rcll (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rcrl (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rcll $7, %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rcrl $7, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rcll $7, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rcrl $7, (%rax) +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - rcll %cl, %edi +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - rcrl %cl, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rcll %cl, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rcrl %cl, (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rclq %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rcrq %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rclq (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rcrq (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rclq $7, %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rcrq $7, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rclq $7, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rcrq $7, (%rax) +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - rclq %cl, %rdi +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - rcrq %cl, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rclq %cl, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rcrq %cl, (%rax) +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rdmsr +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rdpmc +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rdtsc +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rdtscp +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rolb %dil +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rorb %dil +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rolb (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rorb (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rolb $7, %dil +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rorb $7, %dil +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rolb $7, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rorb $7, (%rax) +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - rolb %cl, %dil +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - rorb %cl, %dil +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rolb %cl, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rorb %cl, (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rolw %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rorw %di +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rolw (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rorw (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rolw $7, %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rorw $7, %di +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rolw $7, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rorw $7, (%rax) +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - rolw %cl, %di +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - rorw %cl, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rolw %cl, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rorw %cl, (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - roll %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rorl %edi +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 roll (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rorl (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - roll $7, %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rorl $7, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 roll $7, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rorl $7, (%rax) +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - roll %cl, %edi +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - rorl %cl, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 roll %cl, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rorl %cl, (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rolq %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rorq %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rolq (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rorq (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rolq $7, %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - rorq $7, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rolq $7, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rorq $7, (%rax) +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - rolq %cl, %rdi +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - rorq %cl, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rolq %cl, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 rorq %cl, (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sahf +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sarb %dil +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - shlb %dil +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - shrb %dil +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sarb (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 shlb (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 shrb (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sarb $7, %dil +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - shlb $7, %dil +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - shrb $7, %dil +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sarb $7, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 shlb $7, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 shrb $7, (%rax) +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - sarb %cl, %dil +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - shlb %cl, %dil +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - shrb %cl, %dil +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sarb %cl, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 shlb %cl, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 shrb %cl, (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sarw %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - shlw %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - shrw %di +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sarw (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 shlw (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 shrw (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sarw $7, %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - shlw $7, %di +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - shrw $7, %di +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sarw $7, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 shlw $7, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 shrw $7, (%rax) +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - sarw %cl, %di +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - shlw %cl, %di +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - shrw %cl, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sarw %cl, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 shlw %cl, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 shrw %cl, (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sarl %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - shll %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - shrl %edi +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sarl (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 shll (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 shrl (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sarl $7, %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - shll $7, %edi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - shrl $7, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sarl $7, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 shll $7, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 shrl $7, (%rax) +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - sarl %cl, %edi +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - shll %cl, %edi +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - shrl %cl, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sarl %cl, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 shll %cl, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 shrl %cl, (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sarq %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - shlq %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - shrq %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sarq (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 shlq (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 shrq (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sarq $7, %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - shlq $7, %rdi +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - shrq $7, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sarq $7, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 shlq $7, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 2.00 2.00 2.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 shrq $7, (%rax) +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - sarq %cl, %rdi +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - shlq %cl, %rdi +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - shrq %cl, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sarq %cl, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 shlq %cl, (%rax) +# CHECK-NEXT: - 0.67 0.67 0.67 1.33 1.33 1.33 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 shrq %cl, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sbbb $0, %al +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sbbb $0, %dil +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sbbb $0, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sbbb $7, %al +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sbbb $7, %dil +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sbbb $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sbbb %sil, %dil +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sbbb %sil, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - sbbb (%rax), %dil +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sbbw $0, %ax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sbbw $0, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sbbw $0, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sbbw $511, %ax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sbbw $511, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sbbw $511, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sbbw $7, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sbbw $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sbbw %si, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sbbw %si, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - sbbw (%rax), %di +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sbbl $0, %eax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sbbl $0, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sbbl $0, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sbbl $665536, %eax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sbbl $665536, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sbbl $665536, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sbbl $7, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sbbl $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sbbl %esi, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sbbl %esi, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - sbbl (%rax), %edi +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sbbq $0, %rax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sbbq $0, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sbbq $0, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sbbq $665536, %rax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sbbq $665536, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sbbq $665536, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sbbq $7, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sbbq $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sbbq %rsi, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 sbbq %rsi, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - sbbq (%rax), %rdi +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - scasb %es:(%rdi), %al +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - scasw %es:(%rdi), %ax +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - scasl %es:(%rdi), %eax +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - scasq %es:(%rdi), %rax +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - seto %al +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 seto (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - setno %al +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 setno (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - setb %al +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 setb (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - setae %al +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 setae (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sete %al +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 sete (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - setne %al +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 setne (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - seta %al +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 seta (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - setbe %al +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 setbe (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - sets %al +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 sets (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - setns %al +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 setns (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - setp %al +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 setp (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - setnp %al +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 setnp (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - setl %al +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 setl (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - setge %al +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 setge (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - setg %al +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 setg (%rax) +# CHECK-NEXT: - - - - 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 - - - - - - setle %al +# CHECK-NEXT: - 0.33 0.33 0.33 2.00 2.00 2.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 setle (%rax) +# CHECK-NEXT: - - - - 3.00 3.00 3.00 - - - - - - - 0.33 0.33 0.33 - - - - - - shldw %cl, %si, %di +# CHECK-NEXT: - - - - 3.00 3.00 3.00 - - - - - - - 0.33 0.33 0.33 - - - - - - shrdw %cl, %si, %di +# CHECK-NEXT: - 0.33 0.33 0.33 4.00 4.00 4.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - shldw %cl, %si, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 4.00 4.00 4.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - shrdw %cl, %si, (%rax) +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - shldw $7, %si, %di +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - shrdw $7, %si, %di +# CHECK-NEXT: - 0.33 0.33 0.33 4.33 4.33 4.33 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - shldw $7, %si, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 4.33 4.33 4.33 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - shrdw $7, %si, (%rax) +# CHECK-NEXT: - - - - 3.00 3.00 3.00 - - - - - - - 0.33 0.33 0.33 - - - - - - shldl %cl, %esi, %edi +# CHECK-NEXT: - - - - 3.00 3.00 3.00 - - - - - - - 0.33 0.33 0.33 - - - - - - shrdl %cl, %esi, %edi +# CHECK-NEXT: - 0.33 0.33 0.33 4.00 4.00 4.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - shldl %cl, %esi, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 4.00 4.00 4.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - shrdl %cl, %esi, (%rax) +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - shldl $7, %esi, %edi +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - shrdl $7, %esi, %edi +# CHECK-NEXT: - 0.33 0.33 0.33 4.33 4.33 4.33 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - shldl $7, %esi, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 4.33 4.33 4.33 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - shrdl $7, %esi, (%rax) +# CHECK-NEXT: - - - - 3.00 3.00 3.00 - - - - - - - 0.33 0.33 0.33 - - - - - - shldq %cl, %rsi, %rdi +# CHECK-NEXT: - - - - 3.00 3.00 3.00 - - - - - - - 0.33 0.33 0.33 - - - - - - shrdq %cl, %rsi, %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 4.00 4.00 4.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - shldq %cl, %rsi, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 4.00 4.00 4.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - shrdq %cl, %rsi, (%rax) +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - shldq $7, %rsi, %rdi +# CHECK-NEXT: - - - - 2.67 2.67 2.67 - - - - - - - 0.33 0.33 0.33 - - - - - - shrdq $7, %rsi, %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 4.33 4.33 4.33 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - shldq $7, %rsi, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 4.33 4.33 4.33 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - shrdq $7, %rsi, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - stc +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - std +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - stosb %al, %es:(%rdi) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - stosw %ax, %es:(%rdi) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - stosl %eax, %es:(%rdi) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - stosq %rax, %es:(%rdi) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - subb $7, %al +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - subb $7, %dil +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 subb $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - subb %sil, %dil +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 subb %sil, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - subb (%rax), %dil +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - subw $511, %ax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - subw $511, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 subw $511, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - subw $7, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 subw $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - subw %si, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 subw %si, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - subw (%rax), %di +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - subl $665536, %eax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - subl $665536, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 subl $665536, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - subl $7, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 subl $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - subl %esi, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 subl %esi, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - subl (%rax), %edi +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - subq $665536, %rax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - subq $665536, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 subq $665536, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - subq $7, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 subq $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - subq %rsi, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 subq %rsi, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - subq (%rax), %rdi +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - testb $7, %al +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - testb $7, %dil +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - testb $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - testb %sil, %dil +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - testb %sil, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - testw $511, %ax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - testw $511, %di +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - testw $511, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - testw $7, %di +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - testw $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - testw %si, %di +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - testw %si, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - testl $665536, %eax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - testl $665536, %edi +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - testl $665536, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - testl $7, %edi +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - testl $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - testl %esi, %edi +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - testl %esi, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - testq $665536, %rax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - testq $665536, %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - testq $665536, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - testq $7, %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - testq $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - testq %rsi, %rdi +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - testq %rsi, (%rax) +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - ud2 +# CHECK-NEXT: - - - - 42.00 42.00 42.00 - - - - - - - 0.33 0.33 0.33 - - - - - - wrmsr +# CHECK-NEXT: - - - - 1.67 1.67 1.67 - - - - - - - 0.33 0.33 0.33 - - - - - - xaddb %bl, %cl +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 xaddb %bl, (%rcx) +# CHECK-NEXT: - - - - 1.67 1.67 1.67 - - - - - - - 0.33 0.33 0.33 - - - - - - xaddw %bx, %cx +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 xaddw %ax, (%rbx) +# CHECK-NEXT: - - - - 1.67 1.67 1.67 - - - - - - - 0.33 0.33 0.33 - - - - - - xaddl %ebx, %ecx +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 xaddl %eax, (%rbx) +# CHECK-NEXT: - - - - 1.67 1.67 1.67 - - - - - - - 0.33 0.33 0.33 - - - - - - xaddq %rbx, %rcx +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 xaddq %rax, (%rbx) +# CHECK-NEXT: - - - - 1.67 1.67 1.67 - - - - - - - 0.33 0.33 0.33 - - - - - - xchgb %bl, %cl +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 xchgb %bl, (%rbx) +# CHECK-NEXT: - - - - 1.67 1.67 1.67 - - - - - - - 0.33 0.33 0.33 - - - - - - xchgw %bx, %ax +# CHECK-NEXT: - - - - 1.67 1.67 1.67 - - - - - - - 0.33 0.33 0.33 - - - - - - xchgw %bx, %cx +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 xchgw %ax, (%rbx) +# CHECK-NEXT: - - - - 1.67 1.67 1.67 - - - - - - - 0.33 0.33 0.33 - - - - - - xchgl %ebx, %eax +# CHECK-NEXT: - - - - 1.67 1.67 1.67 - - - - - - - 0.33 0.33 0.33 - - - - - - xchgl %ebx, %ecx +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 xchgl %eax, (%rbx) +# CHECK-NEXT: - - - - 1.67 1.67 1.67 - - - - - - - 0.33 0.33 0.33 - - - - - - xchgq %rbx, %rax +# CHECK-NEXT: - - - - 1.67 1.67 1.67 - - - - - - - 0.33 0.33 0.33 - - - - - - xchgq %rbx, %rcx +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 xchgq %rax, (%rbx) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - xlatb +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - xorb $7, %al +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - xorb $7, %dil +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 xorb $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - xorb %sil, %dil +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 xorb %sil, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - xorb (%rax), %dil +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - xorw $511, %ax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - xorw $511, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 xorw $511, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - xorw $7, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 xorw $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - xorw %si, %di +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 xorw %si, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - xorw (%rax), %di +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - xorl $665536, %eax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - xorl $665536, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 xorl $665536, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - xorl $7, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 xorl $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - xorl %esi, %edi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 xorl %esi, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - xorl (%rax), %edi +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - xorq $665536, %rax +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - xorq $665536, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 xorq $665536, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - xorq $7, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 xorq $7, (%rax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - xorq %rsi, %rdi +# CHECK-NEXT: - 0.67 0.67 0.67 1.00 1.00 1.00 - - - - - - - 0.67 0.67 0.67 1.00 1.00 0.50 0.50 0.50 0.50 xorq %rsi, (%rax) +# CHECK-NEXT: - 0.33 0.33 0.33 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - xorq (%rax), %rdi diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-x87.s b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-x87.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-x87.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-x87.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -instruction-tables < %s | FileCheck %s f2xm1 @@ -206,316 +206,331 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 100 0.33 U f2xm1 -# CHECK-NEXT: 1 1 1.00 U fabs -# CHECK-NEXT: 1 3 1.00 U fadd %st, %st(1) -# CHECK-NEXT: 1 3 1.00 U fadd %st(2), %st -# CHECK-NEXT: 2 10 1.00 * U fadds (%ecx) -# CHECK-NEXT: 2 10 1.00 * U faddl (%ecx) -# CHECK-NEXT: 1 3 1.00 U faddp %st, %st(1) -# CHECK-NEXT: 1 3 1.00 U faddp %st, %st(2) -# CHECK-NEXT: 3 13 2.00 * U fiadds (%ecx) -# CHECK-NEXT: 3 13 2.00 * U fiaddl (%ecx) -# CHECK-NEXT: 1 100 0.33 U fbld (%ecx) -# CHECK-NEXT: 1 100 0.33 U fbstp (%eax) -# CHECK-NEXT: 1 1 1.00 U fchs -# CHECK-NEXT: 1 100 0.33 U fnclex -# CHECK-NEXT: 3 3 2.00 U fcmovb %st(1), %st -# CHECK-NEXT: 3 3 2.00 U fcmovbe %st(1), %st -# CHECK-NEXT: 3 3 2.00 U fcmove %st(1), %st -# CHECK-NEXT: 3 3 2.00 U fcmovnb %st(1), %st -# CHECK-NEXT: 3 3 2.00 U fcmovnbe %st(1), %st -# CHECK-NEXT: 3 3 2.00 U fcmovne %st(1), %st -# CHECK-NEXT: 3 3 2.00 U fcmovnu %st(1), %st -# CHECK-NEXT: 3 3 2.00 U fcmovu %st(1), %st -# CHECK-NEXT: 1 1 1.00 U fcom %st(1) -# CHECK-NEXT: 1 1 1.00 U fcom %st(3) -# CHECK-NEXT: 2 8 1.00 U fcoms (%ecx) -# CHECK-NEXT: 2 8 1.00 U fcoml (%eax) -# CHECK-NEXT: 1 1 1.00 U fcomp %st(1) -# CHECK-NEXT: 1 1 1.00 U fcomp %st(3) -# CHECK-NEXT: 2 8 1.00 U fcomps (%ecx) -# CHECK-NEXT: 2 8 1.00 U fcompl (%eax) -# CHECK-NEXT: 1 100 0.33 U fcompp -# CHECK-NEXT: 3 3 1.00 U fcomi %st(3), %st -# CHECK-NEXT: 3 3 1.00 U fcompi %st(3), %st -# CHECK-NEXT: 1 100 0.33 U fcos -# CHECK-NEXT: 1 1 1.00 U fdecstp -# CHECK-NEXT: 1 14 14.00 U fdiv %st, %st(1) -# CHECK-NEXT: 1 14 14.00 U fdiv %st(2), %st -# CHECK-NEXT: 2 31 1.00 * U fdivs (%ecx) -# CHECK-NEXT: 2 31 1.00 * U fdivl (%eax) -# CHECK-NEXT: 1 14 14.00 U fdivp %st, %st(1) -# CHECK-NEXT: 1 14 14.00 U fdivp %st, %st(2) -# CHECK-NEXT: 3 34 1.00 * U fidivs (%ecx) -# CHECK-NEXT: 3 34 1.00 * U fidivl (%eax) -# CHECK-NEXT: 1 14 14.00 U fdivr %st, %st(1) -# CHECK-NEXT: 1 14 14.00 U fdivr %st(2), %st -# CHECK-NEXT: 2 31 1.00 * U fdivrs (%ecx) -# CHECK-NEXT: 2 31 1.00 * U fdivrl (%eax) -# CHECK-NEXT: 1 14 14.00 U fdivrp %st, %st(1) -# CHECK-NEXT: 1 14 14.00 U fdivrp %st, %st(2) -# CHECK-NEXT: 3 34 1.00 * U fidivrs (%ecx) -# CHECK-NEXT: 3 34 1.00 * U fidivrl (%eax) -# CHECK-NEXT: 1 1 1.00 U ffree %st(0) -# CHECK-NEXT: 3 11 2.00 U ficoms (%ecx) -# CHECK-NEXT: 3 11 2.00 U ficoml (%eax) -# CHECK-NEXT: 3 11 2.00 U ficomps (%ecx) -# CHECK-NEXT: 3 11 2.00 U ficompl (%eax) -# CHECK-NEXT: 2 10 1.00 * U filds (%edx) -# CHECK-NEXT: 2 10 1.00 * U fildl (%ecx) -# CHECK-NEXT: 2 10 1.00 * U fildll (%eax) -# CHECK-NEXT: 1 1 1.00 U fincstp -# CHECK-NEXT: 4 5 1.33 U fninit -# CHECK-NEXT: 4 9 1.00 * U fists (%edx) -# CHECK-NEXT: 4 9 1.00 * U fistl (%ecx) -# CHECK-NEXT: 4 9 1.00 * U fistps (%edx) -# CHECK-NEXT: 4 9 1.00 * U fistpl (%ecx) -# CHECK-NEXT: 4 9 1.00 * U fistpll (%eax) -# CHECK-NEXT: 3 5 1.00 * U fisttps (%edx) -# CHECK-NEXT: 3 5 1.00 * U fisttpl (%ecx) -# CHECK-NEXT: 3 5 1.00 * U fisttpll (%eax) -# CHECK-NEXT: 1 1 1.00 U fld %st(0) -# CHECK-NEXT: 3 9 1.00 * U flds (%edx) -# CHECK-NEXT: 3 9 1.00 * U fldl (%ecx) -# CHECK-NEXT: 3 9 1.00 * U fldt (%eax) -# CHECK-NEXT: 5 8 2.00 * U fldcw (%eax) -# CHECK-NEXT: 1 100 0.33 U fldenv (%eax) -# CHECK-NEXT: 2 1 1.00 U fld1 -# CHECK-NEXT: 2 1 1.00 U fldl2e -# CHECK-NEXT: 2 1 1.00 U fldl2t -# CHECK-NEXT: 2 1 1.00 U fldlg2 -# CHECK-NEXT: 2 1 1.00 U fldln2 -# CHECK-NEXT: 2 1 1.00 U fldpi -# CHECK-NEXT: 1 1 1.00 U fldz -# CHECK-NEXT: 1 5 1.00 U fmul %st, %st(1) -# CHECK-NEXT: 1 5 1.00 U fmul %st(2), %st -# CHECK-NEXT: 2 12 1.00 * U fmuls (%ecx) -# CHECK-NEXT: 2 12 1.00 * U fmull (%eax) -# CHECK-NEXT: 1 5 1.00 U fmulp %st, %st(1) -# CHECK-NEXT: 1 5 1.00 U fmulp %st, %st(2) -# CHECK-NEXT: 3 15 1.00 * U fimuls (%ecx) -# CHECK-NEXT: 3 15 1.00 * U fimull (%eax) -# CHECK-NEXT: 1 1 1.00 U fnop -# CHECK-NEXT: 1 100 0.33 U fpatan -# CHECK-NEXT: 1 100 0.33 U fprem -# CHECK-NEXT: 1 100 0.33 U fprem1 -# CHECK-NEXT: 1 100 0.33 U fptan -# CHECK-NEXT: 1 100 0.33 U frndint -# CHECK-NEXT: 1 100 0.33 U frstor (%eax) -# CHECK-NEXT: 1 100 0.33 U fnsave (%eax) -# CHECK-NEXT: 1 100 0.33 U fscale -# CHECK-NEXT: 1 100 0.33 U fsin -# CHECK-NEXT: 1 100 0.33 U fsincos -# CHECK-NEXT: 1 24 24.00 U fsqrt -# CHECK-NEXT: 1 1 1.00 U fst %st(0) -# CHECK-NEXT: 3 6 1.00 * U fsts (%edx) -# CHECK-NEXT: 3 6 1.00 * U fstl (%ecx) -# CHECK-NEXT: 1 1 1.00 U fstp %st(0) -# CHECK-NEXT: 3 6 1.00 * U fstpl (%edx) -# CHECK-NEXT: 3 6 1.00 * U fstpl (%ecx) -# CHECK-NEXT: 3 6 1.00 * U fstpt (%eax) -# CHECK-NEXT: 4 7 1.00 * U fnstcw (%eax) -# CHECK-NEXT: 1 100 0.33 U fnstenv (%eax) -# CHECK-NEXT: 4 7 1.00 U fnstsw (%eax) -# CHECK-NEXT: 1 100 0.33 U frstor (%eax) -# CHECK-NEXT: 1 100 0.33 U wait -# CHECK-NEXT: 1 100 0.33 U fnsave (%eax) -# CHECK-NEXT: 1 3 1.00 U fsub %st, %st(1) -# CHECK-NEXT: 1 3 1.00 U fsub %st(2), %st -# CHECK-NEXT: 2 10 1.00 * U fsubs (%ecx) -# CHECK-NEXT: 2 10 1.00 * U fsubl (%eax) -# CHECK-NEXT: 1 3 1.00 U fsubp %st, %st(1) -# CHECK-NEXT: 1 3 1.00 U fsubp %st, %st(2) -# CHECK-NEXT: 3 13 2.00 * U fisubs (%ecx) -# CHECK-NEXT: 3 13 2.00 * U fisubl (%eax) -# CHECK-NEXT: 1 3 1.00 U fsubr %st, %st(1) -# CHECK-NEXT: 1 3 1.00 U fsubr %st(2), %st -# CHECK-NEXT: 2 10 1.00 * U fsubrs (%ecx) -# CHECK-NEXT: 2 10 1.00 * U fsubrl (%eax) -# CHECK-NEXT: 1 3 1.00 U fsubrp %st, %st(1) -# CHECK-NEXT: 1 3 1.00 U fsubrp %st, %st(2) -# CHECK-NEXT: 3 13 2.00 * U fisubrs (%ecx) -# CHECK-NEXT: 3 13 2.00 * U fisubrl (%eax) -# CHECK-NEXT: 1 3 1.00 U ftst -# CHECK-NEXT: 1 1 1.00 U fucom %st(1) -# CHECK-NEXT: 1 1 1.00 U fucom %st(3) -# CHECK-NEXT: 1 1 1.00 U fucomp %st(1) -# CHECK-NEXT: 1 1 1.00 U fucomp %st(3) -# CHECK-NEXT: 1 3 1.00 U fucompp -# CHECK-NEXT: 3 3 1.00 U fucomi %st(3), %st -# CHECK-NEXT: 3 3 1.00 U fucompi %st(3), %st -# CHECK-NEXT: 1 100 0.33 U wait -# CHECK-NEXT: 1 100 0.33 U fxam -# CHECK-NEXT: 1 1 0.33 U fxch %st(1) -# CHECK-NEXT: 1 1 0.33 U fxch %st(3) -# CHECK-NEXT: 5 5 2.00 * * U fxrstor (%eax) -# CHECK-NEXT: 1 100 0.33 * * U fxsave (%eax) -# CHECK-NEXT: 1 100 0.33 U fxtract -# CHECK-NEXT: 1 100 0.33 U fyl2x -# CHECK-NEXT: 1 100 0.33 U fyl2xp1 +# CHECK-NEXT: 13 100 9.00 U f2xm1 +# CHECK-NEXT: 1 2 2.00 U fabs +# CHECK-NEXT: 1 4 2.00 U fadd %st, %st(1) +# CHECK-NEXT: 1 4 2.00 U fadd %st(2), %st +# CHECK-NEXT: 1 6 2.50 * U fadds (%ecx) +# CHECK-NEXT: 1 6 2.50 * U faddl (%ecx) +# CHECK-NEXT: 1 4 2.00 U faddp %st, %st(1) +# CHECK-NEXT: 1 4 2.00 U faddp %st, %st(2) +# CHECK-NEXT: 1 6 2.50 * U fiadds (%ecx) +# CHECK-NEXT: 1 6 2.50 * U fiaddl (%ecx) +# CHECK-NEXT: 13 100 9.00 U fbld (%ecx) +# CHECK-NEXT: 13 100 9.00 U fbstp (%eax) +# CHECK-NEXT: 1 2 2.00 U fchs +# CHECK-NEXT: 13 100 9.00 U fnclex +# CHECK-NEXT: 9 15 14.00 U fcmovb %st(1), %st +# CHECK-NEXT: 9 15 14.00 U fcmovbe %st(1), %st +# CHECK-NEXT: 9 15 14.00 U fcmove %st(1), %st +# CHECK-NEXT: 9 15 14.00 U fcmovnb %st(1), %st +# CHECK-NEXT: 9 15 14.00 U fcmovnbe %st(1), %st +# CHECK-NEXT: 9 15 14.00 U fcmovne %st(1), %st +# CHECK-NEXT: 9 15 14.00 U fcmovnu %st(1), %st +# CHECK-NEXT: 9 15 14.00 U fcmovu %st(1), %st +# CHECK-NEXT: 1 1 2.50 U fcom %st(1) +# CHECK-NEXT: 1 1 2.50 U fcom %st(3) +# CHECK-NEXT: 1 3 3.00 U fcoms (%ecx) +# CHECK-NEXT: 1 3 3.00 U fcoml (%eax) +# CHECK-NEXT: 1 1 2.50 U fcomp %st(1) +# CHECK-NEXT: 1 1 2.50 U fcomp %st(3) +# CHECK-NEXT: 1 3 3.00 U fcomps (%ecx) +# CHECK-NEXT: 1 3 3.00 U fcompl (%eax) +# CHECK-NEXT: 13 100 9.00 U fcompp +# CHECK-NEXT: 1 1 2.50 U fcomi %st(3), %st +# CHECK-NEXT: 1 1 2.50 U fcompi %st(3), %st +# CHECK-NEXT: 13 100 9.00 U fcos +# CHECK-NEXT: 13 100 9.00 U fdecstp +# CHECK-NEXT: 1 16 13.00 U fdiv %st, %st(1) +# CHECK-NEXT: 1 16 13.00 U fdiv %st(2), %st +# CHECK-NEXT: 1 18 14.00 * U fdivs (%ecx) +# CHECK-NEXT: 1 18 14.00 * U fdivl (%eax) +# CHECK-NEXT: 1 16 13.00 U fdivp %st, %st(1) +# CHECK-NEXT: 1 16 13.00 U fdivp %st, %st(2) +# CHECK-NEXT: 1 18 14.00 * U fidivs (%ecx) +# CHECK-NEXT: 1 18 14.00 * U fidivl (%eax) +# CHECK-NEXT: 1 16 13.00 U fdivr %st, %st(1) +# CHECK-NEXT: 1 16 13.00 U fdivr %st(2), %st +# CHECK-NEXT: 1 18 14.00 * U fdivrs (%ecx) +# CHECK-NEXT: 1 18 14.00 * U fdivrl (%eax) +# CHECK-NEXT: 1 16 13.00 U fdivrp %st, %st(1) +# CHECK-NEXT: 1 16 13.00 U fdivrp %st, %st(2) +# CHECK-NEXT: 1 18 14.00 * U fidivrs (%ecx) +# CHECK-NEXT: 1 18 14.00 * U fidivrl (%eax) +# CHECK-NEXT: 13 100 9.00 U ffree %st(0) +# CHECK-NEXT: 1 3 3.00 U ficoms (%ecx) +# CHECK-NEXT: 1 3 3.00 U ficoml (%eax) +# CHECK-NEXT: 1 3 3.00 U ficomps (%ecx) +# CHECK-NEXT: 1 3 3.00 U ficompl (%eax) +# CHECK-NEXT: 1 4 0.50 * U filds (%edx) +# CHECK-NEXT: 1 4 0.50 * U fildl (%ecx) +# CHECK-NEXT: 1 4 0.50 * U fildll (%eax) +# CHECK-NEXT: 13 100 9.00 U fincstp +# CHECK-NEXT: 13 100 9.00 U fninit +# CHECK-NEXT: 1 3 0.50 * U fists (%edx) +# CHECK-NEXT: 1 3 0.50 * U fistl (%ecx) +# CHECK-NEXT: 1 3 0.50 * U fistps (%edx) +# CHECK-NEXT: 1 3 0.50 * U fistpl (%ecx) +# CHECK-NEXT: 1 3 0.50 * U fistpll (%eax) +# CHECK-NEXT: 1 3 0.50 * U fisttps (%edx) +# CHECK-NEXT: 1 3 0.50 * U fisttpl (%ecx) +# CHECK-NEXT: 1 3 0.50 * U fisttpll (%eax) +# CHECK-NEXT: 1 1 1.33 U fld %st(0) +# CHECK-NEXT: 1 4 0.50 * U flds (%edx) +# CHECK-NEXT: 1 4 0.50 * U fldl (%ecx) +# CHECK-NEXT: 1 4 0.50 * U fldt (%eax) +# CHECK-NEXT: 1 4 0.50 * U fldcw (%eax) +# CHECK-NEXT: 13 100 9.00 U fldenv (%eax) +# CHECK-NEXT: 1 4 1.00 U fld1 +# CHECK-NEXT: 1 12 1.00 U fldl2e +# CHECK-NEXT: 1 12 1.00 U fldl2t +# CHECK-NEXT: 1 12 1.00 U fldlg2 +# CHECK-NEXT: 1 12 1.00 U fldln2 +# CHECK-NEXT: 1 12 1.00 U fldpi +# CHECK-NEXT: 1 4 1.00 U fldz +# CHECK-NEXT: 1 4 2.50 U fmul %st, %st(1) +# CHECK-NEXT: 1 4 2.50 U fmul %st(2), %st +# CHECK-NEXT: 1 6 3.00 * U fmuls (%ecx) +# CHECK-NEXT: 1 6 3.00 * U fmull (%eax) +# CHECK-NEXT: 1 4 2.50 U fmulp %st, %st(1) +# CHECK-NEXT: 1 4 2.50 U fmulp %st, %st(2) +# CHECK-NEXT: 1 6 3.00 * U fimuls (%ecx) +# CHECK-NEXT: 1 6 3.00 * U fimull (%eax) +# CHECK-NEXT: 1 0 0.33 U fnop +# CHECK-NEXT: 13 100 9.00 U fpatan +# CHECK-NEXT: 13 100 9.00 U fprem +# CHECK-NEXT: 13 100 9.00 U fprem1 +# CHECK-NEXT: 13 100 9.00 U fptan +# CHECK-NEXT: 13 100 9.00 U frndint +# CHECK-NEXT: 13 100 9.00 U frstor (%eax) +# CHECK-NEXT: 13 100 9.00 U fnsave (%eax) +# CHECK-NEXT: 13 100 9.00 U fscale +# CHECK-NEXT: 13 100 9.00 U fsin +# CHECK-NEXT: 13 100 9.00 U fsincos +# CHECK-NEXT: 1 35 35.00 U fsqrt +# CHECK-NEXT: 1 1 1.33 U fst %st(0) +# CHECK-NEXT: 1 3 0.50 * U fsts (%edx) +# CHECK-NEXT: 1 3 0.50 * U fstl (%ecx) +# CHECK-NEXT: 1 1 1.33 U fstp %st(0) +# CHECK-NEXT: 1 3 0.50 * U fstpl (%edx) +# CHECK-NEXT: 1 3 0.50 * U fstpl (%ecx) +# CHECK-NEXT: 1 3 0.50 * U fstpt (%eax) +# CHECK-NEXT: 1 2 1.00 * U fnstcw (%eax) +# CHECK-NEXT: 13 100 9.00 U fnstenv (%eax) +# CHECK-NEXT: 13 100 9.00 U fnstsw (%eax) +# CHECK-NEXT: 13 100 9.00 U frstor (%eax) +# CHECK-NEXT: 13 100 9.00 U wait +# CHECK-NEXT: 13 100 9.00 U fnsave (%eax) +# CHECK-NEXT: 1 4 2.00 U fsub %st, %st(1) +# CHECK-NEXT: 1 4 2.00 U fsub %st(2), %st +# CHECK-NEXT: 1 6 2.50 * U fsubs (%ecx) +# CHECK-NEXT: 1 6 2.50 * U fsubl (%eax) +# CHECK-NEXT: 1 4 2.00 U fsubp %st, %st(1) +# CHECK-NEXT: 1 4 2.00 U fsubp %st, %st(2) +# CHECK-NEXT: 1 6 2.50 * U fisubs (%ecx) +# CHECK-NEXT: 1 6 2.50 * U fisubl (%eax) +# CHECK-NEXT: 1 4 2.00 U fsubr %st, %st(1) +# CHECK-NEXT: 1 4 2.00 U fsubr %st(2), %st +# CHECK-NEXT: 1 6 2.50 * U fsubrs (%ecx) +# CHECK-NEXT: 1 6 2.50 * U fsubrl (%eax) +# CHECK-NEXT: 1 4 2.00 U fsubrp %st, %st(1) +# CHECK-NEXT: 1 4 2.00 U fsubrp %st, %st(2) +# CHECK-NEXT: 1 6 2.50 * U fisubrs (%ecx) +# CHECK-NEXT: 1 6 2.50 * U fisubrl (%eax) +# CHECK-NEXT: 1 1 2.50 U ftst +# CHECK-NEXT: 1 1 2.50 U fucom %st(1) +# CHECK-NEXT: 1 1 2.50 U fucom %st(3) +# CHECK-NEXT: 1 1 2.50 U fucomp %st(1) +# CHECK-NEXT: 1 1 2.50 U fucomp %st(3) +# CHECK-NEXT: 1 1 2.50 U fucompp +# CHECK-NEXT: 1 1 2.50 U fucomi %st(3), %st +# CHECK-NEXT: 1 1 2.50 U fucompi %st(3), %st +# CHECK-NEXT: 13 100 9.00 U wait +# CHECK-NEXT: 13 100 9.00 U fxam +# CHECK-NEXT: 1 1 1.33 U fxch %st(1) +# CHECK-NEXT: 1 1 1.33 U fxch %st(3) +# CHECK-NEXT: 13 100 9.00 * * U fxrstor (%eax) +# CHECK-NEXT: 13 100 9.00 * * U fxsave (%eax) +# CHECK-NEXT: 13 100 9.00 U fxtract +# CHECK-NEXT: 13 100 9.00 U fyl2x +# CHECK-NEXT: 13 100 9.00 U fyl2xp1 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - 136.00 52.67 90.67 17.00 54.67 34.00 34.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - 6.67 6.67 6.67 305.00 305.00 305.00 135.00 119.00 390.00 27.00 46.00 15.00 - 20.00 20.00 20.00 26.00 26.00 19.50 19.50 6.50 6.50 # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - f2xm1 -# CHECK-NEXT: - - - - - 1.00 - - fabs -# CHECK-NEXT: - - - 1.00 - - - - fadd %st, %st(1) -# CHECK-NEXT: - - - 1.00 - - - - fadd %st(2), %st -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fadds (%ecx) -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 faddl (%ecx) -# CHECK-NEXT: - - - 1.00 - - - - faddp %st, %st(1) -# CHECK-NEXT: - - - 1.00 - - - - faddp %st, %st(2) -# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 fiadds (%ecx) -# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 fiaddl (%ecx) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fbld (%ecx) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fbstp (%eax) -# CHECK-NEXT: - - - - - 1.00 - - fchs -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fnclex -# CHECK-NEXT: - - 0.50 - - 2.50 - - fcmovb %st(1), %st -# CHECK-NEXT: - - 0.50 - - 2.50 - - fcmovbe %st(1), %st -# CHECK-NEXT: - - 0.50 - - 2.50 - - fcmove %st(1), %st -# CHECK-NEXT: - - 0.50 - - 2.50 - - fcmovnb %st(1), %st -# CHECK-NEXT: - - 0.50 - - 2.50 - - fcmovnbe %st(1), %st -# CHECK-NEXT: - - 0.50 - - 2.50 - - fcmovne %st(1), %st -# CHECK-NEXT: - - 0.50 - - 2.50 - - fcmovnu %st(1), %st -# CHECK-NEXT: - - 0.50 - - 2.50 - - fcmovu %st(1), %st -# CHECK-NEXT: - - - 1.00 - - - - fcom %st(1) -# CHECK-NEXT: - - - 1.00 - - - - fcom %st(3) -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fcoms (%ecx) -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fcoml (%eax) -# CHECK-NEXT: - - - 1.00 - - - - fcomp %st(1) -# CHECK-NEXT: - - - 1.00 - - - - fcomp %st(3) -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fcomps (%ecx) -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fcompl (%eax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fcompp -# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - fcomi %st(3), %st -# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - fcompi %st(3), %st -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fcos -# CHECK-NEXT: - - - - - 1.00 - - fdecstp -# CHECK-NEXT: - 14.00 1.00 - - - - - fdiv %st, %st(1) -# CHECK-NEXT: - 14.00 1.00 - - - - - fdiv %st(2), %st -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 fdivs (%ecx) -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 fdivl (%eax) -# CHECK-NEXT: - 14.00 1.00 - - - - - fdivp %st, %st(1) -# CHECK-NEXT: - 14.00 1.00 - - - - - fdivp %st, %st(2) -# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 fidivs (%ecx) -# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 fidivl (%eax) -# CHECK-NEXT: - 14.00 1.00 - - - - - fdivr %st, %st(1) -# CHECK-NEXT: - 14.00 1.00 - - - - - fdivr %st(2), %st -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 fdivrs (%ecx) -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 fdivrl (%eax) -# CHECK-NEXT: - 14.00 1.00 - - - - - fdivrp %st, %st(1) -# CHECK-NEXT: - 14.00 1.00 - - - - - fdivrp %st, %st(2) -# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 fidivrs (%ecx) -# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 fidivrl (%eax) -# CHECK-NEXT: - - - - - 1.00 - - ffree %st(0) -# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 ficoms (%ecx) -# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 ficoml (%eax) -# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 ficomps (%ecx) -# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 ficompl (%eax) -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 filds (%edx) -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fildl (%ecx) -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fildll (%eax) -# CHECK-NEXT: - - - - - 1.00 - - fincstp -# CHECK-NEXT: - - 1.00 1.00 - 2.00 - - fninit -# CHECK-NEXT: - - - 1.00 1.00 - 1.00 1.00 fists (%edx) -# CHECK-NEXT: - - - 1.00 1.00 - 1.00 1.00 fistl (%ecx) -# CHECK-NEXT: - - - 1.00 1.00 - 1.00 1.00 fistps (%edx) -# CHECK-NEXT: - - - 1.00 1.00 - 1.00 1.00 fistpl (%ecx) -# CHECK-NEXT: - - - 1.00 1.00 - 1.00 1.00 fistpll (%eax) -# CHECK-NEXT: - - - 1.00 1.00 - 0.50 0.50 fisttps (%edx) -# CHECK-NEXT: - - - 1.00 1.00 - 0.50 0.50 fisttpl (%ecx) -# CHECK-NEXT: - - - 1.00 1.00 - 0.50 0.50 fisttpll (%eax) -# CHECK-NEXT: - - - - - 1.00 - - fld %st(0) -# CHECK-NEXT: - - 0.50 0.50 - 1.00 0.50 0.50 flds (%edx) -# CHECK-NEXT: - - 0.50 0.50 - 1.00 0.50 0.50 fldl (%ecx) -# CHECK-NEXT: - - 0.50 0.50 - 1.00 0.50 0.50 fldt (%eax) -# CHECK-NEXT: - - - - 1.00 2.00 1.00 1.00 fldcw (%eax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fldenv (%eax) -# CHECK-NEXT: - - 1.00 - - 1.00 - - fld1 -# CHECK-NEXT: - - 1.00 1.00 - - - - fldl2e -# CHECK-NEXT: - - 1.00 1.00 - - - - fldl2t -# CHECK-NEXT: - - 1.00 1.00 - - - - fldlg2 -# CHECK-NEXT: - - 1.00 1.00 - - - - fldln2 -# CHECK-NEXT: - - 1.00 1.00 - - - - fldpi -# CHECK-NEXT: - - - - - 1.00 - - fldz -# CHECK-NEXT: - - 1.00 - - - - - fmul %st, %st(1) -# CHECK-NEXT: - - 1.00 - - - - - fmul %st(2), %st -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 fmuls (%ecx) -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 fmull (%eax) -# CHECK-NEXT: - - 1.00 - - - - - fmulp %st, %st(1) -# CHECK-NEXT: - - 1.00 - - - - - fmulp %st, %st(2) -# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 fimuls (%ecx) -# CHECK-NEXT: - - 1.00 1.00 - - 0.50 0.50 fimull (%eax) -# CHECK-NEXT: - - - - - 1.00 - - fnop -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fpatan -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fprem -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fprem1 -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fptan -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - frndint -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - frstor (%eax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fnsave (%eax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fscale -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fsin -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fsincos -# CHECK-NEXT: - 24.00 1.00 - - - - - fsqrt -# CHECK-NEXT: - - - - - 1.00 - - fst %st(0) -# CHECK-NEXT: - - - - 1.00 - 1.00 1.00 fsts (%edx) -# CHECK-NEXT: - - - - 1.00 - 1.00 1.00 fstl (%ecx) -# CHECK-NEXT: - - - - - 1.00 - - fstp %st(0) -# CHECK-NEXT: - - - - 1.00 - 1.00 1.00 fstpl (%edx) -# CHECK-NEXT: - - - - 1.00 - 1.00 1.00 fstpl (%ecx) -# CHECK-NEXT: - - - - 1.00 - 1.00 1.00 fstpt (%eax) -# CHECK-NEXT: - - - - 1.00 1.00 1.00 1.00 fnstcw (%eax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fnstenv (%eax) -# CHECK-NEXT: - - 1.00 - 1.00 - 1.00 1.00 fnstsw (%eax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - frstor (%eax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - wait -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fnsave (%eax) -# CHECK-NEXT: - - - 1.00 - - - - fsub %st, %st(1) -# CHECK-NEXT: - - - 1.00 - - - - fsub %st(2), %st -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fsubs (%ecx) -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fsubl (%eax) -# CHECK-NEXT: - - - 1.00 - - - - fsubp %st, %st(1) -# CHECK-NEXT: - - - 1.00 - - - - fsubp %st, %st(2) -# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 fisubs (%ecx) -# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 fisubl (%eax) -# CHECK-NEXT: - - - 1.00 - - - - fsubr %st, %st(1) -# CHECK-NEXT: - - - 1.00 - - - - fsubr %st(2), %st -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fsubrs (%ecx) -# CHECK-NEXT: - - - 1.00 - - 0.50 0.50 fsubrl (%eax) -# CHECK-NEXT: - - - 1.00 - - - - fsubrp %st, %st(1) -# CHECK-NEXT: - - - 1.00 - - - - fsubrp %st, %st(2) -# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 fisubrs (%ecx) -# CHECK-NEXT: - - - 2.00 - - 0.50 0.50 fisubrl (%eax) -# CHECK-NEXT: - - - 1.00 - - - - ftst -# CHECK-NEXT: - - - 1.00 - - - - fucom %st(1) -# CHECK-NEXT: - - - 1.00 - - - - fucom %st(3) -# CHECK-NEXT: - - - 1.00 - - - - fucomp %st(1) -# CHECK-NEXT: - - - 1.00 - - - - fucomp %st(3) -# CHECK-NEXT: - - - 1.00 - - - - fucompp -# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - fucomi %st(3), %st -# CHECK-NEXT: - - 1.00 1.00 - 1.00 - - fucompi %st(3), %st -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - wait -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fxam -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fxch %st(1) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fxch %st(3) -# CHECK-NEXT: - - 0.50 0.50 1.00 2.00 0.50 0.50 fxrstor (%eax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fxsave (%eax) -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fxtract -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fyl2x -# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - fyl2xp1 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - f2xm1 +# CHECK-NEXT: - - - - - - - - - 2.00 - 1.00 - - - - - - - - - - - fabs +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - fadd %st, %st(1) +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - fadd %st(2), %st +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - fadds (%ecx) +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - faddl (%ecx) +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - faddp %st, %st(1) +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - faddp %st, %st(2) +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - fiadds (%ecx) +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - fiaddl (%ecx) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fbld (%ecx) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fbstp (%eax) +# CHECK-NEXT: - - - - - - - - - 2.00 - 1.00 - - - - - - - - - - - fchs +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fnclex +# CHECK-NEXT: - - - - - - - - 14.00 - - - 1.00 - - - - - - - - - - fcmovb %st(1), %st +# CHECK-NEXT: - - - - - - - - 14.00 - - - 1.00 - - - - - - - - - - fcmovbe %st(1), %st +# CHECK-NEXT: - - - - - - - - 14.00 - - - 1.00 - - - - - - - - - - fcmove %st(1), %st +# CHECK-NEXT: - - - - - - - - 14.00 - - - 1.00 - - - - - - - - - - fcmovnb %st(1), %st +# CHECK-NEXT: - - - - - - - - 14.00 - - - 1.00 - - - - - - - - - - fcmovnbe %st(1), %st +# CHECK-NEXT: - - - - - - - - 14.00 - - - 1.00 - - - - - - - - - - fcmovne %st(1), %st +# CHECK-NEXT: - - - - - - - - 14.00 - - - 1.00 - - - - - - - - - - fcmovnu %st(1), %st +# CHECK-NEXT: - - - - - - - - 14.00 - - - 1.00 - - - - - - - - - - fcmovu %st(1), %st +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - fcom %st(1) +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - fcom %st(3) +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - fcoms (%ecx) +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - fcoml (%eax) +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - fcomp %st(1) +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - fcomp %st(3) +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - fcomps (%ecx) +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - fcompl (%eax) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fcompp +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - fcomi %st(3), %st +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - fcompi %st(3), %st +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fcos +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fdecstp +# CHECK-NEXT: - - - - - - - - - 13.00 - 1.00 - - - - - - - - - - - fdiv %st, %st(1) +# CHECK-NEXT: - - - - - - - - - 13.00 - 1.00 - - - - - - - - - - - fdiv %st(2), %st +# CHECK-NEXT: - - - - - - - - - 14.00 - 1.00 - - - - - 0.50 0.50 0.50 0.50 - - fdivs (%ecx) +# CHECK-NEXT: - - - - - - - - - 14.00 - 1.00 - - - - - 0.50 0.50 0.50 0.50 - - fdivl (%eax) +# CHECK-NEXT: - - - - - - - - - 13.00 - 1.00 - - - - - - - - - - - fdivp %st, %st(1) +# CHECK-NEXT: - - - - - - - - - 13.00 - 1.00 - - - - - - - - - - - fdivp %st, %st(2) +# CHECK-NEXT: - - - - - - - - - 14.00 - 1.00 - - - - - 0.50 0.50 0.50 0.50 - - fidivs (%ecx) +# CHECK-NEXT: - - - - - - - - - 14.00 - 1.00 - - - - - 0.50 0.50 0.50 0.50 - - fidivl (%eax) +# CHECK-NEXT: - - - - - - - - - 13.00 - 1.00 - - - - - - - - - - - fdivr %st, %st(1) +# CHECK-NEXT: - - - - - - - - - 13.00 - 1.00 - - - - - - - - - - - fdivr %st(2), %st +# CHECK-NEXT: - - - - - - - - - 14.00 - 1.00 - - - - - 0.50 0.50 0.50 0.50 - - fdivrs (%ecx) +# CHECK-NEXT: - - - - - - - - - 14.00 - 1.00 - - - - - 0.50 0.50 0.50 0.50 - - fdivrl (%eax) +# CHECK-NEXT: - - - - - - - - - 13.00 - 1.00 - - - - - - - - - - - fdivrp %st, %st(1) +# CHECK-NEXT: - - - - - - - - - 13.00 - 1.00 - - - - - - - - - - - fdivrp %st, %st(2) +# CHECK-NEXT: - - - - - - - - - 14.00 - 1.00 - - - - - 0.50 0.50 0.50 0.50 - - fidivrs (%ecx) +# CHECK-NEXT: - - - - - - - - - 14.00 - 1.00 - - - - - 0.50 0.50 0.50 0.50 - - fidivrl (%eax) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - ffree %st(0) +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - ficoms (%ecx) +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - ficoml (%eax) +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - ficomps (%ecx) +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - ficompl (%eax) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - filds (%edx) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - fildl (%ecx) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - fildll (%eax) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fincstp +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fninit +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 fists (%edx) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 fistl (%ecx) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 fistps (%edx) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 fistpl (%ecx) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 fistpll (%eax) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 fisttps (%edx) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 fisttpl (%ecx) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 fisttpll (%eax) +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - fld %st(0) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - flds (%edx) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - fldl (%ecx) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - fldt (%eax) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50 - - fldcw (%eax) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fldenv (%eax) +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - - - - - - - fld1 +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - - - - - - - fldl2e +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - - - - - - - fldl2t +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - - - - - - - fldlg2 +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - - - - - - - fldln2 +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - - - - - - - fldpi +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - - - - - - - fldz +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - fmul %st, %st(1) +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - fmul %st(2), %st +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - fmuls (%ecx) +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - fmull (%eax) +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - fmulp %st, %st(1) +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - fmulp %st, %st(2) +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - fimuls (%ecx) +# CHECK-NEXT: - - - - - - - 3.00 - 3.00 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - fimull (%eax) +# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - 0.33 0.33 0.33 - - - - - - fnop +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fpatan +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fprem +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fprem1 +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fptan +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - frndint +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - frstor (%eax) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fnsave (%eax) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fscale +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fsin +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fsincos +# CHECK-NEXT: - - - - - - - - - 35.00 - 1.00 - - - - - - - - - - - fsqrt +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - fst %st(0) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 fsts (%edx) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 fstl (%ecx) +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - fstp %st(0) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 fstpl (%edx) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 fstpl (%ecx) +# CHECK-NEXT: - 0.33 0.33 0.33 - - - - - - - - - - 0.33 0.33 0.33 0.50 0.50 - - 0.50 0.50 fstpt (%eax) +# CHECK-NEXT: - - - - 1.00 1.00 1.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fnstcw (%eax) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fnstenv (%eax) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fnstsw (%eax) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - frstor (%eax) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - wait +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fnsave (%eax) +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - fsub %st, %st(1) +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - fsub %st(2), %st +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - fsubs (%ecx) +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - fsubl (%eax) +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - fsubp %st, %st(1) +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - fsubp %st, %st(2) +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - fisubs (%ecx) +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - fisubl (%eax) +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - fsubr %st, %st(1) +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - fsubr %st(2), %st +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - fsubrs (%ecx) +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - fsubrl (%eax) +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - fsubrp %st, %st(1) +# CHECK-NEXT: - - - - - - - 2.00 - 2.00 0.50 0.50 - - - - - - - - - - - fsubrp %st, %st(2) +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - fisubrs (%ecx) +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - 0.50 0.50 0.50 0.50 - - fisubrl (%eax) +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - ftst +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - fucom %st(1) +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - fucom %st(3) +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - fucomp %st(1) +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - fucomp %st(3) +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - fucompp +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - fucomi %st(3), %st +# CHECK-NEXT: - - - - - - - 2.50 - 2.50 0.50 0.50 - - - - - - - - - - - fucompi %st(3), %st +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - wait +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fxam +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - fxch %st(1) +# CHECK-NEXT: - - - - 1.33 1.33 1.33 - - - - - - - 0.33 0.33 0.33 - - - - - - fxch %st(3) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fxrstor (%eax) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fxsave (%eax) +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fxtract +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fyl2x +# CHECK-NEXT: - - - - 9.00 9.00 9.00 - - - - - - - 0.33 0.33 0.33 - - - - - - fyl2xp1 diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/store-throughput.s b/llvm/test/tools/llvm-mca/X86/Barcelona/store-throughput.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/store-throughput.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/store-throughput.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -scheduler-stats -dispatch-stats -iterations=100 -timeline -timeline-max-iterations=1 -noalias=true < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -scheduler-stats -dispatch-stats -iterations=100 -timeline -timeline-max-iterations=1 -noalias=true < %s | FileCheck %s # LLVM-MCA-BEGIN movb %spl, (%rax) @@ -47,13 +47,13 @@ # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 400 -# CHECK-NEXT: Total Cycles: 403 +# CHECK-NEXT: Total Cycles: 1203 # CHECK-NEXT: Total uOps: 400 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 0.99 -# CHECK-NEXT: IPC: 0.99 -# CHECK-NEXT: Block RThroughput: 4.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.33 +# CHECK-NEXT: IPC: 0.33 +# CHECK-NEXT: Block RThroughput: 2.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -64,30 +64,29 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 1 1.00 * movb %spl, (%rax) -# CHECK-NEXT: 1 1 1.00 * movb %bpl, (%rcx) -# CHECK-NEXT: 1 1 1.00 * movb %sil, (%rdx) -# CHECK-NEXT: 1 1 1.00 * movb %dil, (%rbx) +# CHECK-NEXT: 1 3 0.50 * movb %spl, (%rax) +# CHECK-NEXT: 1 3 0.50 * movb %bpl, (%rcx) +# CHECK-NEXT: 1 3 0.50 * movb %sil, (%rdx) +# CHECK-NEXT: 1 3 0.50 * movb %dil, (%rbx) # CHECK: Dynamic Dispatch Stall Cycles: # CHECK-NEXT: RAT - Register unavailable: 0 # CHECK-NEXT: RCU - Retire tokens unavailable: 0 -# CHECK-NEXT: SCHEDQ - Scheduler full: 329 (81.6%) +# CHECK-NEXT: SCHEDQ - Scheduler full: 1117 (92.9%) # CHECK-NEXT: LQ - Load queue full: 0 # CHECK-NEXT: SQ - Store queue full: 0 # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK-NEXT: [# dispatched], [# cycles] -# CHECK-NEXT: 0, 56 (13.9%) -# CHECK-NEXT: 1, 329 (81.6%) -# CHECK-NEXT: 3, 1 (0.2%) -# CHECK-NEXT: 4, 17 (4.2%) +# CHECK-NEXT: 0, 821 (68.2%) +# CHECK-NEXT: 1, 373 (31.0%) +# CHECK-NEXT: 3, 9 (0.7%) # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: # CHECK-NEXT: [# issued], [# cycles] -# CHECK-NEXT: 0, 3 (0.7%) -# CHECK-NEXT: 1, 400 (99.3%) +# CHECK-NEXT: 0, 803 (66.7%) +# CHECK-NEXT: 1, 400 (33.3%) # CHECK: Scheduler's queue usage: # CHECK-NEXT: [1] Resource name. @@ -96,36 +95,55 @@ # CHECK-NEXT: [4] Total number of buffer entries. # CHECK: [1] [2] [3] [4] -# CHECK-NEXT: SBPortAny 49 54 54 +# CHECK-NEXT: BnFPU 0 0 36 +# CHECK-NEXT: BnInt 23 24 24 +# CHECK-NEXT: BnLoad 0 0 12 +# CHECK-NEXT: BnStore 24 25 32 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - - 4.00 - 2.00 2.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - 1.33 1.33 1.34 - - - - - - - - - - 1.33 1.33 1.34 2.00 2.00 - - 2.00 2.00 # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - 1.00 - - 1.00 movb %spl, (%rax) -# CHECK-NEXT: - - - - 1.00 - 1.00 - movb %bpl, (%rcx) -# CHECK-NEXT: - - - - 1.00 - - 1.00 movb %sil, (%rdx) -# CHECK-NEXT: - - - - 1.00 - 1.00 - movb %dil, (%rbx) +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - 0.33 0.33 0.34 - - - - - - - - - - 0.33 0.33 0.34 - 1.00 - - - 1.00 movb %spl, (%rax) +# CHECK-NEXT: - 0.33 0.34 0.33 - - - - - - - - - - 0.33 0.34 0.33 1.00 - - - 1.00 - movb %bpl, (%rcx) +# CHECK-NEXT: - 0.34 0.33 0.33 - - - - - - - - - - 0.34 0.33 0.33 - 1.00 - - - 1.00 movb %sil, (%rdx) +# CHECK-NEXT: - 0.33 0.33 0.34 - - - - - - - - - - 0.33 0.33 0.34 1.00 - - - 1.00 - movb %dil, (%rbx) # CHECK: Timeline view: -# CHECK-NEXT: Index 0123456 +# CHECK-NEXT: 01234 +# CHECK-NEXT: Index 0123456789 -# CHECK: [0,0] DeER .. movb %spl, (%rax) -# CHECK-NEXT: [0,1] D=eER.. movb %bpl, (%rcx) -# CHECK-NEXT: [0,2] D==eER. movb %sil, (%rdx) -# CHECK-NEXT: [0,3] D===eER movb %dil, (%rbx) +# CHECK: [0,0] DeeeER . . movb %spl, (%rax) +# CHECK-NEXT: [0,1] D===eeeER . . movb %bpl, (%rcx) +# CHECK-NEXT: [0,2] D======eeeER . movb %sil, (%rdx) +# CHECK-NEXT: [0,3] .D========eeeER movb %dil, (%rbx) # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -135,21 +153,21 @@ # CHECK: [0] [1] [2] [3] # CHECK-NEXT: 0. 1 1.0 1.0 0.0 movb %spl, (%rax) -# CHECK-NEXT: 1. 1 2.0 0.0 0.0 movb %bpl, (%rcx) -# CHECK-NEXT: 2. 1 3.0 0.0 0.0 movb %sil, (%rdx) -# CHECK-NEXT: 3. 1 4.0 0.0 0.0 movb %dil, (%rbx) +# CHECK-NEXT: 1. 1 4.0 0.0 0.0 movb %bpl, (%rcx) +# CHECK-NEXT: 2. 1 7.0 0.0 0.0 movb %sil, (%rdx) +# CHECK-NEXT: 3. 1 9.0 0.0 0.0 movb %dil, (%rbx) # CHECK: [1] Code Region # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 400 -# CHECK-NEXT: Total Cycles: 403 +# CHECK-NEXT: Total Cycles: 1203 # CHECK-NEXT: Total uOps: 400 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 0.99 -# CHECK-NEXT: IPC: 0.99 -# CHECK-NEXT: Block RThroughput: 4.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.33 +# CHECK-NEXT: IPC: 0.33 +# CHECK-NEXT: Block RThroughput: 2.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -160,30 +178,29 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 1 1.00 * movw %sp, (%rax) -# CHECK-NEXT: 1 1 1.00 * movw %bp, (%rcx) -# CHECK-NEXT: 1 1 1.00 * movw %si, (%rdx) -# CHECK-NEXT: 1 1 1.00 * movw %di, (%rbx) +# CHECK-NEXT: 1 3 0.50 * movw %sp, (%rax) +# CHECK-NEXT: 1 3 0.50 * movw %bp, (%rcx) +# CHECK-NEXT: 1 3 0.50 * movw %si, (%rdx) +# CHECK-NEXT: 1 3 0.50 * movw %di, (%rbx) # CHECK: Dynamic Dispatch Stall Cycles: # CHECK-NEXT: RAT - Register unavailable: 0 # CHECK-NEXT: RCU - Retire tokens unavailable: 0 -# CHECK-NEXT: SCHEDQ - Scheduler full: 329 (81.6%) +# CHECK-NEXT: SCHEDQ - Scheduler full: 1117 (92.9%) # CHECK-NEXT: LQ - Load queue full: 0 # CHECK-NEXT: SQ - Store queue full: 0 # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK-NEXT: [# dispatched], [# cycles] -# CHECK-NEXT: 0, 56 (13.9%) -# CHECK-NEXT: 1, 329 (81.6%) -# CHECK-NEXT: 3, 1 (0.2%) -# CHECK-NEXT: 4, 17 (4.2%) +# CHECK-NEXT: 0, 821 (68.2%) +# CHECK-NEXT: 1, 373 (31.0%) +# CHECK-NEXT: 3, 9 (0.7%) # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: # CHECK-NEXT: [# issued], [# cycles] -# CHECK-NEXT: 0, 3 (0.7%) -# CHECK-NEXT: 1, 400 (99.3%) +# CHECK-NEXT: 0, 803 (66.7%) +# CHECK-NEXT: 1, 400 (33.3%) # CHECK: Scheduler's queue usage: # CHECK-NEXT: [1] Resource name. @@ -192,36 +209,55 @@ # CHECK-NEXT: [4] Total number of buffer entries. # CHECK: [1] [2] [3] [4] -# CHECK-NEXT: SBPortAny 49 54 54 +# CHECK-NEXT: BnFPU 0 0 36 +# CHECK-NEXT: BnInt 23 24 24 +# CHECK-NEXT: BnLoad 0 0 12 +# CHECK-NEXT: BnStore 24 25 32 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - - 4.00 - 2.00 2.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - 1.33 1.33 1.34 - - - - - - - - - - 1.33 1.33 1.34 2.00 2.00 - - 2.00 2.00 # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - 1.00 - - 1.00 movw %sp, (%rax) -# CHECK-NEXT: - - - - 1.00 - 1.00 - movw %bp, (%rcx) -# CHECK-NEXT: - - - - 1.00 - - 1.00 movw %si, (%rdx) -# CHECK-NEXT: - - - - 1.00 - 1.00 - movw %di, (%rbx) +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - 0.33 0.33 0.34 - - - - - - - - - - 0.33 0.33 0.34 - 1.00 - - - 1.00 movw %sp, (%rax) +# CHECK-NEXT: - 0.33 0.34 0.33 - - - - - - - - - - 0.33 0.34 0.33 1.00 - - - 1.00 - movw %bp, (%rcx) +# CHECK-NEXT: - 0.34 0.33 0.33 - - - - - - - - - - 0.34 0.33 0.33 - 1.00 - - - 1.00 movw %si, (%rdx) +# CHECK-NEXT: - 0.33 0.33 0.34 - - - - - - - - - - 0.33 0.33 0.34 1.00 - - - 1.00 - movw %di, (%rbx) # CHECK: Timeline view: -# CHECK-NEXT: Index 0123456 +# CHECK-NEXT: 01234 +# CHECK-NEXT: Index 0123456789 -# CHECK: [0,0] DeER .. movw %sp, (%rax) -# CHECK-NEXT: [0,1] D=eER.. movw %bp, (%rcx) -# CHECK-NEXT: [0,2] D==eER. movw %si, (%rdx) -# CHECK-NEXT: [0,3] D===eER movw %di, (%rbx) +# CHECK: [0,0] DeeeER . . movw %sp, (%rax) +# CHECK-NEXT: [0,1] D===eeeER . . movw %bp, (%rcx) +# CHECK-NEXT: [0,2] D======eeeER . movw %si, (%rdx) +# CHECK-NEXT: [0,3] .D========eeeER movw %di, (%rbx) # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -231,21 +267,21 @@ # CHECK: [0] [1] [2] [3] # CHECK-NEXT: 0. 1 1.0 1.0 0.0 movw %sp, (%rax) -# CHECK-NEXT: 1. 1 2.0 0.0 0.0 movw %bp, (%rcx) -# CHECK-NEXT: 2. 1 3.0 0.0 0.0 movw %si, (%rdx) -# CHECK-NEXT: 3. 1 4.0 0.0 0.0 movw %di, (%rbx) +# CHECK-NEXT: 1. 1 4.0 0.0 0.0 movw %bp, (%rcx) +# CHECK-NEXT: 2. 1 7.0 0.0 0.0 movw %si, (%rdx) +# CHECK-NEXT: 3. 1 9.0 0.0 0.0 movw %di, (%rbx) # CHECK: [2] Code Region # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 400 -# CHECK-NEXT: Total Cycles: 403 +# CHECK-NEXT: Total Cycles: 1203 # CHECK-NEXT: Total uOps: 400 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 0.99 -# CHECK-NEXT: IPC: 0.99 -# CHECK-NEXT: Block RThroughput: 4.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.33 +# CHECK-NEXT: IPC: 0.33 +# CHECK-NEXT: Block RThroughput: 2.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -256,30 +292,29 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 1 1.00 * movl %esp, (%rax) -# CHECK-NEXT: 1 1 1.00 * movl %ebp, (%rcx) -# CHECK-NEXT: 1 1 1.00 * movl %esi, (%rdx) -# CHECK-NEXT: 1 1 1.00 * movl %edi, (%rbx) +# CHECK-NEXT: 1 3 0.50 * movl %esp, (%rax) +# CHECK-NEXT: 1 3 0.50 * movl %ebp, (%rcx) +# CHECK-NEXT: 1 3 0.50 * movl %esi, (%rdx) +# CHECK-NEXT: 1 3 0.50 * movl %edi, (%rbx) # CHECK: Dynamic Dispatch Stall Cycles: # CHECK-NEXT: RAT - Register unavailable: 0 # CHECK-NEXT: RCU - Retire tokens unavailable: 0 -# CHECK-NEXT: SCHEDQ - Scheduler full: 329 (81.6%) +# CHECK-NEXT: SCHEDQ - Scheduler full: 1117 (92.9%) # CHECK-NEXT: LQ - Load queue full: 0 # CHECK-NEXT: SQ - Store queue full: 0 # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK-NEXT: [# dispatched], [# cycles] -# CHECK-NEXT: 0, 56 (13.9%) -# CHECK-NEXT: 1, 329 (81.6%) -# CHECK-NEXT: 3, 1 (0.2%) -# CHECK-NEXT: 4, 17 (4.2%) +# CHECK-NEXT: 0, 821 (68.2%) +# CHECK-NEXT: 1, 373 (31.0%) +# CHECK-NEXT: 3, 9 (0.7%) # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: # CHECK-NEXT: [# issued], [# cycles] -# CHECK-NEXT: 0, 3 (0.7%) -# CHECK-NEXT: 1, 400 (99.3%) +# CHECK-NEXT: 0, 803 (66.7%) +# CHECK-NEXT: 1, 400 (33.3%) # CHECK: Scheduler's queue usage: # CHECK-NEXT: [1] Resource name. @@ -288,36 +323,55 @@ # CHECK-NEXT: [4] Total number of buffer entries. # CHECK: [1] [2] [3] [4] -# CHECK-NEXT: SBPortAny 49 54 54 +# CHECK-NEXT: BnFPU 0 0 36 +# CHECK-NEXT: BnInt 23 24 24 +# CHECK-NEXT: BnLoad 0 0 12 +# CHECK-NEXT: BnStore 24 25 32 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - - 4.00 - 2.00 2.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - 1.33 1.33 1.34 - - - - - - - - - - 1.33 1.33 1.34 2.00 2.00 - - 2.00 2.00 # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - 1.00 - - 1.00 movl %esp, (%rax) -# CHECK-NEXT: - - - - 1.00 - 1.00 - movl %ebp, (%rcx) -# CHECK-NEXT: - - - - 1.00 - - 1.00 movl %esi, (%rdx) -# CHECK-NEXT: - - - - 1.00 - 1.00 - movl %edi, (%rbx) +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - 0.33 0.33 0.34 - - - - - - - - - - 0.33 0.33 0.34 - 1.00 - - - 1.00 movl %esp, (%rax) +# CHECK-NEXT: - 0.33 0.34 0.33 - - - - - - - - - - 0.33 0.34 0.33 1.00 - - - 1.00 - movl %ebp, (%rcx) +# CHECK-NEXT: - 0.34 0.33 0.33 - - - - - - - - - - 0.34 0.33 0.33 - 1.00 - - - 1.00 movl %esi, (%rdx) +# CHECK-NEXT: - 0.33 0.33 0.34 - - - - - - - - - - 0.33 0.33 0.34 1.00 - - - 1.00 - movl %edi, (%rbx) # CHECK: Timeline view: -# CHECK-NEXT: Index 0123456 +# CHECK-NEXT: 01234 +# CHECK-NEXT: Index 0123456789 -# CHECK: [0,0] DeER .. movl %esp, (%rax) -# CHECK-NEXT: [0,1] D=eER.. movl %ebp, (%rcx) -# CHECK-NEXT: [0,2] D==eER. movl %esi, (%rdx) -# CHECK-NEXT: [0,3] D===eER movl %edi, (%rbx) +# CHECK: [0,0] DeeeER . . movl %esp, (%rax) +# CHECK-NEXT: [0,1] D===eeeER . . movl %ebp, (%rcx) +# CHECK-NEXT: [0,2] D======eeeER . movl %esi, (%rdx) +# CHECK-NEXT: [0,3] .D========eeeER movl %edi, (%rbx) # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -327,21 +381,21 @@ # CHECK: [0] [1] [2] [3] # CHECK-NEXT: 0. 1 1.0 1.0 0.0 movl %esp, (%rax) -# CHECK-NEXT: 1. 1 2.0 0.0 0.0 movl %ebp, (%rcx) -# CHECK-NEXT: 2. 1 3.0 0.0 0.0 movl %esi, (%rdx) -# CHECK-NEXT: 3. 1 4.0 0.0 0.0 movl %edi, (%rbx) +# CHECK-NEXT: 1. 1 4.0 0.0 0.0 movl %ebp, (%rcx) +# CHECK-NEXT: 2. 1 7.0 0.0 0.0 movl %esi, (%rdx) +# CHECK-NEXT: 3. 1 9.0 0.0 0.0 movl %edi, (%rbx) # CHECK: [3] Code Region # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 400 -# CHECK-NEXT: Total Cycles: 403 +# CHECK-NEXT: Total Cycles: 1203 # CHECK-NEXT: Total uOps: 400 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 0.99 -# CHECK-NEXT: IPC: 0.99 -# CHECK-NEXT: Block RThroughput: 4.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.33 +# CHECK-NEXT: IPC: 0.33 +# CHECK-NEXT: Block RThroughput: 2.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -352,30 +406,29 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 1 1.00 * movq %rsp, (%rax) -# CHECK-NEXT: 1 1 1.00 * movq %rbp, (%rcx) -# CHECK-NEXT: 1 1 1.00 * movq %rsi, (%rdx) -# CHECK-NEXT: 1 1 1.00 * movq %rdi, (%rbx) +# CHECK-NEXT: 1 3 0.50 * movq %rsp, (%rax) +# CHECK-NEXT: 1 3 0.50 * movq %rbp, (%rcx) +# CHECK-NEXT: 1 3 0.50 * movq %rsi, (%rdx) +# CHECK-NEXT: 1 3 0.50 * movq %rdi, (%rbx) # CHECK: Dynamic Dispatch Stall Cycles: # CHECK-NEXT: RAT - Register unavailable: 0 # CHECK-NEXT: RCU - Retire tokens unavailable: 0 -# CHECK-NEXT: SCHEDQ - Scheduler full: 329 (81.6%) +# CHECK-NEXT: SCHEDQ - Scheduler full: 1117 (92.9%) # CHECK-NEXT: LQ - Load queue full: 0 # CHECK-NEXT: SQ - Store queue full: 0 # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK-NEXT: [# dispatched], [# cycles] -# CHECK-NEXT: 0, 56 (13.9%) -# CHECK-NEXT: 1, 329 (81.6%) -# CHECK-NEXT: 3, 1 (0.2%) -# CHECK-NEXT: 4, 17 (4.2%) +# CHECK-NEXT: 0, 821 (68.2%) +# CHECK-NEXT: 1, 373 (31.0%) +# CHECK-NEXT: 3, 9 (0.7%) # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: # CHECK-NEXT: [# issued], [# cycles] -# CHECK-NEXT: 0, 3 (0.7%) -# CHECK-NEXT: 1, 400 (99.3%) +# CHECK-NEXT: 0, 803 (66.7%) +# CHECK-NEXT: 1, 400 (33.3%) # CHECK: Scheduler's queue usage: # CHECK-NEXT: [1] Resource name. @@ -384,36 +437,55 @@ # CHECK-NEXT: [4] Total number of buffer entries. # CHECK: [1] [2] [3] [4] -# CHECK-NEXT: SBPortAny 49 54 54 +# CHECK-NEXT: BnFPU 0 0 36 +# CHECK-NEXT: BnInt 23 24 24 +# CHECK-NEXT: BnLoad 0 0 12 +# CHECK-NEXT: BnStore 24 25 32 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - - 4.00 - 2.00 2.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - 1.33 1.33 1.34 - - - - - - - - - - 1.33 1.33 1.34 2.00 2.00 - - 2.00 2.00 # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - 1.00 - - 1.00 movq %rsp, (%rax) -# CHECK-NEXT: - - - - 1.00 - 1.00 - movq %rbp, (%rcx) -# CHECK-NEXT: - - - - 1.00 - - 1.00 movq %rsi, (%rdx) -# CHECK-NEXT: - - - - 1.00 - 1.00 - movq %rdi, (%rbx) +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - 0.33 0.33 0.34 - - - - - - - - - - 0.33 0.33 0.34 - 1.00 - - - 1.00 movq %rsp, (%rax) +# CHECK-NEXT: - 0.33 0.34 0.33 - - - - - - - - - - 0.33 0.34 0.33 1.00 - - - 1.00 - movq %rbp, (%rcx) +# CHECK-NEXT: - 0.34 0.33 0.33 - - - - - - - - - - 0.34 0.33 0.33 - 1.00 - - - 1.00 movq %rsi, (%rdx) +# CHECK-NEXT: - 0.33 0.33 0.34 - - - - - - - - - - 0.33 0.33 0.34 1.00 - - - 1.00 - movq %rdi, (%rbx) # CHECK: Timeline view: -# CHECK-NEXT: Index 0123456 +# CHECK-NEXT: 01234 +# CHECK-NEXT: Index 0123456789 -# CHECK: [0,0] DeER .. movq %rsp, (%rax) -# CHECK-NEXT: [0,1] D=eER.. movq %rbp, (%rcx) -# CHECK-NEXT: [0,2] D==eER. movq %rsi, (%rdx) -# CHECK-NEXT: [0,3] D===eER movq %rdi, (%rbx) +# CHECK: [0,0] DeeeER . . movq %rsp, (%rax) +# CHECK-NEXT: [0,1] D===eeeER . . movq %rbp, (%rcx) +# CHECK-NEXT: [0,2] D======eeeER . movq %rsi, (%rdx) +# CHECK-NEXT: [0,3] .D========eeeER movq %rdi, (%rbx) # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -423,20 +495,20 @@ # CHECK: [0] [1] [2] [3] # CHECK-NEXT: 0. 1 1.0 1.0 0.0 movq %rsp, (%rax) -# CHECK-NEXT: 1. 1 2.0 0.0 0.0 movq %rbp, (%rcx) -# CHECK-NEXT: 2. 1 3.0 0.0 0.0 movq %rsi, (%rdx) -# CHECK-NEXT: 3. 1 4.0 0.0 0.0 movq %rdi, (%rbx) +# CHECK-NEXT: 1. 1 4.0 0.0 0.0 movq %rbp, (%rcx) +# CHECK-NEXT: 2. 1 7.0 0.0 0.0 movq %rsi, (%rdx) +# CHECK-NEXT: 3. 1 9.0 0.0 0.0 movq %rdi, (%rbx) # CHECK: [4] Code Region # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 400 -# CHECK-NEXT: Total Cycles: 403 +# CHECK-NEXT: Total Cycles: 803 # CHECK-NEXT: Total uOps: 400 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 0.99 -# CHECK-NEXT: IPC: 0.99 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.50 +# CHECK-NEXT: IPC: 0.50 # CHECK-NEXT: Block RThroughput: 4.0 # CHECK: Instruction Info: @@ -448,30 +520,29 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 1 1.00 * U movd %mm0, (%rax) -# CHECK-NEXT: 1 1 1.00 * U movd %mm1, (%rcx) -# CHECK-NEXT: 1 1 1.00 * U movd %mm2, (%rdx) -# CHECK-NEXT: 1 1 1.00 * U movd %mm3, (%rbx) +# CHECK-NEXT: 1 2 1.00 * U movd %mm0, (%rax) +# CHECK-NEXT: 1 2 1.00 * U movd %mm1, (%rcx) +# CHECK-NEXT: 1 2 1.00 * U movd %mm2, (%rdx) +# CHECK-NEXT: 1 2 1.00 * U movd %mm3, (%rbx) # CHECK: Dynamic Dispatch Stall Cycles: # CHECK-NEXT: RAT - Register unavailable: 0 # CHECK-NEXT: RCU - Retire tokens unavailable: 0 -# CHECK-NEXT: SCHEDQ - Scheduler full: 329 (81.6%) +# CHECK-NEXT: SCHEDQ - Scheduler full: 0 # CHECK-NEXT: LQ - Load queue full: 0 -# CHECK-NEXT: SQ - Store queue full: 0 +# CHECK-NEXT: SQ - Store queue full: 725 (90.3%) # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK-NEXT: [# dispatched], [# cycles] -# CHECK-NEXT: 0, 56 (13.9%) -# CHECK-NEXT: 1, 329 (81.6%) -# CHECK-NEXT: 3, 1 (0.2%) -# CHECK-NEXT: 4, 17 (4.2%) +# CHECK-NEXT: 0, 427 (53.2%) +# CHECK-NEXT: 1, 364 (45.3%) +# CHECK-NEXT: 3, 12 (1.5%) # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: # CHECK-NEXT: [# issued], [# cycles] -# CHECK-NEXT: 0, 3 (0.7%) -# CHECK-NEXT: 1, 400 (99.3%) +# CHECK-NEXT: 0, 403 (50.2%) +# CHECK-NEXT: 1, 400 (49.8%) # CHECK: Scheduler's queue usage: # CHECK-NEXT: [1] Resource name. @@ -480,36 +551,55 @@ # CHECK-NEXT: [4] Total number of buffer entries. # CHECK: [1] [2] [3] [4] -# CHECK-NEXT: SBPortAny 49 54 54 +# CHECK-NEXT: BnFPU 29 31 36 +# CHECK-NEXT: BnInt 0 0 24 +# CHECK-NEXT: BnLoad 0 0 12 +# CHECK-NEXT: BnStore 30 32 32 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - - 4.00 - 2.00 2.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - - - - - 4.00 - - - 4.00 - - - - 2.00 2.00 - - 2.00 2.00 # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - 1.00 - - 1.00 movd %mm0, (%rax) -# CHECK-NEXT: - - - - 1.00 - 1.00 - movd %mm1, (%rcx) -# CHECK-NEXT: - - - - 1.00 - - 1.00 movd %mm2, (%rdx) -# CHECK-NEXT: - - - - 1.00 - 1.00 - movd %mm3, (%rbx) +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - - 1.00 - - - 1.00 movd %mm0, (%rax) +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 1.00 - - - 1.00 - movd %mm1, (%rcx) +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - - 1.00 - - - 1.00 movd %mm2, (%rdx) +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 1.00 - - - 1.00 - movd %mm3, (%rbx) # CHECK: Timeline view: -# CHECK-NEXT: Index 0123456 +# CHECK-NEXT: 0 +# CHECK-NEXT: Index 0123456789 -# CHECK: [0,0] DeER .. movd %mm0, (%rax) -# CHECK-NEXT: [0,1] D=eER.. movd %mm1, (%rcx) -# CHECK-NEXT: [0,2] D==eER. movd %mm2, (%rdx) -# CHECK-NEXT: [0,3] D===eER movd %mm3, (%rbx) +# CHECK: [0,0] DeeER. . movd %mm0, (%rax) +# CHECK-NEXT: [0,1] D==eeER . movd %mm1, (%rcx) +# CHECK-NEXT: [0,2] D====eeER . movd %mm2, (%rdx) +# CHECK-NEXT: [0,3] .D=====eeER movd %mm3, (%rbx) # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -519,20 +609,20 @@ # CHECK: [0] [1] [2] [3] # CHECK-NEXT: 0. 1 1.0 1.0 0.0 movd %mm0, (%rax) -# CHECK-NEXT: 1. 1 2.0 0.0 0.0 movd %mm1, (%rcx) -# CHECK-NEXT: 2. 1 3.0 0.0 0.0 movd %mm2, (%rdx) -# CHECK-NEXT: 3. 1 4.0 0.0 0.0 movd %mm3, (%rbx) +# CHECK-NEXT: 1. 1 3.0 0.0 0.0 movd %mm1, (%rcx) +# CHECK-NEXT: 2. 1 5.0 0.0 0.0 movd %mm2, (%rdx) +# CHECK-NEXT: 3. 1 6.0 0.0 0.0 movd %mm3, (%rbx) # CHECK: [5] Code Region # CHECK: Iterations: 100 # CHECK-NEXT: Instructions: 400 -# CHECK-NEXT: Total Cycles: 403 -# CHECK-NEXT: Total uOps: 400 +# CHECK-NEXT: Total Cycles: 803 +# CHECK-NEXT: Total uOps: 800 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 0.99 -# CHECK-NEXT: IPC: 0.99 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 1.00 +# CHECK-NEXT: IPC: 0.50 # CHECK-NEXT: Block RThroughput: 4.0 # CHECK: Instruction Info: @@ -544,30 +634,28 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 1 1.00 * movaps %xmm0, (%rax) -# CHECK-NEXT: 1 1 1.00 * movaps %xmm1, (%rcx) -# CHECK-NEXT: 1 1 1.00 * movaps %xmm2, (%rdx) -# CHECK-NEXT: 1 1 1.00 * movaps %xmm3, (%rbx) +# CHECK-NEXT: 2 2 1.00 * movaps %xmm0, (%rax) +# CHECK-NEXT: 2 2 1.00 * movaps %xmm1, (%rcx) +# CHECK-NEXT: 2 2 1.00 * movaps %xmm2, (%rdx) +# CHECK-NEXT: 2 2 1.00 * movaps %xmm3, (%rbx) # CHECK: Dynamic Dispatch Stall Cycles: # CHECK-NEXT: RAT - Register unavailable: 0 # CHECK-NEXT: RCU - Retire tokens unavailable: 0 -# CHECK-NEXT: SCHEDQ - Scheduler full: 329 (81.6%) +# CHECK-NEXT: SCHEDQ - Scheduler full: 0 # CHECK-NEXT: LQ - Load queue full: 0 -# CHECK-NEXT: SQ - Store queue full: 0 +# CHECK-NEXT: SQ - Store queue full: 338 (42.1%) # CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0 # CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: # CHECK-NEXT: [# dispatched], [# cycles] -# CHECK-NEXT: 0, 56 (13.9%) -# CHECK-NEXT: 1, 329 (81.6%) -# CHECK-NEXT: 3, 1 (0.2%) -# CHECK-NEXT: 4, 17 (4.2%) +# CHECK-NEXT: 0, 403 (50.2%) +# CHECK-NEXT: 2, 400 (49.8%) # CHECK: Schedulers - number of cycles where we saw N micro opcodes issued: # CHECK-NEXT: [# issued], [# cycles] -# CHECK-NEXT: 0, 3 (0.7%) -# CHECK-NEXT: 1, 400 (99.3%) +# CHECK-NEXT: 0, 403 (50.2%) +# CHECK-NEXT: 2, 400 (49.8%) # CHECK: Scheduler's queue usage: # CHECK-NEXT: [1] Resource name. @@ -576,36 +664,55 @@ # CHECK-NEXT: [4] Total number of buffer entries. # CHECK: [1] [2] [3] [4] -# CHECK-NEXT: SBPortAny 49 54 54 +# CHECK-NEXT: BnFPU 28 31 36 +# CHECK-NEXT: BnInt 0 0 24 +# CHECK-NEXT: BnLoad 0 0 12 +# CHECK-NEXT: BnStore 29 32 32 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - - - 4.00 - 2.00 2.00 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - - - - - 4.00 - - - 4.00 - - - - 4.00 4.00 - - 4.00 4.00 # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - 1.00 - - 1.00 movaps %xmm0, (%rax) -# CHECK-NEXT: - - - - 1.00 - 1.00 - movaps %xmm1, (%rcx) -# CHECK-NEXT: - - - - 1.00 - - 1.00 movaps %xmm2, (%rdx) -# CHECK-NEXT: - - - - 1.00 - 1.00 - movaps %xmm3, (%rbx) +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - - 2.00 - - - 2.00 movaps %xmm0, (%rax) +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 2.00 - - - 2.00 - movaps %xmm1, (%rcx) +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - - 2.00 - - - 2.00 movaps %xmm2, (%rdx) +# CHECK-NEXT: - - - - - - - - 1.00 - - - 1.00 - - - - 2.00 - - - 2.00 - movaps %xmm3, (%rbx) # CHECK: Timeline view: -# CHECK-NEXT: Index 0123456 +# CHECK-NEXT: 0 +# CHECK-NEXT: Index 0123456789 -# CHECK: [0,0] DeER .. movaps %xmm0, (%rax) -# CHECK-NEXT: [0,1] D=eER.. movaps %xmm1, (%rcx) -# CHECK-NEXT: [0,2] D==eER. movaps %xmm2, (%rdx) -# CHECK-NEXT: [0,3] D===eER movaps %xmm3, (%rbx) +# CHECK: [0,0] DeeER. . movaps %xmm0, (%rax) +# CHECK-NEXT: [0,1] .D=eeER . movaps %xmm1, (%rcx) +# CHECK-NEXT: [0,2] . D==eeER . movaps %xmm2, (%rdx) +# CHECK-NEXT: [0,3] . D===eeER movaps %xmm3, (%rbx) # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/zero-idioms.s b/llvm/test/tools/llvm-mca/X86/Barcelona/zero-idioms.s --- a/llvm/test/tools/llvm-mca/X86/Barcelona/zero-idioms.s +++ b/llvm/test/tools/llvm-mca/X86/Barcelona/zero-idioms.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -timeline -register-file-stats -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -timeline -register-file-stats -iterations=1 < %s | FileCheck %s subl %eax, %eax subq %rax, %rax @@ -49,13 +49,13 @@ # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 35 -# CHECK-NEXT: Total Cycles: 39 +# CHECK-NEXT: Total Cycles: 66 # CHECK-NEXT: Total uOps: 35 -# CHECK: Dispatch Width: 4 -# CHECK-NEXT: uOps Per Cycle: 0.90 -# CHECK-NEXT: IPC: 0.90 -# CHECK-NEXT: Block RThroughput: 11.0 +# CHECK: Dispatch Width: 3 +# CHECK-NEXT: uOps Per Cycle: 0.53 +# CHECK-NEXT: IPC: 0.53 +# CHECK-NEXT: Block RThroughput: 62.5 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -66,137 +66,162 @@ # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 0 0.25 subl %eax, %eax -# CHECK-NEXT: 1 0 0.25 subq %rax, %rax -# CHECK-NEXT: 1 0 0.25 xorl %eax, %eax -# CHECK-NEXT: 1 0 0.25 xorq %rax, %rax -# CHECK-NEXT: 1 3 1.00 pcmpgtb %mm2, %mm2 -# CHECK-NEXT: 1 3 1.00 pcmpgtd %mm2, %mm2 -# CHECK-NEXT: 1 3 1.00 pcmpgtw %mm2, %mm2 -# CHECK-NEXT: 1 0 0.25 pcmpgtb %xmm2, %xmm2 -# CHECK-NEXT: 1 0 0.25 pcmpgtd %xmm2, %xmm2 -# CHECK-NEXT: 1 0 0.25 pcmpgtq %xmm2, %xmm2 -# CHECK-NEXT: 1 0 0.25 pcmpgtw %xmm2, %xmm2 -# CHECK-NEXT: 1 3 1.00 psubb %mm2, %mm2 -# CHECK-NEXT: 1 3 1.00 psubd %mm2, %mm2 -# CHECK-NEXT: 1 3 1.00 psubq %mm2, %mm2 -# CHECK-NEXT: 1 3 1.00 psubw %mm2, %mm2 -# CHECK-NEXT: 1 0 0.25 psubb %xmm2, %xmm2 -# CHECK-NEXT: 1 0 0.25 psubd %xmm2, %xmm2 -# CHECK-NEXT: 1 0 0.25 psubq %xmm2, %xmm2 -# CHECK-NEXT: 1 0 0.25 psubw %xmm2, %xmm2 -# CHECK-NEXT: 1 3 1.00 psubsb %mm2, %mm2 -# CHECK-NEXT: 1 3 1.00 psubsw %mm2, %mm2 -# CHECK-NEXT: 1 1 0.50 psubsb %xmm2, %xmm2 -# CHECK-NEXT: 1 1 0.50 psubsw %xmm2, %xmm2 -# CHECK-NEXT: 1 3 1.00 psubusb %mm2, %mm2 -# CHECK-NEXT: 1 3 1.00 psubusw %mm2, %mm2 -# CHECK-NEXT: 1 1 0.50 psubusb %xmm2, %xmm2 -# CHECK-NEXT: 1 1 0.50 psubusw %xmm2, %xmm2 -# CHECK-NEXT: 1 1 1.00 andnps %xmm0, %xmm0 -# CHECK-NEXT: 1 1 1.00 andnpd %xmm1, %xmm1 -# CHECK-NEXT: 1 1 0.33 pandn %mm2, %mm2 -# CHECK-NEXT: 1 1 0.33 pandn %xmm2, %xmm2 -# CHECK-NEXT: 1 0 0.25 xorps %xmm0, %xmm0 -# CHECK-NEXT: 1 0 0.25 xorpd %xmm1, %xmm1 -# CHECK-NEXT: 1 1 0.33 pxor %mm2, %mm2 -# CHECK-NEXT: 1 0 0.25 pxor %xmm2, %xmm2 +# CHECK-NEXT: 1 2 1.00 subl %eax, %eax +# CHECK-NEXT: 1 2 1.00 subq %rax, %rax +# CHECK-NEXT: 1 2 1.00 xorl %eax, %eax +# CHECK-NEXT: 1 2 1.00 xorq %rax, %rax +# CHECK-NEXT: 1 2 1.50 pcmpgtb %mm2, %mm2 +# CHECK-NEXT: 1 2 1.50 pcmpgtd %mm2, %mm2 +# CHECK-NEXT: 1 2 1.50 pcmpgtw %mm2, %mm2 +# CHECK-NEXT: 1 3 2.50 pcmpgtb %xmm2, %xmm2 +# CHECK-NEXT: 1 3 2.50 pcmpgtd %xmm2, %xmm2 +# CHECK-NEXT: 1 3 2.50 pcmpgtq %xmm2, %xmm2 +# CHECK-NEXT: 1 3 2.50 pcmpgtw %xmm2, %xmm2 +# CHECK-NEXT: 1 2 1.50 psubb %mm2, %mm2 +# CHECK-NEXT: 1 2 1.50 psubd %mm2, %mm2 +# CHECK-NEXT: 1 2 1.50 psubq %mm2, %mm2 +# CHECK-NEXT: 1 2 1.50 psubw %mm2, %mm2 +# CHECK-NEXT: 1 3 2.50 psubb %xmm2, %xmm2 +# CHECK-NEXT: 1 3 2.50 psubd %xmm2, %xmm2 +# CHECK-NEXT: 1 3 2.50 psubq %xmm2, %xmm2 +# CHECK-NEXT: 1 3 2.50 psubw %xmm2, %xmm2 +# CHECK-NEXT: 1 2 1.50 psubsb %mm2, %mm2 +# CHECK-NEXT: 1 2 1.50 psubsw %mm2, %mm2 +# CHECK-NEXT: 1 3 2.50 psubsb %xmm2, %xmm2 +# CHECK-NEXT: 1 3 2.50 psubsw %xmm2, %xmm2 +# CHECK-NEXT: 1 2 1.50 psubusb %mm2, %mm2 +# CHECK-NEXT: 1 2 1.50 psubusw %mm2, %mm2 +# CHECK-NEXT: 1 3 2.50 psubusb %xmm2, %xmm2 +# CHECK-NEXT: 1 3 2.50 psubusw %xmm2, %xmm2 +# CHECK-NEXT: 1 2 2.00 andnps %xmm0, %xmm0 +# CHECK-NEXT: 1 2 2.00 andnpd %xmm1, %xmm1 +# CHECK-NEXT: 1 2 1.50 pandn %mm2, %mm2 +# CHECK-NEXT: 1 3 2.50 pandn %xmm2, %xmm2 +# CHECK-NEXT: 1 2 2.00 xorps %xmm0, %xmm0 +# CHECK-NEXT: 1 2 2.00 xorpd %xmm1, %xmm1 +# CHECK-NEXT: 1 2 1.50 pxor %mm2, %mm2 +# CHECK-NEXT: 1 3 2.50 pxor %xmm2, %xmm2 # CHECK: Register File statistics: # CHECK-NEXT: Total number of mappings created: 39 -# CHECK-NEXT: Max number of mappings used: 30 +# CHECK-NEXT: Max number of mappings used: 28 + +# CHECK: * Register File #1 -- BnFpuPRF: +# CHECK-NEXT: Number of physical registers: 120 +# CHECK-NEXT: Total number of mappings created: 31 +# CHECK-NEXT: Max number of mappings used: 27 + +# CHECK: * Register File #2 -- BnIntPRF: +# CHECK-NEXT: Number of physical registers: 40 +# CHECK-NEXT: Total number of mappings created: 8 +# CHECK-NEXT: Max number of mappings used: 8 # CHECK: Resources: -# CHECK-NEXT: [0] - SBDivider -# CHECK-NEXT: [1] - SBFPDivider -# CHECK-NEXT: [2] - SBPort0 -# CHECK-NEXT: [3] - SBPort1 -# CHECK-NEXT: [4] - SBPort4 -# CHECK-NEXT: [5] - SBPort5 -# CHECK-NEXT: [6.0] - SBPort23 -# CHECK-NEXT: [6.1] - SBPort23 +# CHECK-NEXT: [0] - BnABM +# CHECK-NEXT: [1] - BnAGU0 +# CHECK-NEXT: [2] - BnAGU1 +# CHECK-NEXT: [3] - BnAGU2 +# CHECK-NEXT: [4] - BnALU0 +# CHECK-NEXT: [5] - BnALU1 +# CHECK-NEXT: [6] - BnALU2 +# CHECK-NEXT: [7] - BnFADD +# CHECK-NEXT: [8] - BnFMISC +# CHECK-NEXT: [9] - BnFMUL +# CHECK-NEXT: [10] - BnFPU0 +# CHECK-NEXT: [11] - BnFPU1 +# CHECK-NEXT: [12] - BnFPU2 +# CHECK-NEXT: [13] - BnIMUL +# CHECK-NEXT: [14] - BnInt0 +# CHECK-NEXT: [15] - BnInt1 +# CHECK-NEXT: [16] - BnInt2 +# CHECK-NEXT: [17.0] - BnLSU +# CHECK-NEXT: [17.1] - BnLSU +# CHECK-NEXT: [18.0] - BnLoad +# CHECK-NEXT: [18.1] - BnLoad +# CHECK-NEXT: [19.0] - BnStore +# CHECK-NEXT: [19.1] - BnStore # CHECK: Resource pressure per iteration: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] -# CHECK-NEXT: - - 2.00 12.00 - 6.00 - - +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] +# CHECK-NEXT: - - - - 3.00 3.00 6.00 61.00 - 64.00 15.00 16.00 - - 1.00 1.00 2.00 - - - - - - # CHECK: Resource pressure by instruction: -# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - - - - - - - subl %eax, %eax -# CHECK-NEXT: - - - - - - - - subq %rax, %rax -# CHECK-NEXT: - - - - - - - - xorl %eax, %eax -# CHECK-NEXT: - - - - - - - - xorq %rax, %rax -# CHECK-NEXT: - - - 1.00 - - - - pcmpgtb %mm2, %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pcmpgtd %mm2, %mm2 -# CHECK-NEXT: - - - 1.00 - - - - pcmpgtw %mm2, %mm2 -# CHECK-NEXT: - - - - - - - - pcmpgtb %xmm2, %xmm2 -# CHECK-NEXT: - - - - - - - - pcmpgtd %xmm2, %xmm2 -# CHECK-NEXT: - - - - - - - - pcmpgtq %xmm2, %xmm2 -# CHECK-NEXT: - - - - - - - - pcmpgtw %xmm2, %xmm2 -# CHECK-NEXT: - - - 1.00 - - - - psubb %mm2, %mm2 -# CHECK-NEXT: - - - 1.00 - - - - psubd %mm2, %mm2 -# CHECK-NEXT: - - - 1.00 - - - - psubq %mm2, %mm2 -# CHECK-NEXT: - - - 1.00 - - - - psubw %mm2, %mm2 -# CHECK-NEXT: - - - - - - - - psubb %xmm2, %xmm2 -# CHECK-NEXT: - - - - - - - - psubd %xmm2, %xmm2 -# CHECK-NEXT: - - - - - - - - psubq %xmm2, %xmm2 -# CHECK-NEXT: - - - - - - - - psubw %xmm2, %xmm2 -# CHECK-NEXT: - - - 1.00 - - - - psubsb %mm2, %mm2 -# CHECK-NEXT: - - - 1.00 - - - - psubsw %mm2, %mm2 -# CHECK-NEXT: - - - - - 1.00 - - psubsb %xmm2, %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - psubsw %xmm2, %xmm2 -# CHECK-NEXT: - - - 1.00 - - - - psubusb %mm2, %mm2 -# CHECK-NEXT: - - - 1.00 - - - - psubusw %mm2, %mm2 -# CHECK-NEXT: - - - - - 1.00 - - psubusb %xmm2, %xmm2 -# CHECK-NEXT: - - - 1.00 - - - - psubusw %xmm2, %xmm2 -# CHECK-NEXT: - - - - - 1.00 - - andnps %xmm0, %xmm0 -# CHECK-NEXT: - - - - - 1.00 - - andnpd %xmm1, %xmm1 -# CHECK-NEXT: - - 1.00 - - - - - pandn %mm2, %mm2 -# CHECK-NEXT: - - 1.00 - - - - - pandn %xmm2, %xmm2 -# CHECK-NEXT: - - - - - - - - xorps %xmm0, %xmm0 -# CHECK-NEXT: - - - - - - - - xorpd %xmm1, %xmm1 -# CHECK-NEXT: - - - - - 1.00 - - pxor %mm2, %mm2 -# CHECK-NEXT: - - - - - - - - pxor %xmm2, %xmm2 +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17.0] [17.1] [18.0] [18.1] [19.0] [19.1] Instructions: +# CHECK-NEXT: - - - - - - 3.00 - - - - - - - - - 1.00 - - - - - - subl %eax, %eax +# CHECK-NEXT: - - - - - 3.00 - - - - - - - - - 1.00 - - - - - - - subq %rax, %rax +# CHECK-NEXT: - - - - 3.00 - - - - - - - - - 1.00 - - - - - - - - xorl %eax, %eax +# CHECK-NEXT: - - - - - - 3.00 - - - - - - - - - 1.00 - - - - - - xorq %rax, %rax +# CHECK-NEXT: - - - - - - - - - 3.00 - 1.00 - - - - - - - - - - - pcmpgtb %mm2, %mm2 +# CHECK-NEXT: - - - - - - - - - 3.00 - 1.00 - - - - - - - - - - - pcmpgtd %mm2, %mm2 +# CHECK-NEXT: - - - - - - - 3.00 - - 1.00 - - - - - - - - - - - - pcmpgtw %mm2, %mm2 +# CHECK-NEXT: - - - - - - - 5.00 - - 1.00 - - - - - - - - - - - - pcmpgtb %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - - - 5.00 - 1.00 - - - - - - - - - - - pcmpgtd %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - 5.00 - - 1.00 - - - - - - - - - - - - pcmpgtq %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - 5.00 - - 1.00 - - - - - - - - - - - - pcmpgtw %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - - - 3.00 - 1.00 - - - - - - - - - - - psubb %mm2, %mm2 +# CHECK-NEXT: - - - - - - - - - 3.00 - 1.00 - - - - - - - - - - - psubd %mm2, %mm2 +# CHECK-NEXT: - - - - - - - - - 3.00 1.00 - - - - - - - - - - - - psubq %mm2, %mm2 +# CHECK-NEXT: - - - - - - - 3.00 - - - 1.00 - - - - - - - - - - - psubw %mm2, %mm2 +# CHECK-NEXT: - - - - - - - - - 5.00 1.00 - - - - - - - - - - - - psubb %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - - - 5.00 1.00 - - - - - - - - - - - - psubd %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - 5.00 - - 1.00 - - - - - - - - - - - - psubq %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - 5.00 - - 1.00 - - - - - - - - - - - - psubw %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - 3.00 - - - 1.00 - - - - - - - - - - - psubsb %mm2, %mm2 +# CHECK-NEXT: - - - - - - - 3.00 - - - 1.00 - - - - - - - - - - - psubsw %mm2, %mm2 +# CHECK-NEXT: - - - - - - - - - 5.00 1.00 - - - - - - - - - - - - psubsb %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - - - 5.00 1.00 - - - - - - - - - - - - psubsw %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - - - 3.00 - 1.00 - - - - - - - - - - - psubusb %mm2, %mm2 +# CHECK-NEXT: - - - - - - - - - 3.00 - 1.00 - - - - - - - - - - - psubusw %mm2, %mm2 +# CHECK-NEXT: - - - - - - - - - 5.00 1.00 - - - - - - - - - - - - psubusb %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - 5.00 - - 1.00 - - - - - - - - - - - - psubusw %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - 4.00 - - - 1.00 - - - - - - - - - - - andnps %xmm0, %xmm0 +# CHECK-NEXT: - - - - - - - 4.00 - - - 1.00 - - - - - - - - - - - andnpd %xmm1, %xmm1 +# CHECK-NEXT: - - - - - - - 3.00 - - - 1.00 - - - - - - - - - - - pandn %mm2, %mm2 +# CHECK-NEXT: - - - - - - - 5.00 - - 1.00 - - - - - - - - - - - - pandn %xmm2, %xmm2 +# CHECK-NEXT: - - - - - - - - - 4.00 - 1.00 - - - - - - - - - - - xorps %xmm0, %xmm0 +# CHECK-NEXT: - - - - - - - - - 4.00 - 1.00 - - - - - - - - - - - xorpd %xmm1, %xmm1 +# CHECK-NEXT: - - - - - - - 3.00 - - 1.00 - - - - - - - - - - - - pxor %mm2, %mm2 +# CHECK-NEXT: - - - - - - - - - 5.00 - 1.00 - - - - - - - - - - - pxor %xmm2, %xmm2 # CHECK: Timeline view: -# CHECK-NEXT: 0123456789 012345678 -# CHECK-NEXT: Index 0123456789 0123456789 +# CHECK-NEXT: 0123456789 0123456789 0123456789 +# CHECK-NEXT: Index 0123456789 0123456789 0123456789 012345 -# CHECK: [0,0] DR . . . . . . . . subl %eax, %eax -# CHECK-NEXT: [0,1] DR . . . . . . . . subq %rax, %rax -# CHECK-NEXT: [0,2] DR . . . . . . . . xorl %eax, %eax -# CHECK-NEXT: [0,3] DR . . . . . . . . xorq %rax, %rax -# CHECK-NEXT: [0,4] .DeeeER . . . . . . . pcmpgtb %mm2, %mm2 -# CHECK-NEXT: [0,5] .D===eeeER. . . . . . . pcmpgtd %mm2, %mm2 -# CHECK-NEXT: [0,6] .D======eeeER . . . . . . pcmpgtw %mm2, %mm2 -# CHECK-NEXT: [0,7] .D----------R . . . . . . pcmpgtb %xmm2, %xmm2 -# CHECK-NEXT: [0,8] . D---------R . . . . . . pcmpgtd %xmm2, %xmm2 -# CHECK-NEXT: [0,9] . D---------R . . . . . . pcmpgtq %xmm2, %xmm2 -# CHECK-NEXT: [0,10] . D---------R . . . . . . pcmpgtw %xmm2, %xmm2 -# CHECK-NEXT: [0,11] . D========eeeER . . . . . psubb %mm2, %mm2 -# CHECK-NEXT: [0,12] . D==========eeeER . . . . . psubd %mm2, %mm2 -# CHECK-NEXT: [0,13] . D=============eeeER . . . . psubq %mm2, %mm2 -# CHECK-NEXT: [0,14] . D================eeeER. . . . psubw %mm2, %mm2 -# CHECK-NEXT: [0,15] . D--------------------R. . . . psubb %xmm2, %xmm2 -# CHECK-NEXT: [0,16] . D-------------------R. . . . psubd %xmm2, %xmm2 -# CHECK-NEXT: [0,17] . D-------------------R. . . . psubq %xmm2, %xmm2 -# CHECK-NEXT: [0,18] . D-------------------R. . . . psubw %xmm2, %xmm2 -# CHECK-NEXT: [0,19] . D==================eeeER . . . psubsb %mm2, %mm2 -# CHECK-NEXT: [0,20] . D====================eeeER . . psubsw %mm2, %mm2 -# CHECK-NEXT: [0,21] . DeE----------------------R . . psubsb %xmm2, %xmm2 -# CHECK-NEXT: [0,22] . D=eE---------------------R . . psubsw %xmm2, %xmm2 -# CHECK-NEXT: [0,23] . D=======================eeeER . . psubusb %mm2, %mm2 -# CHECK-NEXT: [0,24] . .D=========================eeeER . psubusw %mm2, %mm2 -# CHECK-NEXT: [0,25] . .D=eE--------------------------R . psubusb %xmm2, %xmm2 -# CHECK-NEXT: [0,26] . .D==eE-------------------------R . psubusw %xmm2, %xmm2 -# CHECK-NEXT: [0,27] . .D==eE-------------------------R . andnps %xmm0, %xmm0 -# CHECK-NEXT: [0,28] . . D==eE------------------------R . andnpd %xmm1, %xmm1 -# CHECK-NEXT: [0,29] . . D===========================eER. pandn %mm2, %mm2 -# CHECK-NEXT: [0,30] . . D==eE-------------------------R. pandn %xmm2, %xmm2 -# CHECK-NEXT: [0,31] . . D==E--------------------------R. xorps %xmm0, %xmm0 -# CHECK-NEXT: [0,32] . . D==E-------------------------R. xorpd %xmm1, %xmm1 -# CHECK-NEXT: [0,33] . . D===========================eER pxor %mm2, %mm2 -# CHECK-NEXT: [0,34] . . D==E--------------------------R pxor %xmm2, %xmm2 +# CHECK: [0,0] DeeER. . . . . . . . . . . . . subl %eax, %eax +# CHECK-NEXT: [0,1] D==eeER . . . . . . . . . . . . subq %rax, %rax +# CHECK-NEXT: [0,2] D====eeER . . . . . . . . . . . . xorl %eax, %eax +# CHECK-NEXT: [0,3] .D=====eeER . . . . . . . . . . . xorq %rax, %rax +# CHECK-NEXT: [0,4] .DeeE-----R . . . . . . . . . . . pcmpgtb %mm2, %mm2 +# CHECK-NEXT: [0,5] .D===eeE--R . . . . . . . . . . . pcmpgtd %mm2, %mm2 +# CHECK-NEXT: [0,6] . D=====eeER . . . . . . . . . . . pcmpgtw %mm2, %mm2 +# CHECK-NEXT: [0,7] . DeeeE----R . . . . . . . . . . . pcmpgtb %xmm2, %xmm2 +# CHECK-NEXT: [0,8] . D=====eeeER . . . . . . . . . . . pcmpgtd %xmm2, %xmm2 +# CHECK-NEXT: [0,9] . D=======eeeER . . . . . . . . . . pcmpgtq %xmm2, %xmm2 +# CHECK-NEXT: [0,10] . D============eeeER . . . . . . . . . pcmpgtw %xmm2, %xmm2 +# CHECK-NEXT: [0,11] . D=========eeE----R . . . . . . . . . psubb %mm2, %mm2 +# CHECK-NEXT: [0,12] . D===========eeE-R . . . . . . . . . psubd %mm2, %mm2 +# CHECK-NEXT: [0,13] . D==============eeER . . . . . . . . . psubq %mm2, %mm2 +# CHECK-NEXT: [0,14] . D================eeER. . . . . . . . . psubw %mm2, %mm2 +# CHECK-NEXT: [0,15] . D================eeeER . . . . . . . . psubb %xmm2, %xmm2 +# CHECK-NEXT: [0,16] . D=====================eeeER . . . . . . . psubd %xmm2, %xmm2 +# CHECK-NEXT: [0,17] . D========================eeeER. . . . . . . psubq %xmm2, %xmm2 +# CHECK-NEXT: [0,18] . .D============================eeeER. . . . . . psubw %xmm2, %xmm2 +# CHECK-NEXT: [0,19] . .D=================eeE------------R. . . . . . psubsb %mm2, %mm2 +# CHECK-NEXT: [0,20] . .D====================eeE---------R. . . . . . psubsw %mm2, %mm2 +# CHECK-NEXT: [0,21] . . D==============================eeeER . . . . . psubsb %xmm2, %xmm2 +# CHECK-NEXT: [0,22] . . D===================================eeeER . . . . psubsw %xmm2, %xmm2 +# CHECK-NEXT: [0,23] . . D========================eeE------------R . . . . psubusb %mm2, %mm2 +# CHECK-NEXT: [0,24] . . D==========================eeE---------R . . . . psubusw %mm2, %mm2 +# CHECK-NEXT: [0,25] . . D=======================================eeeER . . . psubusb %xmm2, %xmm2 +# CHECK-NEXT: [0,26] . . D==========================================eeeER . . psubusw %xmm2, %xmm2 +# CHECK-NEXT: [0,27] . . D==============================eeE------------R . . andnps %xmm0, %xmm0 +# CHECK-NEXT: [0,28] . . D==================================eeE--------R . . andnpd %xmm1, %xmm1 +# CHECK-NEXT: [0,29] . . D======================================eeE-----R . . pandn %mm2, %mm2 +# CHECK-NEXT: [0,30] . . D=============================================eeeER . pandn %xmm2, %xmm2 +# CHECK-NEXT: [0,31] . . D==========================================eeE----R . xorps %xmm0, %xmm0 +# CHECK-NEXT: [0,32] . . D==============================================eeER . xorpd %xmm1, %xmm1 +# CHECK-NEXT: [0,33] . . .D=================================================eeER. pxor %mm2, %mm2 +# CHECK-NEXT: [0,34] . . .D=================================================eeeER pxor %xmm2, %xmm2 # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions @@ -205,38 +230,38 @@ # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] -# CHECK-NEXT: 0. 1 0.0 0.0 0.0 subl %eax, %eax -# CHECK-NEXT: 1. 1 0.0 0.0 0.0 subq %rax, %rax -# CHECK-NEXT: 2. 1 0.0 0.0 0.0 xorl %eax, %eax -# CHECK-NEXT: 3. 1 0.0 0.0 0.0 xorq %rax, %rax -# CHECK-NEXT: 4. 1 1.0 1.0 0.0 pcmpgtb %mm2, %mm2 -# CHECK-NEXT: 5. 1 4.0 0.0 0.0 pcmpgtd %mm2, %mm2 -# CHECK-NEXT: 6. 1 7.0 0.0 0.0 pcmpgtw %mm2, %mm2 -# CHECK-NEXT: 7. 1 0.0 0.0 10.0 pcmpgtb %xmm2, %xmm2 -# CHECK-NEXT: 8. 1 0.0 0.0 9.0 pcmpgtd %xmm2, %xmm2 -# CHECK-NEXT: 9. 1 0.0 0.0 9.0 pcmpgtq %xmm2, %xmm2 -# CHECK-NEXT: 10. 1 0.0 0.0 9.0 pcmpgtw %xmm2, %xmm2 -# CHECK-NEXT: 11. 1 9.0 0.0 0.0 psubb %mm2, %mm2 -# CHECK-NEXT: 12. 1 11.0 0.0 0.0 psubd %mm2, %mm2 -# CHECK-NEXT: 13. 1 14.0 0.0 0.0 psubq %mm2, %mm2 +# CHECK-NEXT: 0. 1 1.0 1.0 0.0 subl %eax, %eax +# CHECK-NEXT: 1. 1 3.0 0.0 0.0 subq %rax, %rax +# CHECK-NEXT: 2. 1 5.0 0.0 0.0 xorl %eax, %eax +# CHECK-NEXT: 3. 1 6.0 0.0 0.0 xorq %rax, %rax +# CHECK-NEXT: 4. 1 1.0 1.0 5.0 pcmpgtb %mm2, %mm2 +# CHECK-NEXT: 5. 1 4.0 1.0 2.0 pcmpgtd %mm2, %mm2 +# CHECK-NEXT: 6. 1 6.0 1.0 0.0 pcmpgtw %mm2, %mm2 +# CHECK-NEXT: 7. 1 1.0 1.0 4.0 pcmpgtb %xmm2, %xmm2 +# CHECK-NEXT: 8. 1 6.0 2.0 0.0 pcmpgtd %xmm2, %xmm2 +# CHECK-NEXT: 9. 1 8.0 0.0 0.0 pcmpgtq %xmm2, %xmm2 +# CHECK-NEXT: 10. 1 13.0 2.0 0.0 pcmpgtw %xmm2, %xmm2 +# CHECK-NEXT: 11. 1 10.0 3.0 4.0 psubb %mm2, %mm2 +# CHECK-NEXT: 12. 1 12.0 1.0 1.0 psubd %mm2, %mm2 +# CHECK-NEXT: 13. 1 15.0 1.0 0.0 psubq %mm2, %mm2 # CHECK-NEXT: 14. 1 17.0 0.0 0.0 psubw %mm2, %mm2 -# CHECK-NEXT: 15. 1 0.0 0.0 20.0 psubb %xmm2, %xmm2 -# CHECK-NEXT: 16. 1 0.0 0.0 19.0 psubd %xmm2, %xmm2 -# CHECK-NEXT: 17. 1 0.0 0.0 19.0 psubq %xmm2, %xmm2 -# CHECK-NEXT: 18. 1 0.0 0.0 19.0 psubw %xmm2, %xmm2 -# CHECK-NEXT: 19. 1 19.0 0.0 0.0 psubsb %mm2, %mm2 -# CHECK-NEXT: 20. 1 21.0 0.0 0.0 psubsw %mm2, %mm2 -# CHECK-NEXT: 21. 1 1.0 1.0 22.0 psubsb %xmm2, %xmm2 -# CHECK-NEXT: 22. 1 2.0 0.0 21.0 psubsw %xmm2, %xmm2 -# CHECK-NEXT: 23. 1 24.0 0.0 0.0 psubusb %mm2, %mm2 -# CHECK-NEXT: 24. 1 26.0 0.0 0.0 psubusw %mm2, %mm2 -# CHECK-NEXT: 25. 1 2.0 0.0 26.0 psubusb %xmm2, %xmm2 -# CHECK-NEXT: 26. 1 3.0 0.0 25.0 psubusw %xmm2, %xmm2 -# CHECK-NEXT: 27. 1 3.0 3.0 25.0 andnps %xmm0, %xmm0 -# CHECK-NEXT: 28. 1 3.0 3.0 24.0 andnpd %xmm1, %xmm1 -# CHECK-NEXT: 29. 1 28.0 0.0 0.0 pandn %mm2, %mm2 -# CHECK-NEXT: 30. 1 3.0 0.0 25.0 pandn %xmm2, %xmm2 -# CHECK-NEXT: 31. 1 3.0 0.0 26.0 xorps %xmm0, %xmm0 -# CHECK-NEXT: 32. 1 3.0 0.0 25.0 xorpd %xmm1, %xmm1 -# CHECK-NEXT: 33. 1 28.0 0.0 0.0 pxor %mm2, %mm2 -# CHECK-NEXT: 34. 1 3.0 0.0 26.0 pxor %xmm2, %xmm2 +# CHECK-NEXT: 15. 1 17.0 3.0 0.0 psubb %xmm2, %xmm2 +# CHECK-NEXT: 16. 1 22.0 2.0 0.0 psubd %xmm2, %xmm2 +# CHECK-NEXT: 17. 1 25.0 0.0 0.0 psubq %xmm2, %xmm2 +# CHECK-NEXT: 18. 1 29.0 2.0 0.0 psubw %xmm2, %xmm2 +# CHECK-NEXT: 19. 1 18.0 1.0 12.0 psubsb %mm2, %mm2 +# CHECK-NEXT: 20. 1 21.0 1.0 9.0 psubsw %mm2, %mm2 +# CHECK-NEXT: 21. 1 31.0 0.0 0.0 psubsb %xmm2, %xmm2 +# CHECK-NEXT: 22. 1 36.0 2.0 0.0 psubsw %xmm2, %xmm2 +# CHECK-NEXT: 23. 1 25.0 3.0 12.0 psubusb %mm2, %mm2 +# CHECK-NEXT: 24. 1 27.0 1.0 9.0 psubusw %mm2, %mm2 +# CHECK-NEXT: 25. 1 40.0 2.0 0.0 psubusb %xmm2, %xmm2 +# CHECK-NEXT: 26. 1 43.0 0.0 0.0 psubusw %xmm2, %xmm2 +# CHECK-NEXT: 27. 1 31.0 31.0 12.0 andnps %xmm0, %xmm0 +# CHECK-NEXT: 28. 1 35.0 35.0 8.0 andnpd %xmm1, %xmm1 +# CHECK-NEXT: 29. 1 39.0 11.0 5.0 pandn %mm2, %mm2 +# CHECK-NEXT: 30. 1 46.0 2.0 0.0 pandn %xmm2, %xmm2 +# CHECK-NEXT: 31. 1 43.0 11.0 4.0 xorps %xmm0, %xmm0 +# CHECK-NEXT: 32. 1 47.0 11.0 0.0 xorpd %xmm1, %xmm1 +# CHECK-NEXT: 33. 1 50.0 11.0 0.0 pxor %mm2, %mm2 +# CHECK-NEXT: 34. 1 50.0 2.0 0.0 pxor %xmm2, %xmm2 diff --git a/llvm/test/tools/llvm-mca/X86/cpus.s b/llvm/test/tools/llvm-mca/X86/cpus.s --- a/llvm/test/tools/llvm-mca/X86/cpus.s +++ b/llvm/test/tools/llvm-mca/X86/cpus.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -resource-pressure=false -instruction-info=false < %s | FileCheck --check-prefix=ALL --check-prefix=BARCELONA %s +# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=barcelona -resource-pressure=false -instruction-info=false < %s | FileCheck --check-prefix=ALL --check-prefix=BARCELONA %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -resource-pressure=false -instruction-info=false < %s | FileCheck --check-prefix=ALL --check-prefix=BDVER2 %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=btver2 -resource-pressure=false -instruction-info=false < %s | FileCheck --check-prefix=ALL --check-prefix=BTVER2 %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=znver1 -resource-pressure=false -instruction-info=false < %s | FileCheck --check-prefix=ALL --check-prefix=ZNVER1 %s @@ -16,13 +16,26 @@ # ALL: Iterations: 100 # ALL-NEXT: Instructions: 100 -# ALL-NEXT: Total Cycles: 103 + +# BARCELONA-NEXT: Total Cycles: 203 +# BDVER2-NEXT: Total Cycles: 103 +# BROADWELL-NEXT: Total Cycles: 103 +# BTVER2-NEXT: Total Cycles: 103 +# HASWELL-NEXT: Total Cycles: 103 +# IVYBRIDGE-NEXT: Total Cycles: 103 +# KNL-NEXT: Total Cycles: 103 +# SANDYBRIDGE-NEXT: Total Cycles: 103 +# SKX-NEXT: Total Cycles: 103 +# SKX-AVX512-NEXT: Total Cycles: 103 +# SLM-NEXT: Total Cycles: 103 +# ZNVER1-NEXT: Total Cycles: 103 + # ALL-NEXT: Total uOps: 100 -# BARCELONA: Dispatch Width: 4 -# BARCELONA-NEXT: uOps Per Cycle: 0.97 -# BARCELONA-NEXT: IPC: 0.97 -# BARCELONA-NEXT: Block RThroughput: 0.3 +# BARCELONA: Dispatch Width: 3 +# BARCELONA-NEXT: uOps Per Cycle: 0.49 +# BARCELONA-NEXT: IPC: 0.49 +# BARCELONA-NEXT: Block RThroughput: 1.0 # BDVER2: Dispatch Width: 4 # BDVER2-NEXT: uOps Per Cycle: 0.97 diff --git a/llvm/test/tools/llvm-mca/X86/read-after-ld-1.s b/llvm/test/tools/llvm-mca/X86/read-after-ld-1.s --- a/llvm/test/tools/llvm-mca/X86/read-after-ld-1.s +++ b/llvm/test/tools/llvm-mca/X86/read-after-ld-1.s @@ -3,7 +3,7 @@ # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=HASWELL # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=broadwell -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=BDWELL # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=skylake -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=SKYLAKE -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=BARCELONA +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=BARCELONA # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=BDVER2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=BTVER2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -resource-pressure=false -instruction-info=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=ZNVER1 @@ -14,8 +14,8 @@ # ALL: Iterations: 1 # ALL-NEXT: Instructions: 2 -# BARCELONA-NEXT: Total Cycles: 20 -# BARCELONA-NEXT: Total uOps: 3 +# BARCELONA-NEXT: Total Cycles: 25 +# BARCELONA-NEXT: Total uOps: 2 # BDVER2-NEXT: Total Cycles: 17 # BDVER2-NEXT: Total uOps: 2 @@ -38,10 +38,10 @@ # ZNVER1-NEXT: Total Cycles: 20 # ZNVER1-NEXT: Total uOps: 2 -# BARCELONA: Dispatch Width: 4 -# BARCELONA-NEXT: uOps Per Cycle: 0.15 -# BARCELONA-NEXT: IPC: 0.10 -# BARCELONA-NEXT: Block RThroughput: 14.0 +# BARCELONA: Dispatch Width: 3 +# BARCELONA-NEXT: uOps Per Cycle: 0.08 +# BARCELONA-NEXT: IPC: 0.08 +# BARCELONA-NEXT: Block RThroughput: 15.0 # BDVER2: Dispatch Width: 4 # BDVER2-NEXT: uOps Per Cycle: 0.12 @@ -81,7 +81,7 @@ # ALL: Timeline view: # BARCELONA-NEXT: 0123456789 -# BARCELONA-NEXT: Index 0123456789 +# BARCELONA-NEXT: Index 0123456789 01234 # BDVER2-NEXT: 0123456 # BDVER2-NEXT: Index 0123456789 @@ -104,8 +104,8 @@ # ZNVER1-NEXT: 0123456789 # ZNVER1-NEXT: Index 0123456789 -# BARCELONA: [0,0] DeeeeeeeeeeeeeeER . vdivps %xmm0, %xmm1, %xmm1 -# BARCELONA-NEXT: [0,1] D========eeeeeeeeeER vaddps (%rax), %xmm1, %xmm1 +# BARCELONA: [0,0] DeeeeeeeeeeeeeeeeeeER . vdivps %xmm0, %xmm1, %xmm1 +# BARCELONA-NEXT: [0,1] D================eeeeeeER vaddps (%rax), %xmm1, %xmm1 # BDVER2: [0,0] DeeeeeeeeeER .. vdivps %xmm0, %xmm1, %xmm1 # BDVER2-NEXT: [0,1] D====eeeeeeeeeeER vaddps (%rax), %xmm1, %xmm1 @@ -137,7 +137,7 @@ # ALL: [0] [1] [2] [3] # ALL-NEXT: 0. 1 1.0 1.0 0.0 vdivps %xmm0, %xmm1, %xmm1 -# BARCELONA-NEXT: 1. 1 9.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1 +# BARCELONA-NEXT: 1. 1 17.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1 # BDVER2-NEXT: 1. 1 5.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1 # BDWELL-NEXT: 1. 1 7.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1 # BTVER2-NEXT: 1. 1 15.0 0.0 0.0 vaddps (%rax), %xmm1, %xmm1 diff --git a/llvm/test/tools/llvm-mca/X86/register-file-statistics.s b/llvm/test/tools/llvm-mca/X86/register-file-statistics.s --- a/llvm/test/tools/llvm-mca/X86/register-file-statistics.s +++ b/llvm/test/tools/llvm-mca/X86/register-file-statistics.s @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL %s -# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=BARCELONA %s +# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=barcelona -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL,BARCELONA %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL,BDVER2 %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL,BTVER2 %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -all-stats=false -all-views=false -register-file-stats < %s | FileCheck --check-prefixes=ALL,ZNVER1 %s @@ -19,9 +19,10 @@ # ALL-NEXT: Total number of mappings created: 2 # ALL-NEXT: Max number of mappings used: 2 -# BARCELONA: Register File statistics: -# BARCELONA-NEXT: Total number of mappings created: 2 -# BARCELONA-NEXT: Max number of mappings used: 2 +# BARCELONA: * Register File #1 -- BnFpuPRF: +# BARCELONA-NEXT: Number of physical registers: 120 +# BARCELONA-NEXT: Total number of mappings created: 0 +# BARCELONA-NEXT: Max number of mappings used: 0 # BDVER2: * Register File #1 -- PdFpuPRF: # BDVER2-NEXT: Number of physical registers: 160 @@ -38,6 +39,11 @@ # ZNVER1-NEXT: Total number of mappings created: 0 # ZNVER1-NEXT: Max number of mappings used: 0 +# BARCELONA: * Register File #2 -- BnIntPRF: +# BARCELONA-NEXT: Number of physical registers: 40 +# BARCELONA-NEXT: Total number of mappings created: 2 +# BARCELONA-NEXT: Max number of mappings used: 2 + # BDVER2: * Register File #2 -- PdIntegerPRF: # BDVER2-NEXT: Number of physical registers: 96 # BDVER2-NEXT: Total number of mappings created: 2 diff --git a/llvm/test/tools/llvm-mca/X86/scheduler-queue-usage.s b/llvm/test/tools/llvm-mca/X86/scheduler-queue-usage.s --- a/llvm/test/tools/llvm-mca/X86/scheduler-queue-usage.s +++ b/llvm/test/tools/llvm-mca/X86/scheduler-queue-usage.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,BARCELONA %s +# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=barcelona -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,BARCELONA %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,BDVER2 %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,BTVER2 %s # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,ZNVER1 %s @@ -16,8 +16,42 @@ # ALL: Schedulers - number of cycles where we saw N micro opcodes issued: # ALL-NEXT: [# issued], [# cycles] -# ALL-NEXT: 0, 3 (75.0%) -# ALL-NEXT: 1, 1 (25.0%) + +# BARCELONA-NEXT: 0, 4 (80.0%) +# BARCELONA-NEXT: 1, 1 (20.0%) + +# BDVER2-NEXT: 0, 3 (75.0%) +# BDVER2-NEXT: 1, 1 (25.0%) + +# BDW-NEXT: 0, 3 (75.0%) +# BDW-NEXT: 1, 1 (25.0%) + +# BTVER2-NEXT: 0, 3 (75.0%) +# BTVER2-NEXT: 1, 1 (25.0%) + +# HSW-NEXT: 0, 3 (75.0%) +# HSW-NEXT: 1, 1 (25.0%) + +# IVB-NEXT: 0, 3 (75.0%) +# IVB-NEXT: 1, 1 (25.0%) + +# KNL-NEXT: 0, 3 (75.0%) +# KNL-NEXT: 1, 1 (25.0%) + +# SKX-NEXT: 0, 3 (75.0%) +# SKX-NEXT: 1, 1 (25.0%) + +# SKX-AVX512-NEXT: 0, 3 (75.0%) +# SKX-AVX512-NEXT: 1, 1 (25.0%) + +# SLM-NEXT: 0, 3 (75.0%) +# SLM-NEXT: 1, 1 (25.0%) + +# SNB-NEXT: 0, 3 (75.0%) +# SNB-NEXT: 1, 1 (25.0%) + +# ZNVER1-NEXT: 0, 3 (75.0%) +# ZNVER1-NEXT: 1, 1 (25.0%) # BARCELONA: Scheduler's queue usage: # BARCELONA-NEXT: [1] Resource name. @@ -89,7 +123,10 @@ # ZNVER1-NEXT: [4] Total number of buffer entries. # BARCELONA: [1] [2] [3] [4] -# BARCELONA-NEXT: SBPortAny 0 1 54 +# BARCELONA-NEXT: BnFPU 0 0 36 +# BARCELONA-NEXT: BnInt 0 1 24 +# BARCELONA-NEXT: BnLoad 0 0 12 +# BARCELONA-NEXT: BnStore 0 0 32 # BDVER2: [1] [2] [3] [4] # BDVER2-NEXT: PdEX 0 1 40 diff --git a/llvm/test/tools/llvm-mca/X86/sqrt-rsqrt-rcp-memop.s b/llvm/test/tools/llvm-mca/X86/sqrt-rsqrt-rcp-memop.s --- a/llvm/test/tools/llvm-mca/X86/sqrt-rsqrt-rcp-memop.s +++ b/llvm/test/tools/llvm-mca/X86/sqrt-rsqrt-rcp-memop.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -iterations=1 -all-views=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=BARCELONA +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=barcelona -iterations=1 -all-views=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=BARCELONA # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1 -all-views=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=BDVER2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -all-views=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=BTVER2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -all-views=false -timeline < %s | FileCheck %s -check-prefix=ALL -check-prefix=ZNVER1 @@ -32,7 +32,7 @@ # ALL: Timeline view: # BARCELONA-NEXT: 0123456789 -# BARCELONA-NEXT: Index 0123456789 0123 +# BARCELONA-NEXT: Index 0123456789 01234 # BDVER2-NEXT: 01234567 # BDVER2-NEXT: Index 0123456789 @@ -52,8 +52,8 @@ # ZNVER1-NEXT: 0123456789 0 # ZNVER1-NEXT: Index 0123456789 0123456789 -# BARCELONA: [0,0] DeER . . . . . leaq 8(%rsp,%rdi,2), %rax -# BARCELONA-NEXT: [0,1] D=eeeeeeeeeeeeeeeeeeeeER sqrtss (%rax), %xmm1 +# BARCELONA: [0,0] DeER . . . . . leaq 8(%rsp,%rdi,2), %rax +# BARCELONA-NEXT: [0,1] D=eeeeeeeeeeeeeeeeeeeeeER sqrtss (%rax), %xmm1 # BDVER2: [0,0] DeER . . . . leaq 8(%rsp,%rdi,2), %rax # BDVER2-NEXT: [0,1] D=eeeeeeeeeeeeeeER sqrtss (%rax), %xmm1 @@ -94,7 +94,7 @@ # ALL: Timeline view: -# BARCELONA-NEXT: 0123456789 0 +# BARCELONA-NEXT: 0123456789 012 # BARCELONA-NEXT: Index 0123456789 0123456789 # BDVER2-NEXT: 01234567 @@ -115,8 +115,8 @@ # ZNVER1-NEXT: 0123456789 0 # ZNVER1-NEXT: Index 0123456789 0123456789 -# BARCELONA: [0,0] DeER . . . . . . leaq 8(%rsp,%rdi,2), %rax -# BARCELONA-NEXT: [0,1] D=eeeeeeeeeeeeeeeeeeeeeeeeeeeER sqrtsd (%rax), %xmm1 +# BARCELONA: [0,0] DeER . . . . . . . leaq 8(%rsp,%rdi,2), %rax +# BARCELONA-NEXT: [0,1] D=eeeeeeeeeeeeeeeeeeeeeeeeeeeeeER sqrtsd (%rax), %xmm1 # BDVER2: [0,0] DeER . . . . leaq 8(%rsp,%rdi,2), %rax # BDVER2-NEXT: [0,1] D=eeeeeeeeeeeeeeER sqrtsd (%rax), %xmm1 @@ -155,20 +155,35 @@ # ALL: [2] Code Region - test_rsqrtss -# ALL: Timeline view: +# BARCELONA: Timeline view: +# BARCELONA-NEXT: Index 012345678 -# BARCELONA-NEXT: 01234 +# BDVER2: Timeline view: # BDVER2-NEXT: 0123 +# BDVER2-NEXT: Index 0123456789 + +# BROADWELL: Timeline view: # BROADWELL-NEXT: 0123 +# BROADWELL-NEXT: Index 0123456789 + +# BTVER2: Timeline view: # BTVER2-NEXT: 01 +# BTVER2-NEXT: Index 0123456789 + +# HASWELL: Timeline view: # HASWELL-NEXT: 0123 +# HASWELL-NEXT: Index 0123456789 + +# SKYLAKE: Timeline view: # SKYLAKE-NEXT: 012 +# SKYLAKE-NEXT: Index 0123456789 + +# ZNVER1: Timeline view: # ZNVER1-NEXT: 012345 +# ZNVER1-NEXT: Index 0123456789 -# ALL-NEXT: Index 0123456789 - -# BARCELONA: [0,0] DeER . . . leaq 8(%rsp,%rdi,2), %rax -# BARCELONA-NEXT: [0,1] D=eeeeeeeeeeeER rsqrtss (%rax), %xmm1 +# BARCELONA: [0,0] DeER . . leaq 8(%rsp,%rdi,2), %rax +# BARCELONA-NEXT: [0,1] D=eeeeeER rsqrtss (%rax), %xmm1 # BDVER2: [0,0] DeER . . . leaq 8(%rsp,%rdi,2), %rax # BDVER2-NEXT: [0,1] D=eeeeeeeeeeER rsqrtss (%rax), %xmm1 @@ -207,20 +222,35 @@ # ALL: [3] Code Region - test_rcp -# ALL: Timeline view: +# BARCELONA: Timeline view: +# BARCELONA-NEXT: Index 012345678 -# BARCELONA-NEXT: 01234 +# BDVER2: Timeline view: # BDVER2-NEXT: 0123 +# BDVER2-NEXT: Index 0123456789 + +# BROADWELL: Timeline view: # BROADWELL-NEXT: 0123 +# BROADWELL-NEXT: Index 0123456789 + +# BTVER2: Timeline view: # BTVER2-NEXT: 01 +# BTVER2-NEXT: Index 0123456789 + +# HASWELL: Timeline view: # HASWELL-NEXT: 0123 +# HASWELL-NEXT: Index 0123456789 + +# SKYLAKE: Timeline view: # SKYLAKE-NEXT: 012 +# SKYLAKE-NEXT: Index 0123456789 + +# ZNVER1: Timeline view: # ZNVER1-NEXT: 012345 +# ZNVER1-NEXT: Index 0123456789 -# ALL-NEXT: Index 0123456789 - -# BARCELONA: [0,0] DeER . . . leaq 8(%rsp,%rdi,2), %rax -# BARCELONA-NEXT: [0,1] D=eeeeeeeeeeeER rcpss (%rax), %xmm1 +# BARCELONA: [0,0] DeER . . leaq 8(%rsp,%rdi,2), %rax +# BARCELONA-NEXT: [0,1] D=eeeeeER rcpss (%rax), %xmm1 # BDVER2: [0,0] DeER . . . leaq 8(%rsp,%rdi,2), %rax # BDVER2-NEXT: [0,1] D=eeeeeeeeeeER rcpss (%rax), %xmm1