Index: /home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/vsx-args.ll
===================================================================
--- /home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/vsx-args.ll
+++ /home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/vsx-args.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx | FileCheck %s
+; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx -fast-isel | FileCheck %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
Index: /home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/vsx-fma-m.ll
===================================================================
--- /home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/vsx-fma-m.ll
+++ /home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/vsx-fma-m.ll
@@ -3,6 +3,7 @@
 ; Also run with -schedule-ppc-vsx-fma-mutation-early as a stress test for the
 ; live-interval-updating logic.
 ; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx -schedule-ppc-vsx-fma-mutation-early
+; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx -fast-isel -schedule-ppc-vsx-fma-mutation-early
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
Index: /home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/vsx-p8.ll
===================================================================
--- /home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/vsx-p8.ll
+++ /home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/vsx-p8.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -mcpu=pwr8 -mattr=+power8-vector < %s | FileCheck %s
+; RUN: llc -mcpu=pwr8 -mattr=+power8-vector -fast-isel < %s | FileCheck %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
Index: /home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/vsx-self-copy.ll
===================================================================
--- /home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/vsx-self-copy.ll
+++ /home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/vsx-self-copy.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel < %s | FileCheck %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
Index: /home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/vsx-spill.ll
===================================================================
--- /home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/vsx-spill.ll
+++ /home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/vsx-spill.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel < %s | FileCheck %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
Index: /home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/vsx.ll
===================================================================
--- /home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/vsx.ll
+++ /home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/vsx.ll
@@ -1,4 +1,7 @@
 ; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-REG %s
+; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel < %s | FileCheck -check-prefix=CHECK-FISL %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
@@ -171,9 +174,15 @@
   %v = and <4 x i32> %a, %w
   ret <4 x i32> %v
 
-; CHECK-LABEL: @test17
-; CHECK: xxlandc 34, 34, 35
-; CHECK: blr
+; CHECK-REG-LABEL: @test17
+; CHECK-REG: xxlandc 34, 34, 35
+; CHECK-REG: blr
+
+; CHECK-FISL-LABEL: @test17
+; CHECK-FISL: vspltisb 4, -1
+; CHECK-FISL: xxlxor 35, 35, 36
+; CHECK-FISL: xxland 34, 34, 35
+; CHECK-FISL: blr
 }
 
 define <8 x i16> @test18(<8 x i16> %a, <8 x i16> %b) {
@@ -687,15 +696,22 @@
   %i = add <2 x i32> %b2, <i32 2, i32 3>
   ret <2 x i32> %i
 
-; CHECK-LABEL: @test80
-; CHECK-DAG: addi [[R1:[0-9]+]], 3, 3
-; CHECK-DAG: addi [[R2:[0-9]+]], 1, -16
-; CHECK-DAG: addi [[R3:[0-9]+]], 3, 2
-; CHECK: std [[R1]], -8(1)
-; CHECK: std [[R3]], -16(1)
-; CHECK: lxvd2x 34, 0, [[R2]]
-; CHECK-NOT: stxvd2x
-; CHECK: blr
+; CHECK-REG-LABEL: @test80
+; CHECK-REG-DAG: addi [[R1:[0-9]+]], 3, 3
+; CHECK-REG-DAG: addi [[R2:[0-9]+]], 1, -16
+; CHECK-REG-DAG: addi [[R3:[0-9]+]], 3, 2
+; CHECK-REG: std [[R1]], -8(1)
+; CHECK-REG: std [[R3]], -16(1)
+; CHECK-REG: lxvd2x 34, 0, [[R2]]
+; CHECK-REG-NOT: stxvd2x
+; CHECK-REG: blr
+
+; CHECK-FISL-LABEL: @test80
+; CHECK-FISL: lxvw4x 34, 0, 11
+; CHECK-FISL: vmrghw 2, 2, 2
+; CHECK-FISL: xxpermdi 34, 34, 34, 0
+; CHECK-FISL: stxvd2x 34, 0, 3
+; CHECK-FISL: lxvd2x 34, 0, 12
 }
 
 define <2 x double> @test81(<4 x float> %b) {