Fix ARM's add->adr translations for expressions

[joerg]

Summary

When transforming non-immediates from the PC-argument form of add to adr, PC needs to get added as expression base. At the same time, the magic offset 8 has to be specified too, otherwise the computed immediate is off.

[grosbach]

Seems reasonable to me, but Tim will definitely have a better eye for the details than I.

[t.p.northover]

Hi Joerg,

I've convinced myself that it's probably for the best (a little concerned by the isImm() divergence, but it's certainly arguably the best option).

But I think the calculation & comment could be improved slightly:

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

6489–6490

This is slightly deeper than a fixup compensation, which suggests it's an LLVM implementation-detail.

The +8 is there because for historical reasons whenever you read PC as a register in ARM mode you get "PC of start of current instruction + 8", but that's not what '.' means. So "lbl - (. + 8)" really is what you write to get the address of lbl in an add. The code is perhaps more naturally represented as:

const MCExpr *InstPC = MCSymbolRefExpr::Create(Sym, ...);
[...]
const MCExpr *ReadPC = MCBinaryExpr::CreateAdd(InstPC, Const8);
const MCExpr *FixupAddr = MCBinaryExpr::CreateAdd(ReadPC, OpExpr);

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

#include "ARMGenAsmMatcher.inc"
   OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
                                        SMLoc &EndLoc);
 
   // Asm Match Converter Methods
   void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
   void cvtThumbBranches(MCInst &Inst, const OperandVector &);
 
   bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
-  bool processInstruction(MCInst &Inst, const OperandVector &Ops);
+  bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
   bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
   bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
 
 public:
   enum ARMMatchResultTy {
     Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
     Match_RequiresNotITBlock,
     Match_RequiresV6,
static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
   case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
   case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
   case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
   case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
   }
 }
 
 bool ARMAsmParser::processInstruction(MCInst &Inst,
-                                      const OperandVector &Operands) {
+                                      const OperandVector &Operands,
+                                      MCStreamer &Out) {
   switch (Inst.getOpcode()) {
   // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
   case ARM::LDRT_POST:
   case ARM::LDRBT_POST: {
     const unsigned Opcode =
       (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
                                            : ARM::LDRBT_POST_IMM;
     MCInst TmpInst;
case ARM::STRBT_POST: {
     TmpInst.addOperand(Inst.getOperand(2));
     TmpInst.addOperand(Inst.getOperand(3));
     Inst = TmpInst;
     return true;
   }
   // Alias for alternate form of 'ADR Rd, #imm' instruction.
   case ARM::ADDri: {
     if (Inst.getOperand(1).getReg() != ARM::PC ||
-        Inst.getOperand(5).getReg() != 0)
+        Inst.getOperand(5).getReg() != 0 ||
+        !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm()))
       return false;
     MCInst TmpInst;
     TmpInst.setOpcode(ARM::ADR);
     TmpInst.addOperand(Inst.getOperand(0));
+    if (Inst.getOperand(2).isImm()) {
       TmpInst.addOperand(Inst.getOperand(2));
+    } else {
+      // Turn PC-relative expression into absolute expression.
+      // Special care is needed to compensate for the implicit addition
+      // of 8 Bytes for fixup_arm_adr_pcrel_12.
+      MCSymbol *Sym = getContext().CreateTempSymbol();
+      Out.EmitLabel(Sym);
+      const MCExpr *OpExpr = Inst.getOperand(2).getExpr();
+      const MCExpr *PCRel = MCSymbolRefExpr::Create(Sym,
+                                                    MCSymbolRefExpr::VK_None,
+                                                    getContext());
+      const MCExpr *Const8 = MCConstantExpr::Create(8, getContext());
+      const MCExpr *Addr = MCBinaryExpr::CreateAdd(PCRel, OpExpr,
+                                                   getContext());
+      const MCExpr *FixupAddr = MCBinaryExpr::CreateAdd(Const8, Addr,
+                                                        getContext());
+      TmpInst.addOperand(MCOperand::CreateExpr(FixupAddr));
+    }
     TmpInst.addOperand(Inst.getOperand(3));
     TmpInst.addOperand(Inst.getOperand(4));
     Inst = TmpInst;
     return true;
   }
   // Aliases for alternate PC+imm syntax of LDR instructions.
   case ARM::t2LDRpcrel:
     // Select the narrow version if the immediate will fit.
case Match_Success:
 
     { // processInstruction() updates inITBlock state, we need to save it away
       bool wasInITBlock = inITBlock();
 
       // Some instructions need post-processing to, for example, tweak which
       // encoding is selected. Loop on it while changes happen so the
       // individual transformations can chain off each other. E.g.,
       // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
-      while (processInstruction(Inst, Operands))
+      while (processInstruction(Inst, Operands, Out))
         ;
 
       // Only after the instruction is fully processed, we can validate it
       if (wasInITBlock && hasV8Ops() && isThumb() &&
           !isV8EligibleForIT(&Inst)) {
         Warning(IDLoc, "deprecated instruction in IT block");
       }
     }

test/MC/ARM/basic-arm-instructions.s

@------------------------------------------------------------------------------
         add r6, r7, lsl r9
         add r6, r7, lsr r9
         add r6, r7, asr r9
         add r6, r7, ror r9
         add r4, r5, rrx
 
   add r0, #-4
   add r4, r5, #-21
-        add r0, pc, #0xc0000000
+  add r0, pc, #0xc0000000
 
+  add r0, pc, #(Lback - .)
+
 @ CHECK: add  r4, r5, #61440          @ encoding: [0x0f,0x4a,0x85,0xe2]
 @ CHECK: add  r4, r5, r6              @ encoding: [0x06,0x40,0x85,0xe0]
 @ CHECK: add  r4, r5, r6, lsl #5      @ encoding: [0x86,0x42,0x85,0xe0]
 @ CHECK: add  r4, r5, r6, lsr #5      @ encoding: [0xa6,0x42,0x85,0xe0]
 @ CHECK: add  r4, r5, r6, lsr #5      @ encoding: [0xa6,0x42,0x85,0xe0]
 @ CHECK: add  r4, r5, r6, asr #5      @ encoding: [0xc6,0x42,0x85,0xe0]
 @ CHECK: add  r4, r5, r6, ror #5      @ encoding: [0xe6,0x42,0x85,0xe0]
 @ CHECK: add  r6, r7, r8, lsl r9      @ encoding: [0x18,0x69,0x87,0xe0]

 @ CHECK: add  r6, r6, r7, lsl r9      @ encoding: [0x17,0x69,0x86,0xe0]
 @ CHECK: add  r6, r6, r7, lsr r9      @ encoding: [0x37,0x69,0x86,0xe0]
 @ CHECK: add  r6, r6, r7, asr r9      @ encoding: [0x57,0x69,0x86,0xe0]
 @ CHECK: add  r6, r6, r7, ror r9      @ encoding: [0x77,0x69,0x86,0xe0]
 @ CHECK: add  r4, r4, r5, rrx         @ encoding: [0x65,0x40,0x84,0xe0]
 
 @ CHECK: sub  r0, r0, #4              @ encoding: [0x04,0x00,0x40,0xe2]
 @ CHECK: sub  r4, r5, #21             @ encoding: [0x15,0x40,0x45,0xe2]
-@ CHECK: adr    r0, #-1073741824        @ encoding: [0x03,0x01,0x8f,0xe2]
+@ CHECK: adr  r0, #-1073741824        @ encoding: [0x03,0x01,0x8f,0xe2]
+@ CHECK:        Ltmp0:
+@ CHECK-NEXT:   Ltmp1:
+@ CHECK-NEXT:   adr  r0, 8+(Ltmp1+(Lback-Ltmp0)) @ encoding: [A,A,0x0f'A',0xe2'A']
+@ CHECK-NEXT:                           @   fixup A - offset: 0, value: 8+(Ltmp1+(Lback-Ltmp0)), kind: fixup_arm_adr_pcrel_12
 
     @ Test right shift by 32, which is encoded as 0
     add r3, r1, r2, lsr #32
     add r3, r1, r2, asr #32
 @ CHECK: add  r3, r1, r2, lsr #32     @ encoding: [0x22,0x30,0x81,0xe0]
 @ CHECK: add  r3, r1, r2, asr #32     @ encoding: [0x42,0x30,0x81,0xe0]
 
 @------------------------------------------------------------------------------