Index: lib/Target/AMDGPU/SILowerI1Copies.cpp
===================================================================
--- lib/Target/AMDGPU/SILowerI1Copies.cpp
+++ lib/Target/AMDGPU/SILowerI1Copies.cpp
@@ -688,8 +688,9 @@
       unsigned SrcReg = MI.getOperand(1).getReg();
       assert(!MI.getOperand(1).getSubReg());
 
-      if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
-          !isLaneMaskReg(SrcReg)) {
+      if (AMDGPU::VGPR_32RegClass.contains(SrcReg) &&  
+           (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
+              !isLaneMaskReg(SrcReg))) {
         assert(TII->getRegisterInfo().getRegSizeInBits(SrcReg, *MRI) == 32);
         unsigned TmpReg = createLaneMaskReg(*MF);
         BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CMP_NE_U32_e64), TmpReg)
Index: test/CodeGen/AMDGPU/si-lower-i1-copies-vgpr.mir
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/si-lower-i1-copies-vgpr.mir
@@ -0,0 +1,31 @@
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-i1-copies -o - %s
+# GCN-LABEL: name: inserted_cmp_operand_class
+---
+name: inserted_cmp_operand_class
+tracksRegLiveness: true
+machineFunctionInfo:
+  isEntryFunction: true
+body:             |
+  bb.0:
+    successors: %bb.3
+
+    S_BRANCH %bb.3
+
+  bb.1:
+    successors: %bb.2
+
+    %0:vreg_1 = COPY %1
+
+  bb.2:
+    %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %3:sreg_64_xexec = COPY %0
+    S_ENDPGM 0
+
+  bb.3:
+    successors: %bb.1
+
+    %4:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %5:sreg_32_xm0 = S_MOV_B32 0
+    %6:sreg_64 = V_CMP_EQ_U32_e64 killed %4, killed %5, implicit $exec
+    %1:vreg_1 = COPY %6
+    S_BRANCH %bb.1