Index: llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp =================================================================== --- llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp +++ llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp @@ -1652,6 +1652,15 @@ auto NewPred = isICMP_NE ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_SGE; return new ICmpInst(NewPred, X, Zero); } + + // Restrict this fold only for single-use 'and' (PR10267). + // ((%x & C) == 0) --> %x u< (-C) iff (-C) is power of two. + if ((~(*C2) + 1).isPowerOf2()) { + Constant *NegBOC = + ConstantExpr::getNeg(cast(And->getOperand(1))); + auto NewPred = isICMP_NE ? ICmpInst::ICMP_UGE : ICmpInst::ICMP_ULT; + return new ICmpInst(NewPred, X, NegBOC); + } } // If the LHS is an 'and' of a truncate and we can widen the and/compare to @@ -2797,17 +2806,6 @@ if (C == *BOC && C.isPowerOf2()) return new ICmpInst(isICMP_NE ? ICmpInst::ICMP_EQ : ICmpInst::ICMP_NE, BO, Constant::getNullValue(RHS->getType())); - - // Don't perform the following transforms if the AND has multiple uses - if (!BO->hasOneUse()) - break; - - // ((X & ~7) == 0) --> X < 8 - if (C.isNullValue() && (~(*BOC) + 1).isPowerOf2()) { - Constant *NegBOC = ConstantExpr::getNeg(cast(BOp1)); - auto NewPred = isICMP_NE ? ICmpInst::ICMP_UGE : ICmpInst::ICMP_ULT; - return new ICmpInst(NewPred, BOp0, NegBOC); - } } break; } Index: llvm/test/Transforms/InstCombine/lshr-and-negC-icmpeq-zero.ll =================================================================== --- llvm/test/Transforms/InstCombine/lshr-and-negC-icmpeq-zero.ll +++ llvm/test/Transforms/InstCombine/lshr-and-negC-icmpeq-zero.ll @@ -9,9 +9,8 @@ define i1 @scalar_i8_lshr_and_negC_eq(i8 %x, i8 %y) { ; CHECK-LABEL: @scalar_i8_lshr_and_negC_eq( -; CHECK-NEXT: [[TMP1:%.*]] = shl i8 -4, [[Y:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[TMP2]], 0 +; CHECK-NEXT: [[LSHR:%.*]] = lshr i8 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[LSHR]], 4 ; CHECK-NEXT: ret i1 [[R]] ; %lshr = lshr i8 %x, %y @@ -22,9 +21,8 @@ define i1 @scalar_i16_lshr_and_negC_eq(i16 %x, i16 %y) { ; CHECK-LABEL: @scalar_i16_lshr_and_negC_eq( -; CHECK-NEXT: [[TMP1:%.*]] = shl i16 -128, [[Y:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[TMP2]], 0 +; CHECK-NEXT: [[LSHR:%.*]] = lshr i16 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp ult i16 [[LSHR]], 128 ; CHECK-NEXT: ret i1 [[R]] ; %lshr = lshr i16 %x, %y @@ -35,9 +33,8 @@ define i1 @scalar_i32_lshr_and_negC_eq(i32 %x, i32 %y) { ; CHECK-LABEL: @scalar_i32_lshr_and_negC_eq( -; CHECK-NEXT: [[TMP1:%.*]] = shl i32 -262144, [[Y:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[TMP2]], 0 +; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp ult i32 [[LSHR]], 262144 ; CHECK-NEXT: ret i1 [[R]] ; %lshr = lshr i32 %x, %y @@ -48,9 +45,8 @@ define i1 @scalar_i64_lshr_and_negC_eq(i64 %x, i64 %y) { ; CHECK-LABEL: @scalar_i64_lshr_and_negC_eq( -; CHECK-NEXT: [[TMP1:%.*]] = shl i64 -8589934592, [[Y:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and i64 [[TMP1]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp eq i64 [[TMP2]], 0 +; CHECK-NEXT: [[LSHR:%.*]] = lshr i64 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp ult i64 [[LSHR]], 8589934592 ; CHECK-NEXT: ret i1 [[R]] ; %lshr = lshr i64 %x, %y @@ -61,9 +57,8 @@ define i1 @scalar_i32_lshr_and_negC_ne(i32 %x, i32 %y) { ; CHECK-LABEL: @scalar_i32_lshr_and_negC_ne( -; CHECK-NEXT: [[TMP1:%.*]] = shl i32 -262144, [[Y:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[TMP2]], 0 +; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp ugt i32 [[LSHR]], 262143 ; CHECK-NEXT: ret i1 [[R]] ; %lshr = lshr i32 %x, %y @@ -76,9 +71,8 @@ define <4 x i1> @vec_4xi32_lshr_and_negC_eq(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: @vec_4xi32_lshr_and_negC_eq( -; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i32> , [[Y:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i32> [[TMP1]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i32> [[TMP2]], zeroinitializer +; CHECK-NEXT: [[LSHR:%.*]] = lshr <4 x i32> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp ult <4 x i32> [[LSHR]], ; CHECK-NEXT: ret <4 x i1> [[R]] ; %lshr = lshr <4 x i32> %x, %y Index: llvm/test/Transforms/InstCombine/pr17827.ll =================================================================== --- llvm/test/Transforms/InstCombine/pr17827.ll +++ llvm/test/Transforms/InstCombine/pr17827.ll @@ -66,8 +66,8 @@ ; Unsigned compare allows a transformation to compare against 0. define i1 @test_shift_and_cmp_changed2(i8 %p) { ; CHECK-LABEL: @test_shift_and_cmp_changed2( -; CHECK-NEXT: [[ANDP:%.*]] = and i8 [[P:%.*]], 6 -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[ANDP]], 0 +; CHECK-NEXT: [[SHLP:%.*]] = shl i8 [[P:%.*]], 5 +; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[SHLP]], 64 ; CHECK-NEXT: ret i1 [[CMP]] ; %shlp = shl i8 %p, 5 @@ -78,8 +78,8 @@ define <2 x i1> @test_shift_and_cmp_changed2_vec(<2 x i8> %p) { ; CHECK-LABEL: @test_shift_and_cmp_changed2_vec( -; CHECK-NEXT: [[ANDP:%.*]] = and <2 x i8> [[P:%.*]], -; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[ANDP]], zeroinitializer +; CHECK-NEXT: [[SHLP:%.*]] = shl <2 x i8> [[P:%.*]], +; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i8> [[SHLP]], ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; %shlp = shl <2 x i8> %p, Index: llvm/test/Transforms/InstCombine/shl-and-negC-icmpeq-zero.ll =================================================================== --- llvm/test/Transforms/InstCombine/shl-and-negC-icmpeq-zero.ll +++ llvm/test/Transforms/InstCombine/shl-and-negC-icmpeq-zero.ll @@ -9,9 +9,8 @@ define i1 @scalar_i8_shl_and_negC_eq(i8 %x, i8 %y) { ; CHECK-LABEL: @scalar_i8_shl_and_negC_eq( -; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 -4, [[Y:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[TMP2]], 0 +; CHECK-NEXT: [[SHL:%.*]] = shl i8 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[SHL]], 4 ; CHECK-NEXT: ret i1 [[R]] ; %shl = shl i8 %x, %y @@ -22,9 +21,8 @@ define i1 @scalar_i16_shl_and_negC_eq(i16 %x, i16 %y) { ; CHECK-LABEL: @scalar_i16_shl_and_negC_eq( -; CHECK-NEXT: [[TMP1:%.*]] = lshr i16 -128, [[Y:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[TMP2]], 0 +; CHECK-NEXT: [[SHL:%.*]] = shl i16 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp ult i16 [[SHL]], 128 ; CHECK-NEXT: ret i1 [[R]] ; %shl = shl i16 %x, %y @@ -35,9 +33,8 @@ define i1 @scalar_i32_shl_and_negC_eq(i32 %x, i32 %y) { ; CHECK-LABEL: @scalar_i32_shl_and_negC_eq( -; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 -262144, [[Y:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[TMP2]], 0 +; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp ult i32 [[SHL]], 262144 ; CHECK-NEXT: ret i1 [[R]] ; %shl = shl i32 %x, %y @@ -48,9 +45,8 @@ define i1 @scalar_i64_shl_and_negC_eq(i64 %x, i64 %y) { ; CHECK-LABEL: @scalar_i64_shl_and_negC_eq( -; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 -8589934592, [[Y:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and i64 [[TMP1]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp eq i64 [[TMP2]], 0 +; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp ult i64 [[SHL]], 8589934592 ; CHECK-NEXT: ret i1 [[R]] ; %shl = shl i64 %x, %y @@ -61,9 +57,8 @@ define i1 @scalar_i32_shl_and_negC_ne(i32 %x, i32 %y) { ; CHECK-LABEL: @scalar_i32_shl_and_negC_ne( -; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 -262144, [[Y:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[TMP2]], 0 +; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp ugt i32 [[SHL]], 262143 ; CHECK-NEXT: ret i1 [[R]] ; %shl = shl i32 %x, %y @@ -76,9 +71,8 @@ define <4 x i1> @vec_4xi32_shl_and_negC_eq(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: @vec_4xi32_shl_and_negC_eq( -; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i32> , [[Y:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i32> [[TMP1]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i32> [[TMP2]], zeroinitializer +; CHECK-NEXT: [[SHL:%.*]] = shl <4 x i32> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp ult <4 x i32> [[SHL]], ; CHECK-NEXT: ret <4 x i1> [[R]] ; %shl = shl <4 x i32> %x, %y