Index: include/llvm/Analysis/TargetTransformInfo.h =================================================================== --- include/llvm/Analysis/TargetTransformInfo.h +++ include/llvm/Analysis/TargetTransformInfo.h @@ -448,9 +448,7 @@ void getUnrollingPreferences(Loop *L, ScalarEvolution &, UnrollingPreferences &UP) const; - /// Attributes of a target dependent hardware loop. Here, the term 'element' - /// describes the work performed by an IR loop that has not been vectorized - /// by the compiler. + /// Attributes of a target dependent hardware loop. struct HardwareLoopInfo { HardwareLoopInfo() = delete; HardwareLoopInfo(Loop *L) : L(L) { } @@ -459,12 +457,14 @@ BranchInst *ExitBranch = nullptr; const SCEV *ExitCount = nullptr; IntegerType *CountType = nullptr; - Value *LoopDecrement = nullptr; // The maximum number of elements - // processed in the loop body. + Value *LoopDecrement = nullptr; // Decrement the loop counter by this + // value in every iteration. bool IsNestingLegal = false; // Can a hardware loop be a parent to - // another hardware loop. + // another hardware loop? bool CounterInReg = false; // Should loop counter be updated in // the loop via a phi? + bool RequiresLatch = false; // Does the loop decrement need to be + // in a loop latch? }; /// Query the target whether it would be profitable to convert the given loop Index: lib/CodeGen/HardwareLoops.cpp =================================================================== --- lib/CodeGen/HardwareLoops.cpp +++ lib/CodeGen/HardwareLoops.cpp @@ -70,6 +70,10 @@ CounterBitWidth("hardware-loop-counter-bitwidth", cl::Hidden, cl::init(32), cl::desc("Set the loop counter bitwidth")); +static cl::opt +RequiresLatch("hardware-loop-latch", cl::Hidden, cl::init(false), + cl::desc("Force loop decrement to be placed in loop latch")); + STATISTIC(NumHWLoops, "Number of loops converted to hardware loops"); namespace { @@ -235,7 +239,16 @@ for (SmallVectorImpl::iterator I = ExitingBlocks.begin(), IE = ExitingBlocks.end(); I != IE; ++I) { - const SCEV *EC = SE->getExitCount(L, *I); + BasicBlock *BB = *I; + + if (!L->isLoopLatch(BB)) { + if (RequiresLatch.getNumOccurrences() && RequiresLatch) + continue; + if (HWLoopInfo.RequiresLatch) + continue; + } + + const SCEV *EC = SE->getExitCount(L, BB); if (isa(EC)) continue; if (const SCEVConstant *ConstEC = dyn_cast(EC)) { @@ -251,7 +264,7 @@ // If this exiting block is contained in a nested loop, it is not eligible // for insertion of the branch-and-decrement since the inner loop would // end up messing up the value in the CTR. - if (!HWLoopInfo.IsNestingLegal && LI->getLoopFor(*I) != L && + if (!HWLoopInfo.IsNestingLegal && LI->getLoopFor(BB) != L && !ForceNestedLoop) continue; @@ -278,7 +291,7 @@ continue; // Make sure this blocks ends with a conditional branch. - Instruction *TI = (*I)->getTerminator(); + Instruction *TI = BB->getTerminator(); if (!TI) continue; Index: lib/Target/ARM/ARMTargetTransformInfo.cpp =================================================================== --- lib/Target/ARM/ARMTargetTransformInfo.cpp +++ lib/Target/ARM/ARMTargetTransformInfo.cpp @@ -844,6 +844,7 @@ LLVMContext &C = L->getHeader()->getContext(); HWLoopInfo.CounterInReg = true; + HWLoopInfo.RequiresLatch = true; HWLoopInfo.IsNestingLegal = false; HWLoopInfo.CountType = Type::getInt32Ty(C); HWLoopInfo.LoopDecrement = ConstantInt::get(HWLoopInfo.CountType, 1); Index: test/Transforms/HardwareLoops/ARM/structure.ll =================================================================== --- test/Transforms/HardwareLoops/ARM/structure.ll +++ test/Transforms/HardwareLoops/ARM/structure.ll @@ -135,6 +135,43 @@ ret void } +; CHECK-LABEL: not_rotated +; CHECK-NOT: call void @llvm.set.loop.iterations +; CHECK-NOT: call i32 @llvm.loop.decrement.i32 +define void @not_rotated(i32, i16* nocapture, i16 signext) { + br label %4 + +4: + %5 = phi i32 [ 0, %3 ], [ %19, %18 ] + %6 = icmp eq i32 %5, %0 + br i1 %6, label %20, label %7 + +7: + %8 = mul i32 %5, %0 + br label %9 + +9: + %10 = phi i32 [ %17, %12 ], [ 0, %7 ] + %11 = icmp eq i32 %10, %0 + br i1 %11, label %18, label %12 + +12: + %13 = add i32 %10, %8 + %14 = getelementptr inbounds i16, i16* %1, i32 %13 + %15 = load i16, i16* %14, align 2 + %16 = add i16 %15, %2 + store i16 %16, i16* %14, align 2 + %17 = add i32 %10, 1 + br label %9 + +18: + %19 = add i32 %5, 1 + br label %4 + +20: + ret void +} + declare void @llvm.set.loop.iterations.i32(i32) #0 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0 Index: test/Transforms/HardwareLoops/unconditional-latch.ll =================================================================== --- /dev/null +++ test/Transforms/HardwareLoops/unconditional-latch.ll @@ -0,0 +1,47 @@ +; RUN: opt -force-hardware-loops=true -hardware-loop-decrement=1 -hardware-loop-counter-bitwidth=32 -hardware-loops -S %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ALLOW +; RUN: opt -force-hardware-loops=true -hardware-loop-decrement=1 -hardware-loop-counter-bitwidth=32 -hardware-loop-latch=true -hardware-loops -S %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LATCH + +; CHECK-LABEL: not_rotated +; CHECK-LATCH-NOT: call void @llvm.set.loop.iterations +; CHECK-LATCH-NOT: call i1 @llvm.loop.decrement + +; CHECK: 8: +; CHECK-ALLOW: call void @llvm.set.loop.iterations.i32(i32 %4) +; CHECK-ALLOW: br label %10 +; CHECK: 10: +; CHECK-ALLOW: [[CMP:%[^ ]+]] = call i1 @llvm.loop.decrement.i32(i32 1) +; CHECK-ALLOW: br i1 [[CMP]], label %13, label %19 + +define void @not_rotated(i32, i16* nocapture, i16 signext) { + br label %4 + +4: + %5 = phi i32 [ 0, %3 ], [ %19, %18 ] + %6 = icmp eq i32 %5, %0 + br i1 %6, label %20, label %7 + +7: + %8 = mul i32 %5, %0 + br label %9 + +9: + %10 = phi i32 [ %17, %12 ], [ 0, %7 ] + %11 = icmp eq i32 %10, %0 + br i1 %11, label %18, label %12 + +12: + %13 = add i32 %10, %8 + %14 = getelementptr inbounds i16, i16* %1, i32 %13 + %15 = load i16, i16* %14, align 2 + %16 = add i16 %15, %2 + store i16 %16, i16* %14, align 2 + %17 = add i32 %10, 1 + br label %9 + +18: + %19 = add i32 %5, 1 + br label %4 + +20: + ret void +}