Index: test/TableGen/get-operand-type.td
===================================================================
--- test/TableGen/get-operand-type.td
+++ test/TableGen/get-operand-type.td
@@ -0,0 +1,41 @@
+// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s | FileCheck %s
+
+// Check that getOperandType has the expected info in it
+
+include "llvm/Target/Target.td"
+
+def archInstrInfo : InstrInfo { }
+
+def arch : Target {
+  let InstructionSet = archInstrInfo;
+}
+
+def Reg : Register<"reg">;
+def RegClass : RegisterClass<"foo", [i32], 0, (add Reg)>;
+
+def RegAndImm : Operand<i32> {
+  let MIOperandInfo = (ops RegClass:$a, i32imm:$b);
+}
+
+def InstA : Instruction {
+  let Size = 1;
+  let OutOperandList = (outs RegClass:$dst);
+  let InOperandList = (ins RegAndImm:$src);
+  field bits<8> Inst;
+  field bits<8> SoftFail = 0;
+  let Namespace = "MyNamespace";
+}
+
+def InstB : Instruction {
+  let Size = 1;
+  let OutOperandList = (outs);
+  let InOperandList = (ins unknown:$x);
+  field bits<8> Inst;
+  field bits<8> SoftFail = 0;
+  let Namespace = "MyNamespace";
+}
+
+// CHECK: #ifdef GET_INSTRINFO_OPERAND_TYPE
+// CHECK: { OperandType::RegClass, OperandType::RegClass, OperandType::i32imm, }
+// CHECK-NEXT: { -1, }
+// CHECK: #endif //GET_INSTRINFO_OPERAND_TYPE
Index: utils/TableGen/InstrInfoEmitter.cpp
===================================================================
--- utils/TableGen/InstrInfoEmitter.cpp
+++ utils/TableGen/InstrInfoEmitter.cpp
@@ -76,7 +76,9 @@
                   std::map<std::vector<Record*>, unsigned> &EL,
                   const OperandInfoMapTy &OpInfo,
                   raw_ostream &OS);
-  void emitOperandTypesEnum(raw_ostream &OS, const CodeGenTarget &Target);
+  void emitOperandTypeMappings(
+      raw_ostream &OS, const CodeGenTarget &Target,
+      ArrayRef<const CodeGenInstruction *> NumberedInstructions);
   void initOperandMapData(
             ArrayRef<const CodeGenInstruction *> NumberedInstructions,
             StringRef Namespace,
@@ -324,8 +326,9 @@
 /// Generate an enum for all the operand types for this target, under the
 /// llvm::TargetNamespace::OpTypes namespace.
 /// Operand types are all definitions derived of the Operand Target.td class.
-void InstrInfoEmitter::emitOperandTypesEnum(raw_ostream &OS,
-                                            const CodeGenTarget &Target) {
+void InstrInfoEmitter::emitOperandTypeMappings(
+    raw_ostream &OS, const CodeGenTarget &Target,
+    ArrayRef<const CodeGenInstruction *> NumberedInstructions) {
 
   StringRef Namespace = Target.getInstNamespace();
   std::vector<Record *> Operands = Records.getAllDerivedDefinitions("Operand");
@@ -349,6 +352,57 @@
   OS << "} // end namespace " << Namespace << "\n";
   OS << "} // end namespace llvm\n";
   OS << "#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM\n\n";
+
+  OS << "#ifdef GET_INSTRINFO_OPERAND_TYPE\n";
+  OS << "#undef GET_INSTRINFO_OPERAND_TYPE\n";
+  OS << "namespace llvm {\n";
+  OS << "namespace " << Namespace << " {\n";
+  OS << "LLVM_READONLY\n";
+  OS << "int getOperandType(uint16_t Opcode, uint16_t OpIdx) {\n";
+  if (!NumberedInstructions.empty()) {
+    OS << "  static const std::initializer_list<int> "
+          "OpcodeOperandTypes [] = {\n";
+    for (const CodeGenInstruction *Inst : NumberedInstructions) {
+      OS << "    { ";
+      for (const auto &Op : Inst->Operands) {
+        // Handle aggregate operands and normal operands the same way by
+        // expanding either case into a list of operands for this op.
+        std::vector<CGIOperandList::OperandInfo> OperandList;
+
+        const DagInit *MIOI = Op.MIOperandInfo;
+        if (!MIOI || MIOI->getNumArgs() == 0) {
+          // Single, anonymous, operand.
+          OperandList.push_back(Op);
+        } else {
+          for (unsigned j = 0, e = Op.MINumOperands; j != e; ++j) {
+            OperandList.push_back(Op);
+
+            auto *OpR = cast<DefInit>(MIOI->getArg(j))->getDef();
+            OperandList.back().Rec = OpR;
+          }
+        }
+
+        for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
+          Record *OpR = OperandList[j].Rec;
+          if (OpR->isSubClassOf("unknown_class")) {
+            OS << "-1";
+          } else {
+            OS << "OperandType::" << OpR->getName();
+          }
+          OS << ", ";
+        }
+      }
+      OS << "},\n";
+    }
+    OS << "  };\n";
+    OS << "  return OpcodeOperandTypes[Opcode][OpIdx];\n";
+  } else {
+    OS << "  llvm_unreachable(\"No instructions defined\");\n";
+  }
+  OS << "}\n";
+  OS << "} // end namespace " << Namespace << "\n";
+  OS << "} // end namespace llvm\n";
+  OS << "#endif //GET_INSTRINFO_OPERAND_TYPE\n\n";
 }
 
 void InstrInfoEmitter::emitMCIIHelperMethods(raw_ostream &OS,
@@ -560,7 +614,7 @@
 
   emitOperandNameMappings(OS, Target, NumberedInstructions);
 
-  emitOperandTypesEnum(OS, Target);
+  emitOperandTypeMappings(OS, Target, NumberedInstructions);
 
   emitMCIIHelperMethods(OS, TargetName);
 }