Index: lib/Target/ARM/ARM.h =================================================================== --- lib/Target/ARM/ARM.h +++ lib/Target/ARM/ARM.h @@ -56,11 +56,6 @@ void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, ARMAsmPrinter &AP); -void computeBlockSize(MachineFunction *MF, MachineBasicBlock *MBB, - BasicBlockInfo &BBI); -std::vector computeAllBlockSizes(MachineFunction *MF); - - void initializeARMParallelDSPPass(PassRegistry &); void initializeARMLoadStoreOptPass(PassRegistry &); void initializeARMPreAllocLoadStoreOptPass(PassRegistry &); Index: lib/Target/ARM/ARMBasicBlockInfo.h =================================================================== --- lib/Target/ARM/ARMBasicBlockInfo.h +++ lib/Target/ARM/ARMBasicBlockInfo.h @@ -13,12 +13,16 @@ #ifndef LLVM_LIB_TARGET_ARM_ARMBASICBLOCKINFO_H #define LLVM_LIB_TARGET_ARM_ARMBASICBLOCKINFO_H +#include "ARMBaseInstrInfo.h" +#include "ARMMachineFunctionInfo.h" #include "llvm/Support/MathExtras.h" #include #include namespace llvm { +using BBInfoVector = SmallVectorImpl; + /// UnknownPadding - Return the worst case padding that could result from /// unknown offset bits. This does not include alignment padding caused by /// known offset bits. @@ -103,6 +107,50 @@ } }; +class ARMBasicBlockUtils { + +private: + MachineFunction &MF; + bool isThumb = false; + const ARMBaseInstrInfo *TII = nullptr; + SmallVector BBInfo; + +public: + ARMBasicBlockUtils(MachineFunction &MF) : MF(MF) { + TII = + static_cast(MF.getSubtarget().getInstrInfo()); + isThumb = MF.getInfo()->isThumbFunction(); + } + + void computeAllBlockSizes() { + BBInfo.resize(MF.getNumBlockIDs()); + for (MachineBasicBlock &MBB : MF) + computeBlockSize(&MBB); + } + + void computeBlockSize(MachineBasicBlock *MBB); + + unsigned getOffsetOf(MachineInstr *MI) const; + + void adjustBBOffsetsAfter(MachineBasicBlock *MBB); + + void adjustBBSize(MachineBasicBlock *MBB, int Size) { + BBInfo[MBB->getNumber()].Size += Size; + } + + bool isBBInRange(MachineInstr *MI, MachineBasicBlock *DestBB, + unsigned MaxDisp) const; + + void insert(unsigned BBNum, BasicBlockInfo BBI) { + BBInfo.insert(BBInfo.begin() + BBNum, BBI); + } + + void clear() { BBInfo.clear(); } + + BBInfoVector &getBBInfo() { return BBInfo; } + +}; + } // end namespace llvm #endif // LLVM_LIB_TARGET_ARM_ARMBASICBLOCKINFO_H Index: lib/Target/ARM/ARMBasicBlockInfo.cpp =================================================================== --- /dev/null +++ lib/Target/ARM/ARMBasicBlockInfo.cpp @@ -0,0 +1,146 @@ +//===--- ARMBasicBlockInfo.cpp - Utilities for block sizes ---------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "ARM.h" +#include "ARMBaseInstrInfo.h" +#include "ARMBasicBlockInfo.h" +#include "ARMMachineFunctionInfo.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/TargetSubtargetInfo.h" +#include + +#define DEBUG_TYPE "arm-bb-utils" + +using namespace llvm; + +namespace llvm { + +// mayOptimizeThumb2Instruction - Returns true if optimizeThumb2Instructions +// below may shrink MI. +static bool +mayOptimizeThumb2Instruction(const MachineInstr *MI) { + switch(MI->getOpcode()) { + // optimizeThumb2Instructions. + case ARM::t2LEApcrel: + case ARM::t2LDRpci: + // optimizeThumb2Branches. + case ARM::t2B: + case ARM::t2Bcc: + case ARM::tBcc: + // optimizeThumb2JumpTables. + case ARM::t2BR_JT: + case ARM::tBR_JTr: + return true; + } + return false; +} + +void ARMBasicBlockUtils::computeBlockSize(MachineBasicBlock *MBB) { + LLVM_DEBUG(dbgs() << "computeBlockSize: " << MBB->getName() << "\n"); + BasicBlockInfo &BBI = BBInfo[MBB->getNumber()]; + BBI.Size = 0; + BBI.Unalign = 0; + BBI.PostAlign = 0; + + for (MachineInstr &I : *MBB) { + BBI.Size += TII->getInstSizeInBytes(I); + // For inline asm, getInstSizeInBytes returns a conservative estimate. + // The actual size may be smaller, but still a multiple of the instr size. + if (I.isInlineAsm()) + BBI.Unalign = isThumb ? 1 : 2; + // Also consider instructions that may be shrunk later. + else if (isThumb && mayOptimizeThumb2Instruction(&I)) + BBI.Unalign = 1; + } + + // tBR_JTr contains a .align 2 directive. + if (!MBB->empty() && MBB->back().getOpcode() == ARM::tBR_JTr) { + BBI.PostAlign = 2; + MBB->getParent()->ensureAlignment(2); + } +} + +/// getOffsetOf - Return the current offset of the specified machine instruction +/// from the start of the function. This offset changes as stuff is moved +/// around inside the function. +unsigned ARMBasicBlockUtils::getOffsetOf(MachineInstr *MI) const { + const MachineBasicBlock *MBB = MI->getParent(); + + // The offset is composed of two things: the sum of the sizes of all MBB's + // before this instruction's block, and the offset from the start of the block + // it is in. + unsigned Offset = BBInfo[MBB->getNumber()].Offset; + + // Sum instructions before MI in MBB. + for (MachineBasicBlock::const_iterator I = MBB->begin(); &*I != MI; ++I) { + assert(I != MBB->end() && "Didn't find MI in its own basic block?"); + Offset += TII->getInstSizeInBytes(*I); + } + return Offset; +} + +/// isBBInRange - Returns true if the distance between specific MI and +/// specific BB can fit in MI's displacement field. +bool ARMBasicBlockUtils::isBBInRange(MachineInstr *MI, + MachineBasicBlock *DestBB, + unsigned MaxDisp) const { + unsigned PCAdj = isThumb ? 4 : 8; + unsigned BrOffset = getOffsetOf(MI) + PCAdj; + unsigned DestOffset = BBInfo[DestBB->getNumber()].Offset; + + LLVM_DEBUG(dbgs() << "Branch of destination " << printMBBReference(*DestBB) + << " from " << printMBBReference(*MI->getParent()) + << " max delta=" << MaxDisp << " from " << getOffsetOf(MI) + << " to " << DestOffset << " offset " + << int(DestOffset - BrOffset) << "\t" << *MI); + + if (BrOffset <= DestOffset) { + // Branch before the Dest. + if (DestOffset-BrOffset <= MaxDisp) + return true; + } else { + if (BrOffset-DestOffset <= MaxDisp) + return true; + } + return false; +} + +void ARMBasicBlockUtils::adjustBBOffsetsAfter(MachineBasicBlock *BB) { + assert(BB->getParent() == &MF && + "Basic block is not a child of the current function.\n"); + + unsigned BBNum = BB->getNumber(); + LLVM_DEBUG(dbgs() << "Adjust block:\n" + << " - name: " << BB->getName() << "\n" + << " - number: " << BB->getNumber() << "\n" + << " - function: " << MF.getName() << "\n" + << " - blocks: " << MF.getNumBlockIDs() << "\n"); + + for(unsigned i = BBNum + 1, e = MF.getNumBlockIDs(); i < e; ++i) { + // Get the offset and known bits at the end of the layout predecessor. + // Include the alignment of the current block. + unsigned LogAlign = MF.getBlockNumbered(i)->getAlignment(); + unsigned Offset = BBInfo[i - 1].postOffset(LogAlign); + unsigned KnownBits = BBInfo[i - 1].postKnownBits(LogAlign); + + // This is where block i begins. Stop if the offset is already correct, + // and we have updated 2 blocks. This is the maximum number of blocks + // changed before calling this function. + if (i > BBNum + 2 && + BBInfo[i].Offset == Offset && + BBInfo[i].KnownBits == KnownBits) + break; + + BBInfo[i].Offset = Offset; + BBInfo[i].KnownBits = KnownBits; + } +} + +} // end namespace llvm Index: lib/Target/ARM/ARMComputeBlockSize.cpp =================================================================== --- lib/Target/ARM/ARMComputeBlockSize.cpp +++ /dev/null @@ -1,80 +0,0 @@ -//===--- ARMComputeBlockSize.cpp - Compute machine block sizes ------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "ARM.h" -#include "ARMBaseInstrInfo.h" -#include "ARMBasicBlockInfo.h" -#include "ARMMachineFunctionInfo.h" -#include "llvm/CodeGen/MachineBasicBlock.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/TargetSubtargetInfo.h" -#include - -using namespace llvm; - -namespace llvm { - -// mayOptimizeThumb2Instruction - Returns true if optimizeThumb2Instructions -// below may shrink MI. -static bool -mayOptimizeThumb2Instruction(const MachineInstr *MI) { - switch(MI->getOpcode()) { - // optimizeThumb2Instructions. - case ARM::t2LEApcrel: - case ARM::t2LDRpci: - // optimizeThumb2Branches. - case ARM::t2B: - case ARM::t2Bcc: - case ARM::tBcc: - // optimizeThumb2JumpTables. - case ARM::t2BR_JT: - case ARM::tBR_JTr: - return true; - } - return false; -} - -void computeBlockSize(MachineFunction *MF, MachineBasicBlock *MBB, - BasicBlockInfo &BBI) { - const ARMBaseInstrInfo *TII = - static_cast(MF->getSubtarget().getInstrInfo()); - bool isThumb = MF->getInfo()->isThumbFunction(); - BBI.Size = 0; - BBI.Unalign = 0; - BBI.PostAlign = 0; - - for (MachineInstr &I : *MBB) { - BBI.Size += TII->getInstSizeInBytes(I); - // For inline asm, getInstSizeInBytes returns a conservative estimate. - // The actual size may be smaller, but still a multiple of the instr size. - if (I.isInlineAsm()) - BBI.Unalign = isThumb ? 1 : 2; - // Also consider instructions that may be shrunk later. - else if (isThumb && mayOptimizeThumb2Instruction(&I)) - BBI.Unalign = 1; - } - - // tBR_JTr contains a .align 2 directive. - if (!MBB->empty() && MBB->back().getOpcode() == ARM::tBR_JTr) { - BBI.PostAlign = 2; - MBB->getParent()->ensureAlignment(2); - } -} - -std::vector computeAllBlockSizes(MachineFunction *MF) { - std::vector BBInfo; - BBInfo.resize(MF->getNumBlockIDs()); - - for (MachineBasicBlock &MBB : *MF) - computeBlockSize(MF, &MBB, BBInfo[MBB.getNumber()]); - - return BBInfo; -} - -} // end namespace llvm Index: lib/Target/ARM/ARMConstantIslandPass.cpp =================================================================== --- lib/Target/ARM/ARMConstantIslandPass.cpp +++ lib/Target/ARM/ARMConstantIslandPass.cpp @@ -97,7 +97,7 @@ /// CPE - A constant pool entry that has been placed somewhere, which /// tracks a list of users. class ARMConstantIslands : public MachineFunctionPass { - std::vector BBInfo; + std::unique_ptr BBUtils = nullptr; /// WaterList - A sorted list of basic blocks where islands could be placed /// (i.e. blocks that don't fall through to the following block, due @@ -243,7 +243,6 @@ void initializeFunctionInfo(const std::vector &CPEMIs); MachineBasicBlock *splitBlockBeforeInstr(MachineInstr *MI); void updateForInsertedWaterBlock(MachineBasicBlock *NewBB); - void adjustBBOffsetsAfter(MachineBasicBlock *BB); bool decrementCPEReferenceCount(unsigned CPI, MachineInstr* CPEMI); unsigned getCombinedIndex(const MachineInstr *CPEMI); int findInRangeCPEntry(CPUser& U, unsigned UserOffset); @@ -259,7 +258,6 @@ bool DoDump = false); bool isWaterInRange(unsigned UserOffset, MachineBasicBlock *Water, CPUser &U, unsigned &Growth); - bool isBBInRange(MachineInstr *MI, MachineBasicBlock *BB, unsigned Disp); bool fixupImmediateBr(ImmBranch &Br); bool fixupConditionalBr(ImmBranch &Br); bool fixupUnconditionalBr(ImmBranch &Br); @@ -274,7 +272,6 @@ MachineBasicBlock *adjustJTTargetBlockForward(MachineBasicBlock *BB, MachineBasicBlock *JTBB); - unsigned getOffsetOf(MachineInstr *MI) const; unsigned getUserOffset(CPUser&) const; void dumpBBs(); void verify(); @@ -294,10 +291,11 @@ /// verify - check BBOffsets, BBSizes, alignment of islands void ARMConstantIslands::verify() { + BBInfoVector &BBInfo = BBUtils->getBBInfo(); #ifndef NDEBUG assert(std::is_sorted(MF->begin(), MF->end(), - [this](const MachineBasicBlock &LHS, - const MachineBasicBlock &RHS) { + [&BBInfo](const MachineBasicBlock &LHS, + const MachineBasicBlock &RHS) { return BBInfo[LHS.getNumber()].postOffset() < BBInfo[RHS.getNumber()].postOffset(); })); @@ -323,6 +321,7 @@ #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) /// print block size and offset information - debugging LLVM_DUMP_METHOD void ARMConstantIslands::dumpBBs() { + BBInfoVector &BBInfo = BBUtils->getBBInfo(); LLVM_DEBUG({ for (unsigned J = 0, E = BBInfo.size(); J !=E; ++J) { const BasicBlockInfo &BBI = BBInfo[J]; @@ -339,6 +338,7 @@ bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) { MF = &mf; MCP = mf.getConstantPool(); + BBUtils = std::unique_ptr(new ARMBasicBlockUtils(mf)); LLVM_DEBUG(dbgs() << "***** ARMConstantIslands: " << MCP->getConstants().size() << " CP entries, aligned to " @@ -466,7 +466,7 @@ LLVM_DEBUG(dbgs() << '\n'; dumpBBs()); - BBInfo.clear(); + BBUtils->clear(); WaterList.clear(); CPUsers.clear(); CPEntries.clear(); @@ -683,14 +683,14 @@ void ARMConstantIslands:: initializeFunctionInfo(const std::vector &CPEMIs) { - BBInfo = computeAllBlockSizes(MF); - + BBUtils->computeAllBlockSizes(); + BBInfoVector &BBInfo = BBUtils->getBBInfo(); // The known bits of the entry block offset are determined by the function // alignment. BBInfo.front().KnownBits = MF->getAlignment(); // Compute block offsets and known bits. - adjustBBOffsetsAfter(&MF->front()); + BBUtils->adjustBBOffsetsAfter(&MF->front()); // Now go back through the instructions and build up our data structures. for (MachineBasicBlock &MBB : *MF) { @@ -855,25 +855,6 @@ } } -/// getOffsetOf - Return the current offset of the specified machine instruction -/// from the start of the function. This offset changes as stuff is moved -/// around inside the function. -unsigned ARMConstantIslands::getOffsetOf(MachineInstr *MI) const { - MachineBasicBlock *MBB = MI->getParent(); - - // The offset is composed of two things: the sum of the sizes of all MBB's - // before this instruction's block, and the offset from the start of the block - // it is in. - unsigned Offset = BBInfo[MBB->getNumber()].Offset; - - // Sum instructions before MI in MBB. - for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) { - assert(I != MBB->end() && "Didn't find MI in its own basic block?"); - Offset += TII->getInstSizeInBytes(*I); - } - return Offset; -} - /// CompareMBBNumbers - Little predicate function to sort the WaterList by MBB /// ID. static bool CompareMBBNumbers(const MachineBasicBlock *LHS, @@ -890,7 +871,7 @@ // Insert an entry into BBInfo to align it properly with the (newly // renumbered) block numbers. - BBInfo.insert(BBInfo.begin() + NewBB->getNumber(), BasicBlockInfo()); + BBUtils->insert(NewBB->getNumber(), BasicBlockInfo()); // Next, update WaterList. Specifically, we need to add NewMBB as having // available water after it. @@ -941,7 +922,7 @@ // Insert an entry into BBInfo to align it properly with the (newly // renumbered) block numbers. - BBInfo.insert(BBInfo.begin() + NewBB->getNumber(), BasicBlockInfo()); + BBUtils->insert(NewBB->getNumber(), BasicBlockInfo()); // Next, update WaterList. Specifically, we need to add OrigMBB as having // available water after it (but not if it's already there, which happens @@ -962,14 +943,14 @@ // the new jump we added. (It should be possible to do this without // recounting everything, but it's very confusing, and this is rarely // executed.) - computeBlockSize(MF, OrigBB, BBInfo[OrigBB->getNumber()]); + BBUtils->computeBlockSize(OrigBB); // Figure out how large the NewMBB is. As the second half of the original // block, it may contain a tablejump. - computeBlockSize(MF, NewBB, BBInfo[NewBB->getNumber()]); + BBUtils->computeBlockSize(NewBB); // All BBOffsets following these blocks must be modified. - adjustBBOffsetsAfter(OrigBB); + BBUtils->adjustBBOffsetsAfter(OrigBB); return NewBB; } @@ -978,7 +959,9 @@ /// displacement computation. Update U.KnownAlignment to match its current /// basic block location. unsigned ARMConstantIslands::getUserOffset(CPUser &U) const { - unsigned UserOffset = getOffsetOf(U.MI); + unsigned UserOffset = BBUtils->getOffsetOf(U.MI); + + SmallVectorImpl &BBInfo = BBUtils->getBBInfo(); const BasicBlockInfo &BBI = BBInfo[U.MI->getParent()->getNumber()]; unsigned KnownBits = BBI.internalKnownBits(); @@ -1027,6 +1010,7 @@ bool ARMConstantIslands::isWaterInRange(unsigned UserOffset, MachineBasicBlock* Water, CPUser &U, unsigned &Growth) { + BBInfoVector &BBInfo = BBUtils->getBBInfo(); unsigned CPELogAlign = getCPELogAlign(U.CPEMI); unsigned CPEOffset = BBInfo[Water->getNumber()].postOffset(CPELogAlign); unsigned NextBlockOffset, NextBlockAlignment; @@ -1067,7 +1051,8 @@ bool ARMConstantIslands::isCPEntryInRange(MachineInstr *MI, unsigned UserOffset, MachineInstr *CPEMI, unsigned MaxDisp, bool NegOk, bool DoDump) { - unsigned CPEOffset = getOffsetOf(CPEMI); + BBInfoVector &BBInfo = BBUtils->getBBInfo(); + unsigned CPEOffset = BBUtils->getOffsetOf(CPEMI); if (DoDump) { LLVM_DEBUG({ @@ -1103,28 +1088,6 @@ } #endif // NDEBUG -void ARMConstantIslands::adjustBBOffsetsAfter(MachineBasicBlock *BB) { - unsigned BBNum = BB->getNumber(); - for(unsigned i = BBNum + 1, e = MF->getNumBlockIDs(); i < e; ++i) { - // Get the offset and known bits at the end of the layout predecessor. - // Include the alignment of the current block. - unsigned LogAlign = MF->getBlockNumbered(i)->getAlignment(); - unsigned Offset = BBInfo[i - 1].postOffset(LogAlign); - unsigned KnownBits = BBInfo[i - 1].postKnownBits(LogAlign); - - // This is where block i begins. Stop if the offset is already correct, - // and we have updated 2 blocks. This is the maximum number of blocks - // changed before calling this function. - if (i > BBNum + 2 && - BBInfo[i].Offset == Offset && - BBInfo[i].KnownBits == KnownBits) - break; - - BBInfo[i].Offset = Offset; - BBInfo[i].KnownBits = KnownBits; - } -} - /// decrementCPEReferenceCount - find the constant pool entry with index CPI /// and instruction CPEMI, and decrement its refcount. If the refcount /// becomes 0 remove the entry and instruction. Returns true if we removed @@ -1240,6 +1203,7 @@ // When a CP access is out of range, BB0 may be used as water. However, // inserting islands between BB0 and BB1 makes other accesses out of range. MachineBasicBlock *UserBB = U.MI->getParent(); + BBInfoVector &BBInfo = BBUtils->getBBInfo(); unsigned MinNoSplitDisp = BBInfo[UserBB->getNumber()].postOffset(getCPELogAlign(U.CPEMI)); if (CloserWater && MinNoSplitDisp > U.getMaxDisp() / 2) @@ -1296,6 +1260,7 @@ MachineInstr *CPEMI = U.CPEMI; unsigned CPELogAlign = getCPELogAlign(CPEMI); MachineBasicBlock *UserMBB = UserMI->getParent(); + BBInfoVector &BBInfo = BBUtils->getBBInfo(); const BasicBlockInfo &UserBBI = BBInfo[UserMBB->getNumber()]; // If the block does not end in an unconditional branch already, and if the @@ -1327,8 +1292,8 @@ unsigned MaxDisp = getUnconditionalBrDisp(UncondBr); ImmBranches.push_back(ImmBranch(&UserMBB->back(), MaxDisp, false, UncondBr)); - computeBlockSize(MF, UserMBB, BBInfo[UserMBB->getNumber()]); - adjustBBOffsetsAfter(UserMBB); + BBUtils->computeBlockSize(UserMBB); + BBUtils->adjustBBOffsetsAfter(UserMBB); return; } } @@ -1537,8 +1502,8 @@ NewIsland->setAlignment(getCPELogAlign(U.CPEMI)); // Increase the size of the island block to account for the new entry. - BBInfo[NewIsland->getNumber()].Size += Size; - adjustBBOffsetsAfter(&*--NewIsland->getIterator()); + BBUtils->adjustBBSize(NewIsland, Size); + BBUtils->adjustBBOffsetsAfter(&*--NewIsland->getIterator()); // Finally, change the CPI in the instruction operand to be ID. for (unsigned i = 0, e = UserMI->getNumOperands(); i != e; ++i) @@ -1549,7 +1514,8 @@ LLVM_DEBUG( dbgs() << " Moved CPE to #" << ID << " CPI=" << CPI - << format(" offset=%#x\n", BBInfo[NewIsland->getNumber()].Offset)); + << format(" offset=%#x\n", + BBUtils->getBBInfo()[NewIsland->getNumber()].Offset)); return true; } @@ -1560,7 +1526,8 @@ MachineBasicBlock *CPEBB = CPEMI->getParent(); unsigned Size = CPEMI->getOperand(2).getImm(); CPEMI->eraseFromParent(); - BBInfo[CPEBB->getNumber()].Size -= Size; + BBInfoVector &BBInfo = BBUtils->getBBInfo(); + BBUtils->adjustBBSize(CPEBB, -Size); // All succeeding offsets have the current size value added in, fix this. if (CPEBB->empty()) { BBInfo[CPEBB->getNumber()].Size = 0; @@ -1571,7 +1538,7 @@ // Entries are sorted by descending alignment, so realign from the front. CPEBB->setAlignment(getCPELogAlign(&*CPEBB->begin())); - adjustBBOffsetsAfter(CPEBB); + BBUtils->adjustBBOffsetsAfter(CPEBB); // An island has only one predecessor BB and one successor BB. Check if // this BB's predecessor jumps directly to this BB's successor. This // shouldn't happen currently. @@ -1596,30 +1563,6 @@ return MadeChange; } -/// isBBInRange - Returns true if the distance between specific MI and -/// specific BB can fit in MI's displacement field. -bool ARMConstantIslands::isBBInRange(MachineInstr *MI,MachineBasicBlock *DestBB, - unsigned MaxDisp) { - unsigned PCAdj = isThumb ? 4 : 8; - unsigned BrOffset = getOffsetOf(MI) + PCAdj; - unsigned DestOffset = BBInfo[DestBB->getNumber()].Offset; - - LLVM_DEBUG(dbgs() << "Branch of destination " << printMBBReference(*DestBB) - << " from " << printMBBReference(*MI->getParent()) - << " max delta=" << MaxDisp << " from " << getOffsetOf(MI) - << " to " << DestOffset << " offset " - << int(DestOffset - BrOffset) << "\t" << *MI); - - if (BrOffset <= DestOffset) { - // Branch before the Dest. - if (DestOffset-BrOffset <= MaxDisp) - return true; - } else { - if (BrOffset-DestOffset <= MaxDisp) - return true; - } - return false; -} /// fixupImmediateBr - Fix up an immediate branch whose destination is too far /// away to fit in its displacement field. @@ -1628,7 +1571,7 @@ MachineBasicBlock *DestBB = MI->getOperand(0).getMBB(); // Check to see if the DestBB is already in-range. - if (isBBInRange(MI, DestBB, Br.MaxDisp)) + if (BBUtils->isBBInRange(MI, DestBB, Br.MaxDisp)) return false; if (!Br.isCond) @@ -1653,8 +1596,9 @@ // Use BL to implement far jump. Br.MaxDisp = (1 << 21) * 2; MI->setDesc(TII->get(ARM::tBfar)); + BBInfoVector &BBInfo = BBUtils->getBBInfo(); BBInfo[MBB->getNumber()].Size += 2; - adjustBBOffsetsAfter(MBB); + BBUtils->adjustBBOffsetsAfter(MBB); HasFarJump = true; ++NumUBrFixed; @@ -1701,7 +1645,7 @@ // bne L2 // b L1 MachineBasicBlock *NewDest = BMI->getOperand(0).getMBB(); - if (isBBInRange(MI, NewDest, Br.MaxDisp)) { + if (BBUtils->isBBInRange(MI, NewDest, Br.MaxDisp)) { LLVM_DEBUG( dbgs() << " Invert Bcc condition and swap its destination with " << *BMI); @@ -1718,7 +1662,7 @@ // No need for the branch to the next block. We're adding an unconditional // branch to the destination. int delta = TII->getInstSizeInBytes(MBB->back()); - BBInfo[MBB->getNumber()].Size -= delta; + BBUtils->adjustBBSize(MBB, -delta); MBB->back().eraseFromParent(); // The conditional successor will be swapped between the BBs after this, so @@ -1739,21 +1683,21 @@ BuildMI(MBB, DebugLoc(), TII->get(MI->getOpcode())) .addMBB(NextBB).addImm(CC).addReg(CCReg); Br.MI = &MBB->back(); - BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back()); + BBUtils->adjustBBSize(MBB, TII->getInstSizeInBytes(MBB->back())); if (isThumb) BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)) .addMBB(DestBB) .add(predOps(ARMCC::AL)); else BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB); - BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back()); + BBUtils->adjustBBSize(MBB, TII->getInstSizeInBytes(MBB->back())); unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr); ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr)); // Remove the old conditional branch. It may or may not still be in MBB. - BBInfo[MI->getParent()->getNumber()].Size -= TII->getInstSizeInBytes(*MI); + BBUtils->adjustBBSize(MI->getParent(), -TII->getInstSizeInBytes(*MI)); MI->eraseFromParent(); - adjustBBOffsetsAfter(MBB); + BBUtils->adjustBBOffsetsAfter(MBB); return true; } @@ -1828,8 +1772,8 @@ LLVM_DEBUG(dbgs() << "Shrink: " << *U.MI); U.MI->setDesc(TII->get(NewOpc)); MachineBasicBlock *MBB = U.MI->getParent(); - BBInfo[MBB->getNumber()].Size -= 2; - adjustBBOffsetsAfter(MBB); + BBUtils->adjustBBSize(MBB, -2); + BBUtils->adjustBBOffsetsAfter(MBB); ++NumT2CPShrunk; MadeChange = true; } @@ -1868,12 +1812,12 @@ if (NewOpc) { unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale; MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB(); - if (isBBInRange(Br.MI, DestBB, MaxOffs)) { + if (BBUtils->isBBInRange(Br.MI, DestBB, MaxOffs)) { LLVM_DEBUG(dbgs() << "Shrink branch: " << *Br.MI); Br.MI->setDesc(TII->get(NewOpc)); MachineBasicBlock *MBB = Br.MI->getParent(); - BBInfo[MBB->getNumber()].Size -= 2; - adjustBBOffsetsAfter(MBB); + BBUtils->adjustBBSize(MBB, -2); + BBUtils->adjustBBOffsetsAfter(MBB); ++NumT2BrShrunk; MadeChange = true; } @@ -1900,7 +1844,8 @@ MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB(); // Check if the distance is within 126. Subtract starting offset by 2 // because the cmp will be eliminated. - unsigned BrOffset = getOffsetOf(Br.MI) + 4 - 2; + unsigned BrOffset = BBUtils->getOffsetOf(Br.MI) + 4 - 2; + BBInfoVector &BBInfo = BBUtils->getBBInfo(); unsigned DestOffset = BBInfo[DestBB->getNumber()].Offset; if (BrOffset >= DestOffset || (DestOffset - BrOffset) > 126) continue; @@ -1937,7 +1882,7 @@ Br.MI->eraseFromParent(); Br.MI = NewBR; BBInfo[MBB->getNumber()].Size -= 2; - adjustBBOffsetsAfter(MBB); + BBUtils->adjustBBOffsetsAfter(MBB); ++NumCBZ; MadeChange = true; } @@ -2121,8 +2066,9 @@ bool ByteOk = true; bool HalfWordOk = true; - unsigned JTOffset = getOffsetOf(MI) + 4; + unsigned JTOffset = BBUtils->getOffsetOf(MI) + 4; const std::vector &JTBBs = JT[JTI].MBBs; + BBInfoVector &BBInfo = BBUtils->getBBInfo(); for (unsigned j = 0, ee = JTBBs.size(); j != ee; ++j) { MachineBasicBlock *MBB = JTBBs[j]; unsigned DstOffset = BBInfo[MBB->getNumber()].Offset; @@ -2285,7 +2231,7 @@ int Delta = OrigSize - NewSize + DeadSize; BBInfo[MBB->getNumber()].Size -= Delta; - adjustBBOffsetsAfter(MBB); + BBUtils->adjustBBOffsetsAfter(MBB); ++NumTBs; MadeChange = true; Index: lib/Target/ARM/CMakeLists.txt =================================================================== --- lib/Target/ARM/CMakeLists.txt +++ lib/Target/ARM/CMakeLists.txt @@ -22,6 +22,7 @@ ARMAsmPrinter.cpp ARMBaseInstrInfo.cpp ARMBaseRegisterInfo.cpp + ARMBasicBlockInfo.cpp ARMCallingConv.cpp ARMCallLowering.cpp ARMCodeGenPrepare.cpp @@ -57,7 +58,6 @@ Thumb2ITBlockPass.cpp Thumb2InstrInfo.cpp Thumb2SizeReduction.cpp - ARMComputeBlockSize.cpp ) add_subdirectory(AsmParser)