Index: lib/Target/AArch64/AArch64ISelLowering.cpp =================================================================== --- lib/Target/AArch64/AArch64ISelLowering.cpp +++ lib/Target/AArch64/AArch64ISelLowering.cpp @@ -1652,13 +1652,13 @@ } static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) { - if (Op.getValueType() != MVT::f16) + SDValue Op0 = Op.getOperand(0); + if (Op.getValueType() != MVT::f16 || Op0.getValueType() != MVT::i16) return SDValue(); - assert(Op.getOperand(0).getValueType() == MVT::i16); SDLoc DL(Op); - Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0)); + Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op0); Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op); return SDValue( DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op, @@ -8693,13 +8693,12 @@ static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl &Results, SelectionDAG &DAG) { - if (N->getValueType(0) != MVT::i16) - return; - SDLoc DL(N); SDValue Op = N->getOperand(0); - assert(Op.getValueType() == MVT::f16 && - "Inconsistent bitcast? Only 16-bit types should be i16 or f16"); + + if (N->getValueType(0) != MVT::i16 || Op.getValueType() != MVT::f16) + return; + Op = SDValue( DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32, DAG.getUNDEF(MVT::i32), Op, Index: test/CodeGen/AArch64/bitcast-v2i8.ll =================================================================== --- /dev/null +++ test/CodeGen/AArch64/bitcast-v2i8.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -mtriple=aarch64-apple-ios | FileCheck %s + +; Part of PR21549: going through the stack isn't ideal but is correct. + +define i16 @test_bitcast_v2i8_to_i16(<2 x i8> %a) { +; CHECK-LABEL: test_bitcast_v2i8_to_i16 +; CHECK: mov.s [[WREG_HI:w[0-9]+]], v0[1] +; CHECK-NEXT: fmov [[WREG_LO:w[0-9]+]], s0 +; CHECK-NEXT: strb [[WREG_HI]], [sp, #15] +; CHECK-NEXT: strb [[WREG_LO]], [sp, #14] +; CHECK-NEXT: ldrh w0, [sp, #14] + + %aa = bitcast <2 x i8> %a to i16 + ret i16 %aa +}